1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * PIC32 Integrated Serial Driver. 4 * 5 * Copyright (C) 2015 Microchip Technology, Inc. 6 * 7 * Authors: 8 * Sorin-Andrei Pistirica <andrei.pistirica@microchip.com> 9 */ 10 11 #include <linux/kernel.h> 12 #include <linux/platform_device.h> 13 #include <linux/of.h> 14 #include <linux/of_device.h> 15 #include <linux/of_irq.h> 16 #include <linux/of_gpio.h> 17 #include <linux/init.h> 18 #include <linux/module.h> 19 #include <linux/slab.h> 20 #include <linux/console.h> 21 #include <linux/clk.h> 22 #include <linux/tty.h> 23 #include <linux/tty_flip.h> 24 #include <linux/serial_core.h> 25 #include <linux/delay.h> 26 27 #include <asm/mach-pic32/pic32.h> 28 29 /* UART name and device definitions */ 30 #define PIC32_DEV_NAME "pic32-uart" 31 #define PIC32_MAX_UARTS 6 32 #define PIC32_SDEV_NAME "ttyPIC" 33 34 #define PIC32_UART_DFLT_BRATE 9600 35 #define PIC32_UART_TX_FIFO_DEPTH 8 36 #define PIC32_UART_RX_FIFO_DEPTH 8 37 38 #define PIC32_UART_MODE 0x00 39 #define PIC32_UART_STA 0x10 40 #define PIC32_UART_TX 0x20 41 #define PIC32_UART_RX 0x30 42 #define PIC32_UART_BRG 0x40 43 44 /* struct pic32_sport - pic32 serial port descriptor 45 * @port: uart port descriptor 46 * @idx: port index 47 * @irq_fault: virtual fault interrupt number 48 * @irq_fault_name: irq fault name 49 * @irq_rx: virtual rx interrupt number 50 * @irq_rx_name: irq rx name 51 * @irq_tx: virtual tx interrupt number 52 * @irq_tx_name: irq tx name 53 * @cts_gpiod: clear to send GPIO 54 * @dev: device descriptor 55 **/ 56 struct pic32_sport { 57 struct uart_port port; 58 int idx; 59 60 int irq_fault; 61 const char *irq_fault_name; 62 int irq_rx; 63 const char *irq_rx_name; 64 int irq_tx; 65 const char *irq_tx_name; 66 bool enable_tx_irq; 67 68 struct gpio_desc *cts_gpiod; 69 70 struct clk *clk; 71 72 struct device *dev; 73 }; 74 75 static inline struct pic32_sport *to_pic32_sport(struct uart_port *port) 76 { 77 return container_of(port, struct pic32_sport, port); 78 } 79 80 static inline void pic32_uart_writel(struct pic32_sport *sport, 81 u32 reg, u32 val) 82 { 83 __raw_writel(val, sport->port.membase + reg); 84 } 85 86 static inline u32 pic32_uart_readl(struct pic32_sport *sport, u32 reg) 87 { 88 return __raw_readl(sport->port.membase + reg); 89 } 90 91 /* pic32 uart mode register bits */ 92 #define PIC32_UART_MODE_ON BIT(15) 93 #define PIC32_UART_MODE_FRZ BIT(14) 94 #define PIC32_UART_MODE_SIDL BIT(13) 95 #define PIC32_UART_MODE_IREN BIT(12) 96 #define PIC32_UART_MODE_RTSMD BIT(11) 97 #define PIC32_UART_MODE_RESV1 BIT(10) 98 #define PIC32_UART_MODE_UEN1 BIT(9) 99 #define PIC32_UART_MODE_UEN0 BIT(8) 100 #define PIC32_UART_MODE_WAKE BIT(7) 101 #define PIC32_UART_MODE_LPBK BIT(6) 102 #define PIC32_UART_MODE_ABAUD BIT(5) 103 #define PIC32_UART_MODE_RXINV BIT(4) 104 #define PIC32_UART_MODE_BRGH BIT(3) 105 #define PIC32_UART_MODE_PDSEL1 BIT(2) 106 #define PIC32_UART_MODE_PDSEL0 BIT(1) 107 #define PIC32_UART_MODE_STSEL BIT(0) 108 109 /* pic32 uart status register bits */ 110 #define PIC32_UART_STA_UTXISEL1 BIT(15) 111 #define PIC32_UART_STA_UTXISEL0 BIT(14) 112 #define PIC32_UART_STA_UTXINV BIT(13) 113 #define PIC32_UART_STA_URXEN BIT(12) 114 #define PIC32_UART_STA_UTXBRK BIT(11) 115 #define PIC32_UART_STA_UTXEN BIT(10) 116 #define PIC32_UART_STA_UTXBF BIT(9) 117 #define PIC32_UART_STA_TRMT BIT(8) 118 #define PIC32_UART_STA_URXISEL1 BIT(7) 119 #define PIC32_UART_STA_URXISEL0 BIT(6) 120 #define PIC32_UART_STA_ADDEN BIT(5) 121 #define PIC32_UART_STA_RIDLE BIT(4) 122 #define PIC32_UART_STA_PERR BIT(3) 123 #define PIC32_UART_STA_FERR BIT(2) 124 #define PIC32_UART_STA_OERR BIT(1) 125 #define PIC32_UART_STA_URXDA BIT(0) 126 127 /* pic32_sport pointer for console use */ 128 static struct pic32_sport *pic32_sports[PIC32_MAX_UARTS]; 129 130 static inline void pic32_wait_deplete_txbuf(struct pic32_sport *sport) 131 { 132 /* wait for tx empty, otherwise chars will be lost or corrupted */ 133 while (!(pic32_uart_readl(sport, PIC32_UART_STA) & PIC32_UART_STA_TRMT)) 134 udelay(1); 135 } 136 137 /* serial core request to check if uart tx buffer is empty */ 138 static unsigned int pic32_uart_tx_empty(struct uart_port *port) 139 { 140 struct pic32_sport *sport = to_pic32_sport(port); 141 u32 val = pic32_uart_readl(sport, PIC32_UART_STA); 142 143 return (val & PIC32_UART_STA_TRMT) ? 1 : 0; 144 } 145 146 /* serial core request to set UART outputs */ 147 static void pic32_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 148 { 149 struct pic32_sport *sport = to_pic32_sport(port); 150 151 /* set loopback mode */ 152 if (mctrl & TIOCM_LOOP) 153 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE), 154 PIC32_UART_MODE_LPBK); 155 else 156 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE), 157 PIC32_UART_MODE_LPBK); 158 } 159 160 /* serial core request to return the state of misc UART input pins */ 161 static unsigned int pic32_uart_get_mctrl(struct uart_port *port) 162 { 163 struct pic32_sport *sport = to_pic32_sport(port); 164 unsigned int mctrl = 0; 165 166 /* get the state of CTS input pin for this port */ 167 if (!sport->cts_gpiod) 168 mctrl |= TIOCM_CTS; 169 else if (gpiod_get_value(sport->cts_gpiod)) 170 mctrl |= TIOCM_CTS; 171 172 /* DSR and CD are not supported in PIC32, so return 1 173 * RI is not supported in PIC32, so return 0 174 */ 175 mctrl |= TIOCM_CD; 176 mctrl |= TIOCM_DSR; 177 178 return mctrl; 179 } 180 181 /* stop tx and start tx are not called in pairs, therefore a flag indicates 182 * the status of irq to control the irq-depth. 183 */ 184 static inline void pic32_uart_irqtxen(struct pic32_sport *sport, u8 en) 185 { 186 if (en && !sport->enable_tx_irq) { 187 enable_irq(sport->irq_tx); 188 sport->enable_tx_irq = true; 189 } else if (!en && sport->enable_tx_irq) { 190 /* use disable_irq_nosync() and not disable_irq() to avoid self 191 * imposed deadlock by not waiting for irq handler to end, 192 * since this callback is called from interrupt context. 193 */ 194 disable_irq_nosync(sport->irq_tx); 195 sport->enable_tx_irq = false; 196 } 197 } 198 199 /* serial core request to disable tx ASAP (used for flow control) */ 200 static void pic32_uart_stop_tx(struct uart_port *port) 201 { 202 struct pic32_sport *sport = to_pic32_sport(port); 203 204 if (!(pic32_uart_readl(sport, PIC32_UART_MODE) & PIC32_UART_MODE_ON)) 205 return; 206 207 if (!(pic32_uart_readl(sport, PIC32_UART_STA) & PIC32_UART_STA_UTXEN)) 208 return; 209 210 /* wait for tx empty */ 211 pic32_wait_deplete_txbuf(sport); 212 213 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA), 214 PIC32_UART_STA_UTXEN); 215 pic32_uart_irqtxen(sport, 0); 216 } 217 218 /* serial core request to (re)enable tx */ 219 static void pic32_uart_start_tx(struct uart_port *port) 220 { 221 struct pic32_sport *sport = to_pic32_sport(port); 222 223 pic32_uart_irqtxen(sport, 1); 224 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_STA), 225 PIC32_UART_STA_UTXEN); 226 } 227 228 /* serial core request to stop rx, called before port shutdown */ 229 static void pic32_uart_stop_rx(struct uart_port *port) 230 { 231 struct pic32_sport *sport = to_pic32_sport(port); 232 233 /* disable rx interrupts */ 234 disable_irq(sport->irq_rx); 235 236 /* receiver Enable bit OFF */ 237 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA), 238 PIC32_UART_STA_URXEN); 239 } 240 241 /* serial core request to start/stop emitting break char */ 242 static void pic32_uart_break_ctl(struct uart_port *port, int ctl) 243 { 244 struct pic32_sport *sport = to_pic32_sport(port); 245 unsigned long flags; 246 247 spin_lock_irqsave(&port->lock, flags); 248 249 if (ctl) 250 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_STA), 251 PIC32_UART_STA_UTXBRK); 252 else 253 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA), 254 PIC32_UART_STA_UTXBRK); 255 256 spin_unlock_irqrestore(&port->lock, flags); 257 } 258 259 /* get port type in string format */ 260 static const char *pic32_uart_type(struct uart_port *port) 261 { 262 return (port->type == PORT_PIC32) ? PIC32_DEV_NAME : NULL; 263 } 264 265 /* read all chars in rx fifo and send them to core */ 266 static void pic32_uart_do_rx(struct uart_port *port) 267 { 268 struct pic32_sport *sport = to_pic32_sport(port); 269 struct tty_port *tty; 270 unsigned int max_count; 271 272 /* limit number of char read in interrupt, should not be 273 * higher than fifo size anyway since we're much faster than 274 * serial port 275 */ 276 max_count = PIC32_UART_RX_FIFO_DEPTH; 277 278 spin_lock(&port->lock); 279 280 tty = &port->state->port; 281 282 do { 283 u32 sta_reg, c; 284 char flag; 285 286 /* get overrun/fifo empty information from status register */ 287 sta_reg = pic32_uart_readl(sport, PIC32_UART_STA); 288 if (unlikely(sta_reg & PIC32_UART_STA_OERR)) { 289 290 /* fifo reset is required to clear interrupt */ 291 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA), 292 PIC32_UART_STA_OERR); 293 294 port->icount.overrun++; 295 tty_insert_flip_char(tty, 0, TTY_OVERRUN); 296 } 297 298 /* Can at least one more character can be read? */ 299 if (!(sta_reg & PIC32_UART_STA_URXDA)) 300 break; 301 302 /* read the character and increment the rx counter */ 303 c = pic32_uart_readl(sport, PIC32_UART_RX); 304 305 port->icount.rx++; 306 flag = TTY_NORMAL; 307 c &= 0xff; 308 309 if (unlikely((sta_reg & PIC32_UART_STA_PERR) || 310 (sta_reg & PIC32_UART_STA_FERR))) { 311 312 /* do stats first */ 313 if (sta_reg & PIC32_UART_STA_PERR) 314 port->icount.parity++; 315 if (sta_reg & PIC32_UART_STA_FERR) 316 port->icount.frame++; 317 318 /* update flag wrt read_status_mask */ 319 sta_reg &= port->read_status_mask; 320 321 if (sta_reg & PIC32_UART_STA_FERR) 322 flag = TTY_FRAME; 323 if (sta_reg & PIC32_UART_STA_PERR) 324 flag = TTY_PARITY; 325 } 326 327 if (uart_handle_sysrq_char(port, c)) 328 continue; 329 330 if ((sta_reg & port->ignore_status_mask) == 0) 331 tty_insert_flip_char(tty, c, flag); 332 333 } while (--max_count); 334 335 spin_unlock(&port->lock); 336 337 tty_flip_buffer_push(tty); 338 } 339 340 /* fill tx fifo with chars to send, stop when fifo is about to be full 341 * or when all chars have been sent. 342 */ 343 static void pic32_uart_do_tx(struct uart_port *port) 344 { 345 struct pic32_sport *sport = to_pic32_sport(port); 346 struct circ_buf *xmit = &port->state->xmit; 347 unsigned int max_count = PIC32_UART_TX_FIFO_DEPTH; 348 349 if (port->x_char) { 350 pic32_uart_writel(sport, PIC32_UART_TX, port->x_char); 351 port->icount.tx++; 352 port->x_char = 0; 353 return; 354 } 355 356 if (uart_tx_stopped(port)) { 357 pic32_uart_stop_tx(port); 358 return; 359 } 360 361 if (uart_circ_empty(xmit)) 362 goto txq_empty; 363 364 /* keep stuffing chars into uart tx buffer 365 * 1) until uart fifo is full 366 * or 367 * 2) until the circ buffer is empty 368 * (all chars have been sent) 369 * or 370 * 3) until the max count is reached 371 * (prevents lingering here for too long in certain cases) 372 */ 373 while (!(PIC32_UART_STA_UTXBF & 374 pic32_uart_readl(sport, PIC32_UART_STA))) { 375 unsigned int c = xmit->buf[xmit->tail]; 376 377 pic32_uart_writel(sport, PIC32_UART_TX, c); 378 379 uart_xmit_advance(port, 1); 380 if (uart_circ_empty(xmit)) 381 break; 382 if (--max_count == 0) 383 break; 384 } 385 386 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 387 uart_write_wakeup(port); 388 389 if (uart_circ_empty(xmit)) 390 goto txq_empty; 391 392 return; 393 394 txq_empty: 395 pic32_uart_irqtxen(sport, 0); 396 } 397 398 /* RX interrupt handler */ 399 static irqreturn_t pic32_uart_rx_interrupt(int irq, void *dev_id) 400 { 401 struct uart_port *port = dev_id; 402 403 pic32_uart_do_rx(port); 404 405 return IRQ_HANDLED; 406 } 407 408 /* TX interrupt handler */ 409 static irqreturn_t pic32_uart_tx_interrupt(int irq, void *dev_id) 410 { 411 struct uart_port *port = dev_id; 412 unsigned long flags; 413 414 spin_lock_irqsave(&port->lock, flags); 415 pic32_uart_do_tx(port); 416 spin_unlock_irqrestore(&port->lock, flags); 417 418 return IRQ_HANDLED; 419 } 420 421 /* FAULT interrupt handler */ 422 static irqreturn_t pic32_uart_fault_interrupt(int irq, void *dev_id) 423 { 424 /* do nothing: pic32_uart_do_rx() handles faults. */ 425 return IRQ_HANDLED; 426 } 427 428 /* enable rx & tx operation on uart */ 429 static void pic32_uart_en_and_unmask(struct uart_port *port) 430 { 431 struct pic32_sport *sport = to_pic32_sport(port); 432 433 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_STA), 434 PIC32_UART_STA_UTXEN | PIC32_UART_STA_URXEN); 435 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE), 436 PIC32_UART_MODE_ON); 437 } 438 439 /* disable rx & tx operation on uart */ 440 static void pic32_uart_dsbl_and_mask(struct uart_port *port) 441 { 442 struct pic32_sport *sport = to_pic32_sport(port); 443 444 /* wait for tx empty, otherwise chars will be lost or corrupted */ 445 pic32_wait_deplete_txbuf(sport); 446 447 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA), 448 PIC32_UART_STA_UTXEN | PIC32_UART_STA_URXEN); 449 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE), 450 PIC32_UART_MODE_ON); 451 } 452 453 /* serial core request to initialize uart and start rx operation */ 454 static int pic32_uart_startup(struct uart_port *port) 455 { 456 struct pic32_sport *sport = to_pic32_sport(port); 457 u32 dflt_baud = (port->uartclk / PIC32_UART_DFLT_BRATE / 16) - 1; 458 unsigned long flags; 459 int ret; 460 461 local_irq_save(flags); 462 463 ret = clk_prepare_enable(sport->clk); 464 if (ret) { 465 local_irq_restore(flags); 466 goto out_done; 467 } 468 469 /* clear status and mode registers */ 470 pic32_uart_writel(sport, PIC32_UART_MODE, 0); 471 pic32_uart_writel(sport, PIC32_UART_STA, 0); 472 473 /* disable uart and mask all interrupts */ 474 pic32_uart_dsbl_and_mask(port); 475 476 /* set default baud */ 477 pic32_uart_writel(sport, PIC32_UART_BRG, dflt_baud); 478 479 local_irq_restore(flags); 480 481 /* Each UART of a PIC32 has three interrupts therefore, 482 * we setup driver to register the 3 irqs for the device. 483 * 484 * For each irq request_irq() is called with interrupt disabled. 485 * And the irq is enabled as soon as we are ready to handle them. 486 */ 487 sport->enable_tx_irq = false; 488 489 sport->irq_fault_name = kasprintf(GFP_KERNEL, "%s%d-fault", 490 pic32_uart_type(port), 491 sport->idx); 492 if (!sport->irq_fault_name) { 493 dev_err(port->dev, "%s: kasprintf err!", __func__); 494 ret = -ENOMEM; 495 goto out_disable_clk; 496 } 497 irq_set_status_flags(sport->irq_fault, IRQ_NOAUTOEN); 498 ret = request_irq(sport->irq_fault, pic32_uart_fault_interrupt, 499 IRQF_NO_THREAD, sport->irq_fault_name, port); 500 if (ret) { 501 dev_err(port->dev, "%s: request irq(%d) err! ret:%d name:%s\n", 502 __func__, sport->irq_fault, ret, 503 pic32_uart_type(port)); 504 goto out_f; 505 } 506 507 sport->irq_rx_name = kasprintf(GFP_KERNEL, "%s%d-rx", 508 pic32_uart_type(port), 509 sport->idx); 510 if (!sport->irq_rx_name) { 511 dev_err(port->dev, "%s: kasprintf err!", __func__); 512 ret = -ENOMEM; 513 goto out_f; 514 } 515 irq_set_status_flags(sport->irq_rx, IRQ_NOAUTOEN); 516 ret = request_irq(sport->irq_rx, pic32_uart_rx_interrupt, 517 IRQF_NO_THREAD, sport->irq_rx_name, port); 518 if (ret) { 519 dev_err(port->dev, "%s: request irq(%d) err! ret:%d name:%s\n", 520 __func__, sport->irq_rx, ret, 521 pic32_uart_type(port)); 522 goto out_r; 523 } 524 525 sport->irq_tx_name = kasprintf(GFP_KERNEL, "%s%d-tx", 526 pic32_uart_type(port), 527 sport->idx); 528 if (!sport->irq_tx_name) { 529 dev_err(port->dev, "%s: kasprintf err!", __func__); 530 ret = -ENOMEM; 531 goto out_r; 532 } 533 irq_set_status_flags(sport->irq_tx, IRQ_NOAUTOEN); 534 ret = request_irq(sport->irq_tx, pic32_uart_tx_interrupt, 535 IRQF_NO_THREAD, sport->irq_tx_name, port); 536 if (ret) { 537 dev_err(port->dev, "%s: request irq(%d) err! ret:%d name:%s\n", 538 __func__, sport->irq_tx, ret, 539 pic32_uart_type(port)); 540 goto out_t; 541 } 542 543 local_irq_save(flags); 544 545 /* set rx interrupt on first receive */ 546 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA), 547 PIC32_UART_STA_URXISEL1 | PIC32_UART_STA_URXISEL0); 548 549 /* set interrupt on empty */ 550 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA), 551 PIC32_UART_STA_UTXISEL1); 552 553 /* enable all interrupts and eanable uart */ 554 pic32_uart_en_and_unmask(port); 555 556 local_irq_restore(flags); 557 558 enable_irq(sport->irq_rx); 559 560 return 0; 561 562 out_t: 563 free_irq(sport->irq_tx, port); 564 kfree(sport->irq_tx_name); 565 out_r: 566 free_irq(sport->irq_rx, port); 567 kfree(sport->irq_rx_name); 568 out_f: 569 free_irq(sport->irq_fault, port); 570 kfree(sport->irq_fault_name); 571 out_disable_clk: 572 clk_disable_unprepare(sport->clk); 573 out_done: 574 return ret; 575 } 576 577 /* serial core request to flush & disable uart */ 578 static void pic32_uart_shutdown(struct uart_port *port) 579 { 580 struct pic32_sport *sport = to_pic32_sport(port); 581 unsigned long flags; 582 583 /* disable uart */ 584 spin_lock_irqsave(&port->lock, flags); 585 pic32_uart_dsbl_and_mask(port); 586 spin_unlock_irqrestore(&port->lock, flags); 587 clk_disable_unprepare(sport->clk); 588 589 /* free all 3 interrupts for this UART */ 590 free_irq(sport->irq_fault, port); 591 kfree(sport->irq_fault_name); 592 free_irq(sport->irq_tx, port); 593 kfree(sport->irq_tx_name); 594 free_irq(sport->irq_rx, port); 595 kfree(sport->irq_rx_name); 596 } 597 598 /* serial core request to change current uart setting */ 599 static void pic32_uart_set_termios(struct uart_port *port, 600 struct ktermios *new, 601 const struct ktermios *old) 602 { 603 struct pic32_sport *sport = to_pic32_sport(port); 604 unsigned int baud; 605 unsigned int quot; 606 unsigned long flags; 607 608 spin_lock_irqsave(&port->lock, flags); 609 610 /* disable uart and mask all interrupts while changing speed */ 611 pic32_uart_dsbl_and_mask(port); 612 613 /* stop bit options */ 614 if (new->c_cflag & CSTOPB) 615 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE), 616 PIC32_UART_MODE_STSEL); 617 else 618 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE), 619 PIC32_UART_MODE_STSEL); 620 621 /* parity options */ 622 if (new->c_cflag & PARENB) { 623 if (new->c_cflag & PARODD) { 624 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE), 625 PIC32_UART_MODE_PDSEL1); 626 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE), 627 PIC32_UART_MODE_PDSEL0); 628 } else { 629 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE), 630 PIC32_UART_MODE_PDSEL0); 631 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE), 632 PIC32_UART_MODE_PDSEL1); 633 } 634 } else { 635 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE), 636 PIC32_UART_MODE_PDSEL1 | 637 PIC32_UART_MODE_PDSEL0); 638 } 639 /* if hw flow ctrl, then the pins must be specified in device tree */ 640 if ((new->c_cflag & CRTSCTS) && sport->cts_gpiod) { 641 /* enable hardware flow control */ 642 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE), 643 PIC32_UART_MODE_UEN1); 644 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE), 645 PIC32_UART_MODE_UEN0); 646 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE), 647 PIC32_UART_MODE_RTSMD); 648 } else { 649 /* disable hardware flow control */ 650 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE), 651 PIC32_UART_MODE_UEN1); 652 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE), 653 PIC32_UART_MODE_UEN0); 654 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE), 655 PIC32_UART_MODE_RTSMD); 656 } 657 658 /* Always 8-bit */ 659 new->c_cflag |= CS8; 660 661 /* Mark/Space parity is not supported */ 662 new->c_cflag &= ~CMSPAR; 663 664 /* update baud */ 665 baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16); 666 quot = uart_get_divisor(port, baud) - 1; 667 pic32_uart_writel(sport, PIC32_UART_BRG, quot); 668 uart_update_timeout(port, new->c_cflag, baud); 669 670 if (tty_termios_baud_rate(new)) 671 tty_termios_encode_baud_rate(new, baud, baud); 672 673 /* enable uart */ 674 pic32_uart_en_and_unmask(port); 675 676 spin_unlock_irqrestore(&port->lock, flags); 677 } 678 679 /* serial core request to claim uart iomem */ 680 static int pic32_uart_request_port(struct uart_port *port) 681 { 682 struct platform_device *pdev = to_platform_device(port->dev); 683 struct resource *res_mem; 684 685 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 686 if (unlikely(!res_mem)) 687 return -EINVAL; 688 689 if (!request_mem_region(port->mapbase, resource_size(res_mem), 690 "pic32_uart_mem")) 691 return -EBUSY; 692 693 port->membase = devm_ioremap(port->dev, port->mapbase, 694 resource_size(res_mem)); 695 if (!port->membase) { 696 dev_err(port->dev, "Unable to map registers\n"); 697 release_mem_region(port->mapbase, resource_size(res_mem)); 698 return -ENOMEM; 699 } 700 701 return 0; 702 } 703 704 /* serial core request to release uart iomem */ 705 static void pic32_uart_release_port(struct uart_port *port) 706 { 707 struct platform_device *pdev = to_platform_device(port->dev); 708 struct resource *res_mem; 709 unsigned int res_size; 710 711 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 712 if (unlikely(!res_mem)) 713 return; 714 res_size = resource_size(res_mem); 715 716 release_mem_region(port->mapbase, res_size); 717 } 718 719 /* serial core request to do any port required auto-configuration */ 720 static void pic32_uart_config_port(struct uart_port *port, int flags) 721 { 722 if (flags & UART_CONFIG_TYPE) { 723 if (pic32_uart_request_port(port)) 724 return; 725 port->type = PORT_PIC32; 726 } 727 } 728 729 /* serial core request to check that port information in serinfo are suitable */ 730 static int pic32_uart_verify_port(struct uart_port *port, 731 struct serial_struct *serinfo) 732 { 733 if (port->type != PORT_PIC32) 734 return -EINVAL; 735 if (port->irq != serinfo->irq) 736 return -EINVAL; 737 if (port->iotype != serinfo->io_type) 738 return -EINVAL; 739 if (port->mapbase != (unsigned long)serinfo->iomem_base) 740 return -EINVAL; 741 742 return 0; 743 } 744 745 /* serial core callbacks */ 746 static const struct uart_ops pic32_uart_ops = { 747 .tx_empty = pic32_uart_tx_empty, 748 .get_mctrl = pic32_uart_get_mctrl, 749 .set_mctrl = pic32_uart_set_mctrl, 750 .start_tx = pic32_uart_start_tx, 751 .stop_tx = pic32_uart_stop_tx, 752 .stop_rx = pic32_uart_stop_rx, 753 .break_ctl = pic32_uart_break_ctl, 754 .startup = pic32_uart_startup, 755 .shutdown = pic32_uart_shutdown, 756 .set_termios = pic32_uart_set_termios, 757 .type = pic32_uart_type, 758 .release_port = pic32_uart_release_port, 759 .request_port = pic32_uart_request_port, 760 .config_port = pic32_uart_config_port, 761 .verify_port = pic32_uart_verify_port, 762 }; 763 764 #ifdef CONFIG_SERIAL_PIC32_CONSOLE 765 /* output given char */ 766 static void pic32_console_putchar(struct uart_port *port, unsigned char ch) 767 { 768 struct pic32_sport *sport = to_pic32_sport(port); 769 770 if (!(pic32_uart_readl(sport, PIC32_UART_MODE) & PIC32_UART_MODE_ON)) 771 return; 772 773 if (!(pic32_uart_readl(sport, PIC32_UART_STA) & PIC32_UART_STA_UTXEN)) 774 return; 775 776 /* wait for tx empty */ 777 pic32_wait_deplete_txbuf(sport); 778 779 pic32_uart_writel(sport, PIC32_UART_TX, ch & 0xff); 780 } 781 782 /* console core request to output given string */ 783 static void pic32_console_write(struct console *co, const char *s, 784 unsigned int count) 785 { 786 struct pic32_sport *sport = pic32_sports[co->index]; 787 788 /* call uart helper to deal with \r\n */ 789 uart_console_write(&sport->port, s, count, pic32_console_putchar); 790 } 791 792 /* console core request to setup given console, find matching uart 793 * port and setup it. 794 */ 795 static int pic32_console_setup(struct console *co, char *options) 796 { 797 struct pic32_sport *sport; 798 int baud = 115200; 799 int bits = 8; 800 int parity = 'n'; 801 int flow = 'n'; 802 int ret = 0; 803 804 if (unlikely(co->index < 0 || co->index >= PIC32_MAX_UARTS)) 805 return -ENODEV; 806 807 sport = pic32_sports[co->index]; 808 if (!sport) 809 return -ENODEV; 810 811 ret = clk_prepare_enable(sport->clk); 812 if (ret) 813 return ret; 814 815 if (options) 816 uart_parse_options(options, &baud, &parity, &bits, &flow); 817 818 return uart_set_options(&sport->port, co, baud, parity, bits, flow); 819 } 820 821 static struct uart_driver pic32_uart_driver; 822 static struct console pic32_console = { 823 .name = PIC32_SDEV_NAME, 824 .write = pic32_console_write, 825 .device = uart_console_device, 826 .setup = pic32_console_setup, 827 .flags = CON_PRINTBUFFER, 828 .index = -1, 829 .data = &pic32_uart_driver, 830 }; 831 #define PIC32_SCONSOLE (&pic32_console) 832 833 static int __init pic32_console_init(void) 834 { 835 register_console(&pic32_console); 836 return 0; 837 } 838 console_initcall(pic32_console_init); 839 840 /* 841 * Late console initialization. 842 */ 843 static int __init pic32_late_console_init(void) 844 { 845 if (!console_is_registered(&pic32_console)) 846 register_console(&pic32_console); 847 848 return 0; 849 } 850 851 core_initcall(pic32_late_console_init); 852 853 #else 854 #define PIC32_SCONSOLE NULL 855 #endif 856 857 static struct uart_driver pic32_uart_driver = { 858 .owner = THIS_MODULE, 859 .driver_name = PIC32_DEV_NAME, 860 .dev_name = PIC32_SDEV_NAME, 861 .nr = PIC32_MAX_UARTS, 862 .cons = PIC32_SCONSOLE, 863 }; 864 865 static int pic32_uart_probe(struct platform_device *pdev) 866 { 867 struct device *dev = &pdev->dev; 868 struct device_node *np = dev->of_node; 869 struct pic32_sport *sport; 870 int uart_idx = 0; 871 struct resource *res_mem; 872 struct uart_port *port; 873 int ret; 874 875 uart_idx = of_alias_get_id(np, "serial"); 876 if (uart_idx < 0 || uart_idx >= PIC32_MAX_UARTS) 877 return -EINVAL; 878 879 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 880 if (!res_mem) 881 return -EINVAL; 882 883 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); 884 if (!sport) 885 return -ENOMEM; 886 887 sport->idx = uart_idx; 888 sport->irq_fault = irq_of_parse_and_map(np, 0); 889 sport->irq_rx = irq_of_parse_and_map(np, 1); 890 sport->irq_tx = irq_of_parse_and_map(np, 2); 891 sport->clk = devm_clk_get(&pdev->dev, NULL); 892 sport->dev = &pdev->dev; 893 894 /* Hardware flow control: gpios 895 * !Note: Basically, CTS is needed for reading the status. 896 */ 897 sport->cts_gpiod = devm_gpiod_get_optional(dev, "cts", GPIOD_IN); 898 if (IS_ERR(sport->cts_gpiod)) 899 return dev_err_probe(dev, PTR_ERR(sport->cts_gpiod), "error requesting CTS GPIO\n"); 900 gpiod_set_consumer_name(sport->cts_gpiod, "CTS"); 901 902 pic32_sports[uart_idx] = sport; 903 port = &sport->port; 904 port->iotype = UPIO_MEM; 905 port->mapbase = res_mem->start; 906 port->ops = &pic32_uart_ops; 907 port->flags = UPF_BOOT_AUTOCONF; 908 port->dev = &pdev->dev; 909 port->fifosize = PIC32_UART_TX_FIFO_DEPTH; 910 port->uartclk = clk_get_rate(sport->clk); 911 port->line = uart_idx; 912 913 ret = uart_add_one_port(&pic32_uart_driver, port); 914 if (ret) { 915 port->membase = NULL; 916 dev_err(port->dev, "%s: uart add port error!\n", __func__); 917 goto err; 918 } 919 920 #ifdef CONFIG_SERIAL_PIC32_CONSOLE 921 if (uart_console_registered(port)) { 922 /* The peripheral clock has been enabled by console_setup, 923 * so disable it till the port is used. 924 */ 925 clk_disable_unprepare(sport->clk); 926 } 927 #endif 928 929 platform_set_drvdata(pdev, port); 930 931 dev_info(&pdev->dev, "%s: uart(%d) driver initialized.\n", 932 __func__, uart_idx); 933 934 return 0; 935 err: 936 /* automatic unroll of sport and gpios */ 937 return ret; 938 } 939 940 static int pic32_uart_remove(struct platform_device *pdev) 941 { 942 struct uart_port *port = platform_get_drvdata(pdev); 943 struct pic32_sport *sport = to_pic32_sport(port); 944 945 uart_remove_one_port(&pic32_uart_driver, port); 946 clk_disable_unprepare(sport->clk); 947 platform_set_drvdata(pdev, NULL); 948 pic32_sports[sport->idx] = NULL; 949 950 /* automatic unroll of sport and gpios */ 951 return 0; 952 } 953 954 static const struct of_device_id pic32_serial_dt_ids[] = { 955 { .compatible = "microchip,pic32mzda-uart" }, 956 { /* sentinel */ } 957 }; 958 MODULE_DEVICE_TABLE(of, pic32_serial_dt_ids); 959 960 static struct platform_driver pic32_uart_platform_driver = { 961 .probe = pic32_uart_probe, 962 .remove = pic32_uart_remove, 963 .driver = { 964 .name = PIC32_DEV_NAME, 965 .of_match_table = of_match_ptr(pic32_serial_dt_ids), 966 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_PIC32), 967 }, 968 }; 969 970 static int __init pic32_uart_init(void) 971 { 972 int ret; 973 974 ret = uart_register_driver(&pic32_uart_driver); 975 if (ret) { 976 pr_err("failed to register %s:%d\n", 977 pic32_uart_driver.driver_name, ret); 978 return ret; 979 } 980 981 ret = platform_driver_register(&pic32_uart_platform_driver); 982 if (ret) { 983 pr_err("fail to register pic32 uart\n"); 984 uart_unregister_driver(&pic32_uart_driver); 985 } 986 987 return ret; 988 } 989 arch_initcall(pic32_uart_init); 990 991 static void __exit pic32_uart_exit(void) 992 { 993 #ifdef CONFIG_SERIAL_PIC32_CONSOLE 994 unregister_console(&pic32_console); 995 #endif 996 platform_driver_unregister(&pic32_uart_platform_driver); 997 uart_unregister_driver(&pic32_uart_driver); 998 } 999 module_exit(pic32_uart_exit); 1000 1001 MODULE_AUTHOR("Sorin-Andrei Pistirica <andrei.pistirica@microchip.com>"); 1002 MODULE_DESCRIPTION("Microchip PIC32 integrated serial port driver"); 1003 MODULE_LICENSE("GPL v2"); 1004