1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * SC16IS7xx tty serial driver - Copyright (C) 2014 GridPoint 4 * Author: Jon Ringle <jringle@gridpoint.com> 5 * 6 * Based on max310x.c, by Alexander Shiyan <shc_work@mail.ru> 7 */ 8 9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 10 11 #include <linux/bitops.h> 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/device.h> 15 #include <linux/gpio/driver.h> 16 #include <linux/i2c.h> 17 #include <linux/mod_devicetable.h> 18 #include <linux/module.h> 19 #include <linux/property.h> 20 #include <linux/regmap.h> 21 #include <linux/serial_core.h> 22 #include <linux/serial.h> 23 #include <linux/tty.h> 24 #include <linux/tty_flip.h> 25 #include <linux/spi/spi.h> 26 #include <linux/uaccess.h> 27 #include <uapi/linux/sched/types.h> 28 29 #define SC16IS7XX_NAME "sc16is7xx" 30 #define SC16IS7XX_MAX_DEVS 8 31 32 /* SC16IS7XX register definitions */ 33 #define SC16IS7XX_RHR_REG (0x00) /* RX FIFO */ 34 #define SC16IS7XX_THR_REG (0x00) /* TX FIFO */ 35 #define SC16IS7XX_IER_REG (0x01) /* Interrupt enable */ 36 #define SC16IS7XX_IIR_REG (0x02) /* Interrupt Identification */ 37 #define SC16IS7XX_FCR_REG (0x02) /* FIFO control */ 38 #define SC16IS7XX_LCR_REG (0x03) /* Line Control */ 39 #define SC16IS7XX_MCR_REG (0x04) /* Modem Control */ 40 #define SC16IS7XX_LSR_REG (0x05) /* Line Status */ 41 #define SC16IS7XX_MSR_REG (0x06) /* Modem Status */ 42 #define SC16IS7XX_SPR_REG (0x07) /* Scratch Pad */ 43 #define SC16IS7XX_TXLVL_REG (0x08) /* TX FIFO level */ 44 #define SC16IS7XX_RXLVL_REG (0x09) /* RX FIFO level */ 45 #define SC16IS7XX_IODIR_REG (0x0a) /* I/O Direction 46 * - only on 75x/76x 47 */ 48 #define SC16IS7XX_IOSTATE_REG (0x0b) /* I/O State 49 * - only on 75x/76x 50 */ 51 #define SC16IS7XX_IOINTENA_REG (0x0c) /* I/O Interrupt Enable 52 * - only on 75x/76x 53 */ 54 #define SC16IS7XX_IOCONTROL_REG (0x0e) /* I/O Control 55 * - only on 75x/76x 56 */ 57 #define SC16IS7XX_EFCR_REG (0x0f) /* Extra Features Control */ 58 59 /* TCR/TLR Register set: Only if ((MCR[2] == 1) && (EFR[4] == 1)) */ 60 #define SC16IS7XX_TCR_REG (0x06) /* Transmit control */ 61 #define SC16IS7XX_TLR_REG (0x07) /* Trigger level */ 62 63 /* Special Register set: Only if ((LCR[7] == 1) && (LCR != 0xBF)) */ 64 #define SC16IS7XX_DLL_REG (0x00) /* Divisor Latch Low */ 65 #define SC16IS7XX_DLH_REG (0x01) /* Divisor Latch High */ 66 67 /* Enhanced Register set: Only if (LCR == 0xBF) */ 68 #define SC16IS7XX_EFR_REG (0x02) /* Enhanced Features */ 69 #define SC16IS7XX_XON1_REG (0x04) /* Xon1 word */ 70 #define SC16IS7XX_XON2_REG (0x05) /* Xon2 word */ 71 #define SC16IS7XX_XOFF1_REG (0x06) /* Xoff1 word */ 72 #define SC16IS7XX_XOFF2_REG (0x07) /* Xoff2 word */ 73 74 /* IER register bits */ 75 #define SC16IS7XX_IER_RDI_BIT (1 << 0) /* Enable RX data interrupt */ 76 #define SC16IS7XX_IER_THRI_BIT (1 << 1) /* Enable TX holding register 77 * interrupt */ 78 #define SC16IS7XX_IER_RLSI_BIT (1 << 2) /* Enable RX line status 79 * interrupt */ 80 #define SC16IS7XX_IER_MSI_BIT (1 << 3) /* Enable Modem status 81 * interrupt */ 82 83 /* IER register bits - write only if (EFR[4] == 1) */ 84 #define SC16IS7XX_IER_SLEEP_BIT (1 << 4) /* Enable Sleep mode */ 85 #define SC16IS7XX_IER_XOFFI_BIT (1 << 5) /* Enable Xoff interrupt */ 86 #define SC16IS7XX_IER_RTSI_BIT (1 << 6) /* Enable nRTS interrupt */ 87 #define SC16IS7XX_IER_CTSI_BIT (1 << 7) /* Enable nCTS interrupt */ 88 89 /* FCR register bits */ 90 #define SC16IS7XX_FCR_FIFO_BIT (1 << 0) /* Enable FIFO */ 91 #define SC16IS7XX_FCR_RXRESET_BIT (1 << 1) /* Reset RX FIFO */ 92 #define SC16IS7XX_FCR_TXRESET_BIT (1 << 2) /* Reset TX FIFO */ 93 #define SC16IS7XX_FCR_RXLVLL_BIT (1 << 6) /* RX Trigger level LSB */ 94 #define SC16IS7XX_FCR_RXLVLH_BIT (1 << 7) /* RX Trigger level MSB */ 95 96 /* FCR register bits - write only if (EFR[4] == 1) */ 97 #define SC16IS7XX_FCR_TXLVLL_BIT (1 << 4) /* TX Trigger level LSB */ 98 #define SC16IS7XX_FCR_TXLVLH_BIT (1 << 5) /* TX Trigger level MSB */ 99 100 /* IIR register bits */ 101 #define SC16IS7XX_IIR_NO_INT_BIT (1 << 0) /* No interrupts pending */ 102 #define SC16IS7XX_IIR_ID_MASK 0x3e /* Mask for the interrupt ID */ 103 #define SC16IS7XX_IIR_THRI_SRC 0x02 /* TX holding register empty */ 104 #define SC16IS7XX_IIR_RDI_SRC 0x04 /* RX data interrupt */ 105 #define SC16IS7XX_IIR_RLSE_SRC 0x06 /* RX line status error */ 106 #define SC16IS7XX_IIR_RTOI_SRC 0x0c /* RX time-out interrupt */ 107 #define SC16IS7XX_IIR_MSI_SRC 0x00 /* Modem status interrupt 108 * - only on 75x/76x 109 */ 110 #define SC16IS7XX_IIR_INPIN_SRC 0x30 /* Input pin change of state 111 * - only on 75x/76x 112 */ 113 #define SC16IS7XX_IIR_XOFFI_SRC 0x10 /* Received Xoff */ 114 #define SC16IS7XX_IIR_CTSRTS_SRC 0x20 /* nCTS,nRTS change of state 115 * from active (LOW) 116 * to inactive (HIGH) 117 */ 118 /* LCR register bits */ 119 #define SC16IS7XX_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */ 120 #define SC16IS7XX_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1 121 * 122 * Word length bits table: 123 * 00 -> 5 bit words 124 * 01 -> 6 bit words 125 * 10 -> 7 bit words 126 * 11 -> 8 bit words 127 */ 128 #define SC16IS7XX_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit 129 * 130 * STOP length bit table: 131 * 0 -> 1 stop bit 132 * 1 -> 1-1.5 stop bits if 133 * word length is 5, 134 * 2 stop bits otherwise 135 */ 136 #define SC16IS7XX_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */ 137 #define SC16IS7XX_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */ 138 #define SC16IS7XX_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */ 139 #define SC16IS7XX_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */ 140 #define SC16IS7XX_LCR_DLAB_BIT (1 << 7) /* Divisor Latch enable */ 141 #define SC16IS7XX_LCR_WORD_LEN_5 (0x00) 142 #define SC16IS7XX_LCR_WORD_LEN_6 (0x01) 143 #define SC16IS7XX_LCR_WORD_LEN_7 (0x02) 144 #define SC16IS7XX_LCR_WORD_LEN_8 (0x03) 145 #define SC16IS7XX_LCR_CONF_MODE_A SC16IS7XX_LCR_DLAB_BIT /* Special 146 * reg set */ 147 #define SC16IS7XX_LCR_CONF_MODE_B 0xBF /* Enhanced 148 * reg set */ 149 150 /* MCR register bits */ 151 #define SC16IS7XX_MCR_DTR_BIT (1 << 0) /* DTR complement 152 * - only on 75x/76x 153 */ 154 #define SC16IS7XX_MCR_RTS_BIT (1 << 1) /* RTS complement */ 155 #define SC16IS7XX_MCR_TCRTLR_BIT (1 << 2) /* TCR/TLR register enable */ 156 #define SC16IS7XX_MCR_LOOP_BIT (1 << 4) /* Enable loopback test mode */ 157 #define SC16IS7XX_MCR_XONANY_BIT (1 << 5) /* Enable Xon Any 158 * - write enabled 159 * if (EFR[4] == 1) 160 */ 161 #define SC16IS7XX_MCR_IRDA_BIT (1 << 6) /* Enable IrDA mode 162 * - write enabled 163 * if (EFR[4] == 1) 164 */ 165 #define SC16IS7XX_MCR_CLKSEL_BIT (1 << 7) /* Divide clock by 4 166 * - write enabled 167 * if (EFR[4] == 1) 168 */ 169 170 /* LSR register bits */ 171 #define SC16IS7XX_LSR_DR_BIT (1 << 0) /* Receiver data ready */ 172 #define SC16IS7XX_LSR_OE_BIT (1 << 1) /* Overrun Error */ 173 #define SC16IS7XX_LSR_PE_BIT (1 << 2) /* Parity Error */ 174 #define SC16IS7XX_LSR_FE_BIT (1 << 3) /* Frame Error */ 175 #define SC16IS7XX_LSR_BI_BIT (1 << 4) /* Break Interrupt */ 176 #define SC16IS7XX_LSR_BRK_ERROR_MASK 0x1E /* BI, FE, PE, OE bits */ 177 #define SC16IS7XX_LSR_THRE_BIT (1 << 5) /* TX holding register empty */ 178 #define SC16IS7XX_LSR_TEMT_BIT (1 << 6) /* Transmitter empty */ 179 #define SC16IS7XX_LSR_FIFOE_BIT (1 << 7) /* Fifo Error */ 180 181 /* MSR register bits */ 182 #define SC16IS7XX_MSR_DCTS_BIT (1 << 0) /* Delta CTS Clear To Send */ 183 #define SC16IS7XX_MSR_DDSR_BIT (1 << 1) /* Delta DSR Data Set Ready 184 * or (IO4) 185 * - only on 75x/76x 186 */ 187 #define SC16IS7XX_MSR_DRI_BIT (1 << 2) /* Delta RI Ring Indicator 188 * or (IO7) 189 * - only on 75x/76x 190 */ 191 #define SC16IS7XX_MSR_DCD_BIT (1 << 3) /* Delta CD Carrier Detect 192 * or (IO6) 193 * - only on 75x/76x 194 */ 195 #define SC16IS7XX_MSR_CTS_BIT (1 << 4) /* CTS */ 196 #define SC16IS7XX_MSR_DSR_BIT (1 << 5) /* DSR (IO4) 197 * - only on 75x/76x 198 */ 199 #define SC16IS7XX_MSR_RI_BIT (1 << 6) /* RI (IO7) 200 * - only on 75x/76x 201 */ 202 #define SC16IS7XX_MSR_CD_BIT (1 << 7) /* CD (IO6) 203 * - only on 75x/76x 204 */ 205 #define SC16IS7XX_MSR_DELTA_MASK 0x0F /* Any of the delta bits! */ 206 207 /* 208 * TCR register bits 209 * TCR trigger levels are available from 0 to 60 characters with a granularity 210 * of four. 211 * The programmer must program the TCR such that TCR[3:0] > TCR[7:4]. There is 212 * no built-in hardware check to make sure this condition is met. Also, the TCR 213 * must be programmed with this condition before auto RTS or software flow 214 * control is enabled to avoid spurious operation of the device. 215 */ 216 #define SC16IS7XX_TCR_RX_HALT(words) ((((words) / 4) & 0x0f) << 0) 217 #define SC16IS7XX_TCR_RX_RESUME(words) ((((words) / 4) & 0x0f) << 4) 218 219 /* 220 * TLR register bits 221 * If TLR[3:0] or TLR[7:4] are logical 0, the selectable trigger levels via the 222 * FIFO Control Register (FCR) are used for the transmit and receive FIFO 223 * trigger levels. Trigger levels from 4 characters to 60 characters are 224 * available with a granularity of four. 225 * 226 * When the trigger level setting in TLR is zero, the SC16IS74x/75x/76x uses the 227 * trigger level setting defined in FCR. If TLR has non-zero trigger level value 228 * the trigger level defined in FCR is discarded. This applies to both transmit 229 * FIFO and receive FIFO trigger level setting. 230 * 231 * When TLR is used for RX trigger level control, FCR[7:6] should be left at the 232 * default state, that is, '00'. 233 */ 234 #define SC16IS7XX_TLR_TX_TRIGGER(words) ((((words) / 4) & 0x0f) << 0) 235 #define SC16IS7XX_TLR_RX_TRIGGER(words) ((((words) / 4) & 0x0f) << 4) 236 237 /* IOControl register bits (Only 75x/76x) */ 238 #define SC16IS7XX_IOCONTROL_LATCH_BIT (1 << 0) /* Enable input latching */ 239 #define SC16IS7XX_IOCONTROL_MODEM_A_BIT (1 << 1) /* Enable GPIO[7:4] as modem A pins */ 240 #define SC16IS7XX_IOCONTROL_MODEM_B_BIT (1 << 2) /* Enable GPIO[3:0] as modem B pins */ 241 #define SC16IS7XX_IOCONTROL_SRESET_BIT (1 << 3) /* Software Reset */ 242 243 /* EFCR register bits */ 244 #define SC16IS7XX_EFCR_9BIT_MODE_BIT (1 << 0) /* Enable 9-bit or Multidrop 245 * mode (RS485) */ 246 #define SC16IS7XX_EFCR_RXDISABLE_BIT (1 << 1) /* Disable receiver */ 247 #define SC16IS7XX_EFCR_TXDISABLE_BIT (1 << 2) /* Disable transmitter */ 248 #define SC16IS7XX_EFCR_AUTO_RS485_BIT (1 << 4) /* Auto RS485 RTS direction */ 249 #define SC16IS7XX_EFCR_RTS_INVERT_BIT (1 << 5) /* RTS output inversion */ 250 #define SC16IS7XX_EFCR_IRDA_MODE_BIT (1 << 7) /* IrDA mode 251 * 0 = rate upto 115.2 kbit/s 252 * - Only 75x/76x 253 * 1 = rate upto 1.152 Mbit/s 254 * - Only 76x 255 */ 256 257 /* EFR register bits */ 258 #define SC16IS7XX_EFR_AUTORTS_BIT (1 << 6) /* Auto RTS flow ctrl enable */ 259 #define SC16IS7XX_EFR_AUTOCTS_BIT (1 << 7) /* Auto CTS flow ctrl enable */ 260 #define SC16IS7XX_EFR_XOFF2_DETECT_BIT (1 << 5) /* Enable Xoff2 detection */ 261 #define SC16IS7XX_EFR_ENABLE_BIT (1 << 4) /* Enable enhanced functions 262 * and writing to IER[7:4], 263 * FCR[5:4], MCR[7:5] 264 */ 265 #define SC16IS7XX_EFR_SWFLOW3_BIT (1 << 3) /* SWFLOW bit 3 */ 266 #define SC16IS7XX_EFR_SWFLOW2_BIT (1 << 2) /* SWFLOW bit 2 267 * 268 * SWFLOW bits 3 & 2 table: 269 * 00 -> no transmitter flow 270 * control 271 * 01 -> transmitter generates 272 * XON2 and XOFF2 273 * 10 -> transmitter generates 274 * XON1 and XOFF1 275 * 11 -> transmitter generates 276 * XON1, XON2, XOFF1 and 277 * XOFF2 278 */ 279 #define SC16IS7XX_EFR_SWFLOW1_BIT (1 << 1) /* SWFLOW bit 2 */ 280 #define SC16IS7XX_EFR_SWFLOW0_BIT (1 << 0) /* SWFLOW bit 3 281 * 282 * SWFLOW bits 3 & 2 table: 283 * 00 -> no received flow 284 * control 285 * 01 -> receiver compares 286 * XON2 and XOFF2 287 * 10 -> receiver compares 288 * XON1 and XOFF1 289 * 11 -> receiver compares 290 * XON1, XON2, XOFF1 and 291 * XOFF2 292 */ 293 #define SC16IS7XX_EFR_FLOWCTRL_BITS (SC16IS7XX_EFR_AUTORTS_BIT | \ 294 SC16IS7XX_EFR_AUTOCTS_BIT | \ 295 SC16IS7XX_EFR_XOFF2_DETECT_BIT | \ 296 SC16IS7XX_EFR_SWFLOW3_BIT | \ 297 SC16IS7XX_EFR_SWFLOW2_BIT | \ 298 SC16IS7XX_EFR_SWFLOW1_BIT | \ 299 SC16IS7XX_EFR_SWFLOW0_BIT) 300 301 302 /* Misc definitions */ 303 #define SC16IS7XX_FIFO_SIZE (64) 304 #define SC16IS7XX_REG_SHIFT 2 305 #define SC16IS7XX_GPIOS_PER_BANK 4 306 307 struct sc16is7xx_devtype { 308 char name[10]; 309 int nr_gpio; 310 int nr_uart; 311 }; 312 313 #define SC16IS7XX_RECONF_MD (1 << 0) 314 #define SC16IS7XX_RECONF_IER (1 << 1) 315 #define SC16IS7XX_RECONF_RS485 (1 << 2) 316 317 struct sc16is7xx_one_config { 318 unsigned int flags; 319 u8 ier_mask; 320 u8 ier_val; 321 }; 322 323 struct sc16is7xx_one { 324 struct uart_port port; 325 u8 line; 326 struct kthread_work tx_work; 327 struct kthread_work reg_work; 328 struct kthread_delayed_work ms_work; 329 struct sc16is7xx_one_config config; 330 bool irda_mode; 331 unsigned int old_mctrl; 332 }; 333 334 struct sc16is7xx_port { 335 const struct sc16is7xx_devtype *devtype; 336 struct regmap *regmap; 337 struct clk *clk; 338 #ifdef CONFIG_GPIOLIB 339 struct gpio_chip gpio; 340 unsigned long gpio_valid_mask; 341 #endif 342 u8 mctrl_mask; 343 unsigned char buf[SC16IS7XX_FIFO_SIZE]; 344 struct kthread_worker kworker; 345 struct task_struct *kworker_task; 346 struct mutex efr_lock; 347 struct sc16is7xx_one p[]; 348 }; 349 350 static unsigned long sc16is7xx_lines; 351 352 static struct uart_driver sc16is7xx_uart = { 353 .owner = THIS_MODULE, 354 .dev_name = "ttySC", 355 .nr = SC16IS7XX_MAX_DEVS, 356 }; 357 358 static void sc16is7xx_ier_set(struct uart_port *port, u8 bit); 359 static void sc16is7xx_stop_tx(struct uart_port *port); 360 361 #define to_sc16is7xx_one(p,e) ((container_of((p), struct sc16is7xx_one, e))) 362 363 static int sc16is7xx_line(struct uart_port *port) 364 { 365 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 366 367 return one->line; 368 } 369 370 static u8 sc16is7xx_port_read(struct uart_port *port, u8 reg) 371 { 372 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 373 unsigned int val = 0; 374 const u8 line = sc16is7xx_line(port); 375 376 regmap_read(s->regmap, (reg << SC16IS7XX_REG_SHIFT) | line, &val); 377 378 return val; 379 } 380 381 static void sc16is7xx_port_write(struct uart_port *port, u8 reg, u8 val) 382 { 383 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 384 const u8 line = sc16is7xx_line(port); 385 386 regmap_write(s->regmap, (reg << SC16IS7XX_REG_SHIFT) | line, val); 387 } 388 389 static void sc16is7xx_fifo_read(struct uart_port *port, unsigned int rxlen) 390 { 391 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 392 const u8 line = sc16is7xx_line(port); 393 u8 addr = (SC16IS7XX_RHR_REG << SC16IS7XX_REG_SHIFT) | line; 394 395 regcache_cache_bypass(s->regmap, true); 396 regmap_raw_read(s->regmap, addr, s->buf, rxlen); 397 regcache_cache_bypass(s->regmap, false); 398 } 399 400 static void sc16is7xx_fifo_write(struct uart_port *port, u8 to_send) 401 { 402 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 403 const u8 line = sc16is7xx_line(port); 404 u8 addr = (SC16IS7XX_THR_REG << SC16IS7XX_REG_SHIFT) | line; 405 406 /* 407 * Don't send zero-length data, at least on SPI it confuses the chip 408 * delivering wrong TXLVL data. 409 */ 410 if (unlikely(!to_send)) 411 return; 412 413 regcache_cache_bypass(s->regmap, true); 414 regmap_raw_write(s->regmap, addr, s->buf, to_send); 415 regcache_cache_bypass(s->regmap, false); 416 } 417 418 static void sc16is7xx_port_update(struct uart_port *port, u8 reg, 419 u8 mask, u8 val) 420 { 421 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 422 const u8 line = sc16is7xx_line(port); 423 424 regmap_update_bits(s->regmap, (reg << SC16IS7XX_REG_SHIFT) | line, 425 mask, val); 426 } 427 428 static int sc16is7xx_alloc_line(void) 429 { 430 int i; 431 432 BUILD_BUG_ON(SC16IS7XX_MAX_DEVS > BITS_PER_LONG); 433 434 for (i = 0; i < SC16IS7XX_MAX_DEVS; i++) 435 if (!test_and_set_bit(i, &sc16is7xx_lines)) 436 break; 437 438 return i; 439 } 440 441 static void sc16is7xx_power(struct uart_port *port, int on) 442 { 443 sc16is7xx_port_update(port, SC16IS7XX_IER_REG, 444 SC16IS7XX_IER_SLEEP_BIT, 445 on ? 0 : SC16IS7XX_IER_SLEEP_BIT); 446 } 447 448 static const struct sc16is7xx_devtype sc16is74x_devtype = { 449 .name = "SC16IS74X", 450 .nr_gpio = 0, 451 .nr_uart = 1, 452 }; 453 454 static const struct sc16is7xx_devtype sc16is750_devtype = { 455 .name = "SC16IS750", 456 .nr_gpio = 8, 457 .nr_uart = 1, 458 }; 459 460 static const struct sc16is7xx_devtype sc16is752_devtype = { 461 .name = "SC16IS752", 462 .nr_gpio = 8, 463 .nr_uart = 2, 464 }; 465 466 static const struct sc16is7xx_devtype sc16is760_devtype = { 467 .name = "SC16IS760", 468 .nr_gpio = 8, 469 .nr_uart = 1, 470 }; 471 472 static const struct sc16is7xx_devtype sc16is762_devtype = { 473 .name = "SC16IS762", 474 .nr_gpio = 8, 475 .nr_uart = 2, 476 }; 477 478 static bool sc16is7xx_regmap_volatile(struct device *dev, unsigned int reg) 479 { 480 switch (reg >> SC16IS7XX_REG_SHIFT) { 481 case SC16IS7XX_RHR_REG: 482 case SC16IS7XX_IIR_REG: 483 case SC16IS7XX_LSR_REG: 484 case SC16IS7XX_MSR_REG: 485 case SC16IS7XX_TXLVL_REG: 486 case SC16IS7XX_RXLVL_REG: 487 case SC16IS7XX_IOSTATE_REG: 488 case SC16IS7XX_IOCONTROL_REG: 489 return true; 490 default: 491 break; 492 } 493 494 return false; 495 } 496 497 static bool sc16is7xx_regmap_precious(struct device *dev, unsigned int reg) 498 { 499 switch (reg >> SC16IS7XX_REG_SHIFT) { 500 case SC16IS7XX_RHR_REG: 501 return true; 502 default: 503 break; 504 } 505 506 return false; 507 } 508 509 static int sc16is7xx_set_baud(struct uart_port *port, int baud) 510 { 511 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 512 u8 lcr; 513 u8 prescaler = 0; 514 unsigned long clk = port->uartclk, div = clk / 16 / baud; 515 516 if (div > 0xffff) { 517 prescaler = SC16IS7XX_MCR_CLKSEL_BIT; 518 div /= 4; 519 } 520 521 /* In an amazing feat of design, the Enhanced Features Register shares 522 * the address of the Interrupt Identification Register, and is 523 * switched in by writing a magic value (0xbf) to the Line Control 524 * Register. Any interrupt firing during this time will see the EFR 525 * where it expects the IIR to be, leading to "Unexpected interrupt" 526 * messages. 527 * 528 * Prevent this possibility by claiming a mutex while accessing the 529 * EFR, and claiming the same mutex from within the interrupt handler. 530 * This is similar to disabling the interrupt, but that doesn't work 531 * because the bulk of the interrupt processing is run as a workqueue 532 * job in thread context. 533 */ 534 mutex_lock(&s->efr_lock); 535 536 lcr = sc16is7xx_port_read(port, SC16IS7XX_LCR_REG); 537 538 /* Open the LCR divisors for configuration */ 539 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, 540 SC16IS7XX_LCR_CONF_MODE_B); 541 542 /* Enable enhanced features */ 543 regcache_cache_bypass(s->regmap, true); 544 sc16is7xx_port_update(port, SC16IS7XX_EFR_REG, 545 SC16IS7XX_EFR_ENABLE_BIT, 546 SC16IS7XX_EFR_ENABLE_BIT); 547 548 regcache_cache_bypass(s->regmap, false); 549 550 /* Put LCR back to the normal mode */ 551 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr); 552 553 mutex_unlock(&s->efr_lock); 554 555 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG, 556 SC16IS7XX_MCR_CLKSEL_BIT, 557 prescaler); 558 559 /* Open the LCR divisors for configuration */ 560 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, 561 SC16IS7XX_LCR_CONF_MODE_A); 562 563 /* Write the new divisor */ 564 regcache_cache_bypass(s->regmap, true); 565 sc16is7xx_port_write(port, SC16IS7XX_DLH_REG, div / 256); 566 sc16is7xx_port_write(port, SC16IS7XX_DLL_REG, div % 256); 567 regcache_cache_bypass(s->regmap, false); 568 569 /* Put LCR back to the normal mode */ 570 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr); 571 572 return DIV_ROUND_CLOSEST(clk / 16, div); 573 } 574 575 static void sc16is7xx_handle_rx(struct uart_port *port, unsigned int rxlen, 576 unsigned int iir) 577 { 578 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 579 unsigned int lsr = 0, bytes_read, i; 580 bool read_lsr = (iir == SC16IS7XX_IIR_RLSE_SRC) ? true : false; 581 u8 ch, flag; 582 583 if (unlikely(rxlen >= sizeof(s->buf))) { 584 dev_warn_ratelimited(port->dev, 585 "ttySC%i: Possible RX FIFO overrun: %d\n", 586 port->line, rxlen); 587 port->icount.buf_overrun++; 588 /* Ensure sanity of RX level */ 589 rxlen = sizeof(s->buf); 590 } 591 592 while (rxlen) { 593 /* Only read lsr if there are possible errors in FIFO */ 594 if (read_lsr) { 595 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG); 596 if (!(lsr & SC16IS7XX_LSR_FIFOE_BIT)) 597 read_lsr = false; /* No errors left in FIFO */ 598 } else 599 lsr = 0; 600 601 if (read_lsr) { 602 s->buf[0] = sc16is7xx_port_read(port, SC16IS7XX_RHR_REG); 603 bytes_read = 1; 604 } else { 605 sc16is7xx_fifo_read(port, rxlen); 606 bytes_read = rxlen; 607 } 608 609 lsr &= SC16IS7XX_LSR_BRK_ERROR_MASK; 610 611 port->icount.rx++; 612 flag = TTY_NORMAL; 613 614 if (unlikely(lsr)) { 615 if (lsr & SC16IS7XX_LSR_BI_BIT) { 616 port->icount.brk++; 617 if (uart_handle_break(port)) 618 continue; 619 } else if (lsr & SC16IS7XX_LSR_PE_BIT) 620 port->icount.parity++; 621 else if (lsr & SC16IS7XX_LSR_FE_BIT) 622 port->icount.frame++; 623 else if (lsr & SC16IS7XX_LSR_OE_BIT) 624 port->icount.overrun++; 625 626 lsr &= port->read_status_mask; 627 if (lsr & SC16IS7XX_LSR_BI_BIT) 628 flag = TTY_BREAK; 629 else if (lsr & SC16IS7XX_LSR_PE_BIT) 630 flag = TTY_PARITY; 631 else if (lsr & SC16IS7XX_LSR_FE_BIT) 632 flag = TTY_FRAME; 633 else if (lsr & SC16IS7XX_LSR_OE_BIT) 634 flag = TTY_OVERRUN; 635 } 636 637 for (i = 0; i < bytes_read; ++i) { 638 ch = s->buf[i]; 639 if (uart_handle_sysrq_char(port, ch)) 640 continue; 641 642 if (lsr & port->ignore_status_mask) 643 continue; 644 645 uart_insert_char(port, lsr, SC16IS7XX_LSR_OE_BIT, ch, 646 flag); 647 } 648 rxlen -= bytes_read; 649 } 650 651 tty_flip_buffer_push(&port->state->port); 652 } 653 654 static void sc16is7xx_handle_tx(struct uart_port *port) 655 { 656 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 657 struct circ_buf *xmit = &port->state->xmit; 658 unsigned int txlen, to_send, i; 659 unsigned long flags; 660 661 if (unlikely(port->x_char)) { 662 sc16is7xx_port_write(port, SC16IS7XX_THR_REG, port->x_char); 663 port->icount.tx++; 664 port->x_char = 0; 665 return; 666 } 667 668 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { 669 uart_port_lock_irqsave(port, &flags); 670 sc16is7xx_stop_tx(port); 671 uart_port_unlock_irqrestore(port, flags); 672 return; 673 } 674 675 /* Get length of data pending in circular buffer */ 676 to_send = uart_circ_chars_pending(xmit); 677 if (likely(to_send)) { 678 /* Limit to size of TX FIFO */ 679 txlen = sc16is7xx_port_read(port, SC16IS7XX_TXLVL_REG); 680 if (txlen > SC16IS7XX_FIFO_SIZE) { 681 dev_err_ratelimited(port->dev, 682 "chip reports %d free bytes in TX fifo, but it only has %d", 683 txlen, SC16IS7XX_FIFO_SIZE); 684 txlen = 0; 685 } 686 to_send = (to_send > txlen) ? txlen : to_send; 687 688 /* Convert to linear buffer */ 689 for (i = 0; i < to_send; ++i) { 690 s->buf[i] = xmit->buf[xmit->tail]; 691 uart_xmit_advance(port, 1); 692 } 693 694 sc16is7xx_fifo_write(port, to_send); 695 } 696 697 uart_port_lock_irqsave(port, &flags); 698 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 699 uart_write_wakeup(port); 700 701 if (uart_circ_empty(xmit)) 702 sc16is7xx_stop_tx(port); 703 uart_port_unlock_irqrestore(port, flags); 704 } 705 706 static unsigned int sc16is7xx_get_hwmctrl(struct uart_port *port) 707 { 708 u8 msr = sc16is7xx_port_read(port, SC16IS7XX_MSR_REG); 709 unsigned int mctrl = 0; 710 711 mctrl |= (msr & SC16IS7XX_MSR_CTS_BIT) ? TIOCM_CTS : 0; 712 mctrl |= (msr & SC16IS7XX_MSR_DSR_BIT) ? TIOCM_DSR : 0; 713 mctrl |= (msr & SC16IS7XX_MSR_CD_BIT) ? TIOCM_CAR : 0; 714 mctrl |= (msr & SC16IS7XX_MSR_RI_BIT) ? TIOCM_RNG : 0; 715 return mctrl; 716 } 717 718 static void sc16is7xx_update_mlines(struct sc16is7xx_one *one) 719 { 720 struct uart_port *port = &one->port; 721 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 722 unsigned long flags; 723 unsigned int status, changed; 724 725 lockdep_assert_held_once(&s->efr_lock); 726 727 status = sc16is7xx_get_hwmctrl(port); 728 changed = status ^ one->old_mctrl; 729 730 if (changed == 0) 731 return; 732 733 one->old_mctrl = status; 734 735 uart_port_lock_irqsave(port, &flags); 736 if ((changed & TIOCM_RNG) && (status & TIOCM_RNG)) 737 port->icount.rng++; 738 if (changed & TIOCM_DSR) 739 port->icount.dsr++; 740 if (changed & TIOCM_CAR) 741 uart_handle_dcd_change(port, status & TIOCM_CAR); 742 if (changed & TIOCM_CTS) 743 uart_handle_cts_change(port, status & TIOCM_CTS); 744 745 wake_up_interruptible(&port->state->port.delta_msr_wait); 746 uart_port_unlock_irqrestore(port, flags); 747 } 748 749 static bool sc16is7xx_port_irq(struct sc16is7xx_port *s, int portno) 750 { 751 struct uart_port *port = &s->p[portno].port; 752 753 do { 754 unsigned int iir, rxlen; 755 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 756 757 iir = sc16is7xx_port_read(port, SC16IS7XX_IIR_REG); 758 if (iir & SC16IS7XX_IIR_NO_INT_BIT) 759 return false; 760 761 iir &= SC16IS7XX_IIR_ID_MASK; 762 763 switch (iir) { 764 case SC16IS7XX_IIR_RDI_SRC: 765 case SC16IS7XX_IIR_RLSE_SRC: 766 case SC16IS7XX_IIR_RTOI_SRC: 767 case SC16IS7XX_IIR_XOFFI_SRC: 768 rxlen = sc16is7xx_port_read(port, SC16IS7XX_RXLVL_REG); 769 770 /* 771 * There is a silicon bug that makes the chip report a 772 * time-out interrupt but no data in the FIFO. This is 773 * described in errata section 18.1.4. 774 * 775 * When this happens, read one byte from the FIFO to 776 * clear the interrupt. 777 */ 778 if (iir == SC16IS7XX_IIR_RTOI_SRC && !rxlen) 779 rxlen = 1; 780 781 if (rxlen) 782 sc16is7xx_handle_rx(port, rxlen, iir); 783 break; 784 /* CTSRTS interrupt comes only when CTS goes inactive */ 785 case SC16IS7XX_IIR_CTSRTS_SRC: 786 case SC16IS7XX_IIR_MSI_SRC: 787 sc16is7xx_update_mlines(one); 788 break; 789 case SC16IS7XX_IIR_THRI_SRC: 790 sc16is7xx_handle_tx(port); 791 break; 792 default: 793 dev_err_ratelimited(port->dev, 794 "ttySC%i: Unexpected interrupt: %x", 795 port->line, iir); 796 break; 797 } 798 } while (0); 799 return true; 800 } 801 802 static irqreturn_t sc16is7xx_irq(int irq, void *dev_id) 803 { 804 struct sc16is7xx_port *s = (struct sc16is7xx_port *)dev_id; 805 806 mutex_lock(&s->efr_lock); 807 808 while (1) { 809 bool keep_polling = false; 810 int i; 811 812 for (i = 0; i < s->devtype->nr_uart; ++i) 813 keep_polling |= sc16is7xx_port_irq(s, i); 814 if (!keep_polling) 815 break; 816 } 817 818 mutex_unlock(&s->efr_lock); 819 820 return IRQ_HANDLED; 821 } 822 823 static void sc16is7xx_tx_proc(struct kthread_work *ws) 824 { 825 struct uart_port *port = &(to_sc16is7xx_one(ws, tx_work)->port); 826 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 827 unsigned long flags; 828 829 if ((port->rs485.flags & SER_RS485_ENABLED) && 830 (port->rs485.delay_rts_before_send > 0)) 831 msleep(port->rs485.delay_rts_before_send); 832 833 mutex_lock(&s->efr_lock); 834 sc16is7xx_handle_tx(port); 835 mutex_unlock(&s->efr_lock); 836 837 uart_port_lock_irqsave(port, &flags); 838 sc16is7xx_ier_set(port, SC16IS7XX_IER_THRI_BIT); 839 uart_port_unlock_irqrestore(port, flags); 840 } 841 842 static void sc16is7xx_reconf_rs485(struct uart_port *port) 843 { 844 const u32 mask = SC16IS7XX_EFCR_AUTO_RS485_BIT | 845 SC16IS7XX_EFCR_RTS_INVERT_BIT; 846 u32 efcr = 0; 847 struct serial_rs485 *rs485 = &port->rs485; 848 unsigned long irqflags; 849 850 uart_port_lock_irqsave(port, &irqflags); 851 if (rs485->flags & SER_RS485_ENABLED) { 852 efcr |= SC16IS7XX_EFCR_AUTO_RS485_BIT; 853 854 if (rs485->flags & SER_RS485_RTS_AFTER_SEND) 855 efcr |= SC16IS7XX_EFCR_RTS_INVERT_BIT; 856 } 857 uart_port_unlock_irqrestore(port, irqflags); 858 859 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, mask, efcr); 860 } 861 862 static void sc16is7xx_reg_proc(struct kthread_work *ws) 863 { 864 struct sc16is7xx_one *one = to_sc16is7xx_one(ws, reg_work); 865 struct sc16is7xx_one_config config; 866 unsigned long irqflags; 867 868 uart_port_lock_irqsave(&one->port, &irqflags); 869 config = one->config; 870 memset(&one->config, 0, sizeof(one->config)); 871 uart_port_unlock_irqrestore(&one->port, irqflags); 872 873 if (config.flags & SC16IS7XX_RECONF_MD) { 874 u8 mcr = 0; 875 876 /* Device ignores RTS setting when hardware flow is enabled */ 877 if (one->port.mctrl & TIOCM_RTS) 878 mcr |= SC16IS7XX_MCR_RTS_BIT; 879 880 if (one->port.mctrl & TIOCM_DTR) 881 mcr |= SC16IS7XX_MCR_DTR_BIT; 882 883 if (one->port.mctrl & TIOCM_LOOP) 884 mcr |= SC16IS7XX_MCR_LOOP_BIT; 885 sc16is7xx_port_update(&one->port, SC16IS7XX_MCR_REG, 886 SC16IS7XX_MCR_RTS_BIT | 887 SC16IS7XX_MCR_DTR_BIT | 888 SC16IS7XX_MCR_LOOP_BIT, 889 mcr); 890 } 891 892 if (config.flags & SC16IS7XX_RECONF_IER) 893 sc16is7xx_port_update(&one->port, SC16IS7XX_IER_REG, 894 config.ier_mask, config.ier_val); 895 896 if (config.flags & SC16IS7XX_RECONF_RS485) 897 sc16is7xx_reconf_rs485(&one->port); 898 } 899 900 static void sc16is7xx_ier_clear(struct uart_port *port, u8 bit) 901 { 902 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 903 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 904 905 lockdep_assert_held_once(&port->lock); 906 907 one->config.flags |= SC16IS7XX_RECONF_IER; 908 one->config.ier_mask |= bit; 909 one->config.ier_val &= ~bit; 910 kthread_queue_work(&s->kworker, &one->reg_work); 911 } 912 913 static void sc16is7xx_ier_set(struct uart_port *port, u8 bit) 914 { 915 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 916 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 917 918 lockdep_assert_held_once(&port->lock); 919 920 one->config.flags |= SC16IS7XX_RECONF_IER; 921 one->config.ier_mask |= bit; 922 one->config.ier_val |= bit; 923 kthread_queue_work(&s->kworker, &one->reg_work); 924 } 925 926 static void sc16is7xx_stop_tx(struct uart_port *port) 927 { 928 sc16is7xx_ier_clear(port, SC16IS7XX_IER_THRI_BIT); 929 } 930 931 static void sc16is7xx_stop_rx(struct uart_port *port) 932 { 933 sc16is7xx_ier_clear(port, SC16IS7XX_IER_RDI_BIT); 934 } 935 936 static void sc16is7xx_ms_proc(struct kthread_work *ws) 937 { 938 struct sc16is7xx_one *one = to_sc16is7xx_one(ws, ms_work.work); 939 struct sc16is7xx_port *s = dev_get_drvdata(one->port.dev); 940 941 if (one->port.state) { 942 mutex_lock(&s->efr_lock); 943 sc16is7xx_update_mlines(one); 944 mutex_unlock(&s->efr_lock); 945 946 kthread_queue_delayed_work(&s->kworker, &one->ms_work, HZ); 947 } 948 } 949 950 static void sc16is7xx_enable_ms(struct uart_port *port) 951 { 952 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 953 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 954 955 lockdep_assert_held_once(&port->lock); 956 957 kthread_queue_delayed_work(&s->kworker, &one->ms_work, 0); 958 } 959 960 static void sc16is7xx_start_tx(struct uart_port *port) 961 { 962 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 963 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 964 965 kthread_queue_work(&s->kworker, &one->tx_work); 966 } 967 968 static void sc16is7xx_throttle(struct uart_port *port) 969 { 970 unsigned long flags; 971 972 /* 973 * Hardware flow control is enabled and thus the device ignores RTS 974 * value set in MCR register. Stop reading data from RX FIFO so the 975 * AutoRTS feature will de-activate RTS output. 976 */ 977 uart_port_lock_irqsave(port, &flags); 978 sc16is7xx_ier_clear(port, SC16IS7XX_IER_RDI_BIT); 979 uart_port_unlock_irqrestore(port, flags); 980 } 981 982 static void sc16is7xx_unthrottle(struct uart_port *port) 983 { 984 unsigned long flags; 985 986 uart_port_lock_irqsave(port, &flags); 987 sc16is7xx_ier_set(port, SC16IS7XX_IER_RDI_BIT); 988 uart_port_unlock_irqrestore(port, flags); 989 } 990 991 static unsigned int sc16is7xx_tx_empty(struct uart_port *port) 992 { 993 unsigned int lsr; 994 995 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG); 996 997 return (lsr & SC16IS7XX_LSR_TEMT_BIT) ? TIOCSER_TEMT : 0; 998 } 999 1000 static unsigned int sc16is7xx_get_mctrl(struct uart_port *port) 1001 { 1002 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 1003 1004 /* Called with port lock taken so we can only return cached value */ 1005 return one->old_mctrl; 1006 } 1007 1008 static void sc16is7xx_set_mctrl(struct uart_port *port, unsigned int mctrl) 1009 { 1010 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 1011 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 1012 1013 one->config.flags |= SC16IS7XX_RECONF_MD; 1014 kthread_queue_work(&s->kworker, &one->reg_work); 1015 } 1016 1017 static void sc16is7xx_break_ctl(struct uart_port *port, int break_state) 1018 { 1019 sc16is7xx_port_update(port, SC16IS7XX_LCR_REG, 1020 SC16IS7XX_LCR_TXBREAK_BIT, 1021 break_state ? SC16IS7XX_LCR_TXBREAK_BIT : 0); 1022 } 1023 1024 static void sc16is7xx_set_termios(struct uart_port *port, 1025 struct ktermios *termios, 1026 const struct ktermios *old) 1027 { 1028 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 1029 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 1030 unsigned int lcr, flow = 0; 1031 int baud; 1032 unsigned long flags; 1033 1034 kthread_cancel_delayed_work_sync(&one->ms_work); 1035 1036 /* Mask termios capabilities we don't support */ 1037 termios->c_cflag &= ~CMSPAR; 1038 1039 /* Word size */ 1040 switch (termios->c_cflag & CSIZE) { 1041 case CS5: 1042 lcr = SC16IS7XX_LCR_WORD_LEN_5; 1043 break; 1044 case CS6: 1045 lcr = SC16IS7XX_LCR_WORD_LEN_6; 1046 break; 1047 case CS7: 1048 lcr = SC16IS7XX_LCR_WORD_LEN_7; 1049 break; 1050 case CS8: 1051 lcr = SC16IS7XX_LCR_WORD_LEN_8; 1052 break; 1053 default: 1054 lcr = SC16IS7XX_LCR_WORD_LEN_8; 1055 termios->c_cflag &= ~CSIZE; 1056 termios->c_cflag |= CS8; 1057 break; 1058 } 1059 1060 /* Parity */ 1061 if (termios->c_cflag & PARENB) { 1062 lcr |= SC16IS7XX_LCR_PARITY_BIT; 1063 if (!(termios->c_cflag & PARODD)) 1064 lcr |= SC16IS7XX_LCR_EVENPARITY_BIT; 1065 } 1066 1067 /* Stop bits */ 1068 if (termios->c_cflag & CSTOPB) 1069 lcr |= SC16IS7XX_LCR_STOPLEN_BIT; /* 2 stops */ 1070 1071 /* Set read status mask */ 1072 port->read_status_mask = SC16IS7XX_LSR_OE_BIT; 1073 if (termios->c_iflag & INPCK) 1074 port->read_status_mask |= SC16IS7XX_LSR_PE_BIT | 1075 SC16IS7XX_LSR_FE_BIT; 1076 if (termios->c_iflag & (BRKINT | PARMRK)) 1077 port->read_status_mask |= SC16IS7XX_LSR_BI_BIT; 1078 1079 /* Set status ignore mask */ 1080 port->ignore_status_mask = 0; 1081 if (termios->c_iflag & IGNBRK) 1082 port->ignore_status_mask |= SC16IS7XX_LSR_BI_BIT; 1083 if (!(termios->c_cflag & CREAD)) 1084 port->ignore_status_mask |= SC16IS7XX_LSR_BRK_ERROR_MASK; 1085 1086 /* As above, claim the mutex while accessing the EFR. */ 1087 mutex_lock(&s->efr_lock); 1088 1089 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, 1090 SC16IS7XX_LCR_CONF_MODE_B); 1091 1092 /* Configure flow control */ 1093 regcache_cache_bypass(s->regmap, true); 1094 sc16is7xx_port_write(port, SC16IS7XX_XON1_REG, termios->c_cc[VSTART]); 1095 sc16is7xx_port_write(port, SC16IS7XX_XOFF1_REG, termios->c_cc[VSTOP]); 1096 1097 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS); 1098 if (termios->c_cflag & CRTSCTS) { 1099 flow |= SC16IS7XX_EFR_AUTOCTS_BIT | 1100 SC16IS7XX_EFR_AUTORTS_BIT; 1101 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 1102 } 1103 if (termios->c_iflag & IXON) 1104 flow |= SC16IS7XX_EFR_SWFLOW3_BIT; 1105 if (termios->c_iflag & IXOFF) 1106 flow |= SC16IS7XX_EFR_SWFLOW1_BIT; 1107 1108 sc16is7xx_port_update(port, 1109 SC16IS7XX_EFR_REG, 1110 SC16IS7XX_EFR_FLOWCTRL_BITS, 1111 flow); 1112 regcache_cache_bypass(s->regmap, false); 1113 1114 /* Update LCR register */ 1115 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr); 1116 1117 mutex_unlock(&s->efr_lock); 1118 1119 /* Get baud rate generator configuration */ 1120 baud = uart_get_baud_rate(port, termios, old, 1121 port->uartclk / 16 / 4 / 0xffff, 1122 port->uartclk / 16); 1123 1124 /* Setup baudrate generator */ 1125 baud = sc16is7xx_set_baud(port, baud); 1126 1127 uart_port_lock_irqsave(port, &flags); 1128 1129 /* Update timeout according to new baud rate */ 1130 uart_update_timeout(port, termios->c_cflag, baud); 1131 1132 if (UART_ENABLE_MS(port, termios->c_cflag)) 1133 sc16is7xx_enable_ms(port); 1134 1135 uart_port_unlock_irqrestore(port, flags); 1136 } 1137 1138 static int sc16is7xx_config_rs485(struct uart_port *port, struct ktermios *termios, 1139 struct serial_rs485 *rs485) 1140 { 1141 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 1142 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 1143 1144 if (rs485->flags & SER_RS485_ENABLED) { 1145 /* 1146 * RTS signal is handled by HW, it's timing can't be influenced. 1147 * However, it's sometimes useful to delay TX even without RTS 1148 * control therefore we try to handle .delay_rts_before_send. 1149 */ 1150 if (rs485->delay_rts_after_send) 1151 return -EINVAL; 1152 } 1153 1154 one->config.flags |= SC16IS7XX_RECONF_RS485; 1155 kthread_queue_work(&s->kworker, &one->reg_work); 1156 1157 return 0; 1158 } 1159 1160 static int sc16is7xx_startup(struct uart_port *port) 1161 { 1162 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 1163 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 1164 unsigned int val; 1165 unsigned long flags; 1166 1167 sc16is7xx_power(port, 1); 1168 1169 /* Reset FIFOs*/ 1170 val = SC16IS7XX_FCR_RXRESET_BIT | SC16IS7XX_FCR_TXRESET_BIT; 1171 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG, val); 1172 udelay(5); 1173 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG, 1174 SC16IS7XX_FCR_FIFO_BIT); 1175 1176 /* Enable EFR */ 1177 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, 1178 SC16IS7XX_LCR_CONF_MODE_B); 1179 1180 regcache_cache_bypass(s->regmap, true); 1181 1182 /* Enable write access to enhanced features and internal clock div */ 1183 sc16is7xx_port_update(port, SC16IS7XX_EFR_REG, 1184 SC16IS7XX_EFR_ENABLE_BIT, 1185 SC16IS7XX_EFR_ENABLE_BIT); 1186 1187 /* Enable TCR/TLR */ 1188 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG, 1189 SC16IS7XX_MCR_TCRTLR_BIT, 1190 SC16IS7XX_MCR_TCRTLR_BIT); 1191 1192 /* Configure flow control levels */ 1193 /* Flow control halt level 48, resume level 24 */ 1194 sc16is7xx_port_write(port, SC16IS7XX_TCR_REG, 1195 SC16IS7XX_TCR_RX_RESUME(24) | 1196 SC16IS7XX_TCR_RX_HALT(48)); 1197 1198 regcache_cache_bypass(s->regmap, false); 1199 1200 /* Now, initialize the UART */ 1201 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, SC16IS7XX_LCR_WORD_LEN_8); 1202 1203 /* Enable IrDA mode if requested in DT */ 1204 /* This bit must be written with LCR[7] = 0 */ 1205 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG, 1206 SC16IS7XX_MCR_IRDA_BIT, 1207 one->irda_mode ? 1208 SC16IS7XX_MCR_IRDA_BIT : 0); 1209 1210 /* Enable the Rx and Tx FIFO */ 1211 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, 1212 SC16IS7XX_EFCR_RXDISABLE_BIT | 1213 SC16IS7XX_EFCR_TXDISABLE_BIT, 1214 0); 1215 1216 /* Enable RX, CTS change and modem lines interrupts */ 1217 val = SC16IS7XX_IER_RDI_BIT | SC16IS7XX_IER_CTSI_BIT | 1218 SC16IS7XX_IER_MSI_BIT; 1219 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, val); 1220 1221 /* Enable modem status polling */ 1222 uart_port_lock_irqsave(port, &flags); 1223 sc16is7xx_enable_ms(port); 1224 uart_port_unlock_irqrestore(port, flags); 1225 1226 return 0; 1227 } 1228 1229 static void sc16is7xx_shutdown(struct uart_port *port) 1230 { 1231 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 1232 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 1233 1234 kthread_cancel_delayed_work_sync(&one->ms_work); 1235 1236 /* Disable all interrupts */ 1237 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, 0); 1238 /* Disable TX/RX */ 1239 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, 1240 SC16IS7XX_EFCR_RXDISABLE_BIT | 1241 SC16IS7XX_EFCR_TXDISABLE_BIT, 1242 SC16IS7XX_EFCR_RXDISABLE_BIT | 1243 SC16IS7XX_EFCR_TXDISABLE_BIT); 1244 1245 sc16is7xx_power(port, 0); 1246 1247 kthread_flush_worker(&s->kworker); 1248 } 1249 1250 static const char *sc16is7xx_type(struct uart_port *port) 1251 { 1252 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 1253 1254 return (port->type == PORT_SC16IS7XX) ? s->devtype->name : NULL; 1255 } 1256 1257 static int sc16is7xx_request_port(struct uart_port *port) 1258 { 1259 /* Do nothing */ 1260 return 0; 1261 } 1262 1263 static void sc16is7xx_config_port(struct uart_port *port, int flags) 1264 { 1265 if (flags & UART_CONFIG_TYPE) 1266 port->type = PORT_SC16IS7XX; 1267 } 1268 1269 static int sc16is7xx_verify_port(struct uart_port *port, 1270 struct serial_struct *s) 1271 { 1272 if ((s->type != PORT_UNKNOWN) && (s->type != PORT_SC16IS7XX)) 1273 return -EINVAL; 1274 if (s->irq != port->irq) 1275 return -EINVAL; 1276 1277 return 0; 1278 } 1279 1280 static void sc16is7xx_pm(struct uart_port *port, unsigned int state, 1281 unsigned int oldstate) 1282 { 1283 sc16is7xx_power(port, (state == UART_PM_STATE_ON) ? 1 : 0); 1284 } 1285 1286 static void sc16is7xx_null_void(struct uart_port *port) 1287 { 1288 /* Do nothing */ 1289 } 1290 1291 static const struct uart_ops sc16is7xx_ops = { 1292 .tx_empty = sc16is7xx_tx_empty, 1293 .set_mctrl = sc16is7xx_set_mctrl, 1294 .get_mctrl = sc16is7xx_get_mctrl, 1295 .stop_tx = sc16is7xx_stop_tx, 1296 .start_tx = sc16is7xx_start_tx, 1297 .throttle = sc16is7xx_throttle, 1298 .unthrottle = sc16is7xx_unthrottle, 1299 .stop_rx = sc16is7xx_stop_rx, 1300 .enable_ms = sc16is7xx_enable_ms, 1301 .break_ctl = sc16is7xx_break_ctl, 1302 .startup = sc16is7xx_startup, 1303 .shutdown = sc16is7xx_shutdown, 1304 .set_termios = sc16is7xx_set_termios, 1305 .type = sc16is7xx_type, 1306 .request_port = sc16is7xx_request_port, 1307 .release_port = sc16is7xx_null_void, 1308 .config_port = sc16is7xx_config_port, 1309 .verify_port = sc16is7xx_verify_port, 1310 .pm = sc16is7xx_pm, 1311 }; 1312 1313 #ifdef CONFIG_GPIOLIB 1314 static int sc16is7xx_gpio_get(struct gpio_chip *chip, unsigned offset) 1315 { 1316 unsigned int val; 1317 struct sc16is7xx_port *s = gpiochip_get_data(chip); 1318 struct uart_port *port = &s->p[0].port; 1319 1320 val = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG); 1321 1322 return !!(val & BIT(offset)); 1323 } 1324 1325 static void sc16is7xx_gpio_set(struct gpio_chip *chip, unsigned offset, int val) 1326 { 1327 struct sc16is7xx_port *s = gpiochip_get_data(chip); 1328 struct uart_port *port = &s->p[0].port; 1329 1330 sc16is7xx_port_update(port, SC16IS7XX_IOSTATE_REG, BIT(offset), 1331 val ? BIT(offset) : 0); 1332 } 1333 1334 static int sc16is7xx_gpio_direction_input(struct gpio_chip *chip, 1335 unsigned offset) 1336 { 1337 struct sc16is7xx_port *s = gpiochip_get_data(chip); 1338 struct uart_port *port = &s->p[0].port; 1339 1340 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset), 0); 1341 1342 return 0; 1343 } 1344 1345 static int sc16is7xx_gpio_direction_output(struct gpio_chip *chip, 1346 unsigned offset, int val) 1347 { 1348 struct sc16is7xx_port *s = gpiochip_get_data(chip); 1349 struct uart_port *port = &s->p[0].port; 1350 u8 state = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG); 1351 1352 if (val) 1353 state |= BIT(offset); 1354 else 1355 state &= ~BIT(offset); 1356 1357 /* 1358 * If we write IOSTATE first, and then IODIR, the output value is not 1359 * transferred to the corresponding I/O pin. 1360 * The datasheet states that each register bit will be transferred to 1361 * the corresponding I/O pin programmed as output when writing to 1362 * IOSTATE. Therefore, configure direction first with IODIR, and then 1363 * set value after with IOSTATE. 1364 */ 1365 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset), 1366 BIT(offset)); 1367 sc16is7xx_port_write(port, SC16IS7XX_IOSTATE_REG, state); 1368 1369 return 0; 1370 } 1371 1372 static int sc16is7xx_gpio_init_valid_mask(struct gpio_chip *chip, 1373 unsigned long *valid_mask, 1374 unsigned int ngpios) 1375 { 1376 struct sc16is7xx_port *s = gpiochip_get_data(chip); 1377 1378 *valid_mask = s->gpio_valid_mask; 1379 1380 return 0; 1381 } 1382 1383 static int sc16is7xx_setup_gpio_chip(struct sc16is7xx_port *s) 1384 { 1385 struct device *dev = s->p[0].port.dev; 1386 1387 if (!s->devtype->nr_gpio) 1388 return 0; 1389 1390 switch (s->mctrl_mask) { 1391 case 0: 1392 s->gpio_valid_mask = GENMASK(7, 0); 1393 break; 1394 case SC16IS7XX_IOCONTROL_MODEM_A_BIT: 1395 s->gpio_valid_mask = GENMASK(3, 0); 1396 break; 1397 case SC16IS7XX_IOCONTROL_MODEM_B_BIT: 1398 s->gpio_valid_mask = GENMASK(7, 4); 1399 break; 1400 default: 1401 break; 1402 } 1403 1404 if (s->gpio_valid_mask == 0) 1405 return 0; 1406 1407 s->gpio.owner = THIS_MODULE; 1408 s->gpio.parent = dev; 1409 s->gpio.label = dev_name(dev); 1410 s->gpio.init_valid_mask = sc16is7xx_gpio_init_valid_mask; 1411 s->gpio.direction_input = sc16is7xx_gpio_direction_input; 1412 s->gpio.get = sc16is7xx_gpio_get; 1413 s->gpio.direction_output = sc16is7xx_gpio_direction_output; 1414 s->gpio.set = sc16is7xx_gpio_set; 1415 s->gpio.base = -1; 1416 s->gpio.ngpio = s->devtype->nr_gpio; 1417 s->gpio.can_sleep = 1; 1418 1419 return gpiochip_add_data(&s->gpio, s); 1420 } 1421 #endif 1422 1423 static void sc16is7xx_setup_irda_ports(struct sc16is7xx_port *s) 1424 { 1425 int i; 1426 int ret; 1427 int count; 1428 u32 irda_port[2]; 1429 struct device *dev = s->p[0].port.dev; 1430 1431 count = device_property_count_u32(dev, "irda-mode-ports"); 1432 if (count < 0 || count > ARRAY_SIZE(irda_port)) 1433 return; 1434 1435 ret = device_property_read_u32_array(dev, "irda-mode-ports", 1436 irda_port, count); 1437 if (ret) 1438 return; 1439 1440 for (i = 0; i < count; i++) { 1441 if (irda_port[i] < s->devtype->nr_uart) 1442 s->p[irda_port[i]].irda_mode = true; 1443 } 1444 } 1445 1446 /* 1447 * Configure ports designated to operate as modem control lines. 1448 */ 1449 static int sc16is7xx_setup_mctrl_ports(struct sc16is7xx_port *s) 1450 { 1451 int i; 1452 int ret; 1453 int count; 1454 u32 mctrl_port[2]; 1455 struct device *dev = s->p[0].port.dev; 1456 1457 count = device_property_count_u32(dev, "nxp,modem-control-line-ports"); 1458 if (count < 0 || count > ARRAY_SIZE(mctrl_port)) 1459 return 0; 1460 1461 ret = device_property_read_u32_array(dev, "nxp,modem-control-line-ports", 1462 mctrl_port, count); 1463 if (ret) 1464 return ret; 1465 1466 s->mctrl_mask = 0; 1467 1468 for (i = 0; i < count; i++) { 1469 /* Use GPIO lines as modem control lines */ 1470 if (mctrl_port[i] == 0) 1471 s->mctrl_mask |= SC16IS7XX_IOCONTROL_MODEM_A_BIT; 1472 else if (mctrl_port[i] == 1) 1473 s->mctrl_mask |= SC16IS7XX_IOCONTROL_MODEM_B_BIT; 1474 } 1475 1476 if (s->mctrl_mask) 1477 regmap_update_bits( 1478 s->regmap, 1479 SC16IS7XX_IOCONTROL_REG << SC16IS7XX_REG_SHIFT, 1480 SC16IS7XX_IOCONTROL_MODEM_A_BIT | 1481 SC16IS7XX_IOCONTROL_MODEM_B_BIT, s->mctrl_mask); 1482 1483 return 0; 1484 } 1485 1486 static const struct serial_rs485 sc16is7xx_rs485_supported = { 1487 .flags = SER_RS485_ENABLED | SER_RS485_RTS_AFTER_SEND, 1488 .delay_rts_before_send = 1, 1489 .delay_rts_after_send = 1, /* Not supported but keep returning -EINVAL */ 1490 }; 1491 1492 static int sc16is7xx_probe(struct device *dev, 1493 const struct sc16is7xx_devtype *devtype, 1494 struct regmap *regmap, int irq) 1495 { 1496 unsigned long freq = 0, *pfreq = dev_get_platdata(dev); 1497 unsigned int val; 1498 u32 uartclk = 0; 1499 int i, ret; 1500 struct sc16is7xx_port *s; 1501 1502 if (IS_ERR(regmap)) 1503 return PTR_ERR(regmap); 1504 1505 /* 1506 * This device does not have an identification register that would 1507 * tell us if we are really connected to the correct device. 1508 * The best we can do is to check if communication is at all possible. 1509 */ 1510 ret = regmap_read(regmap, 1511 SC16IS7XX_LSR_REG << SC16IS7XX_REG_SHIFT, &val); 1512 if (ret < 0) 1513 return -EPROBE_DEFER; 1514 1515 /* Alloc port structure */ 1516 s = devm_kzalloc(dev, struct_size(s, p, devtype->nr_uart), GFP_KERNEL); 1517 if (!s) { 1518 dev_err(dev, "Error allocating port structure\n"); 1519 return -ENOMEM; 1520 } 1521 1522 /* Always ask for fixed clock rate from a property. */ 1523 device_property_read_u32(dev, "clock-frequency", &uartclk); 1524 1525 s->clk = devm_clk_get_optional(dev, NULL); 1526 if (IS_ERR(s->clk)) 1527 return PTR_ERR(s->clk); 1528 1529 ret = clk_prepare_enable(s->clk); 1530 if (ret) 1531 return ret; 1532 1533 freq = clk_get_rate(s->clk); 1534 if (freq == 0) { 1535 if (uartclk) 1536 freq = uartclk; 1537 if (pfreq) 1538 freq = *pfreq; 1539 if (freq) 1540 dev_dbg(dev, "Clock frequency: %luHz\n", freq); 1541 else 1542 return -EINVAL; 1543 } 1544 1545 s->regmap = regmap; 1546 s->devtype = devtype; 1547 dev_set_drvdata(dev, s); 1548 mutex_init(&s->efr_lock); 1549 1550 kthread_init_worker(&s->kworker); 1551 s->kworker_task = kthread_run(kthread_worker_fn, &s->kworker, 1552 "sc16is7xx"); 1553 if (IS_ERR(s->kworker_task)) { 1554 ret = PTR_ERR(s->kworker_task); 1555 goto out_clk; 1556 } 1557 sched_set_fifo(s->kworker_task); 1558 1559 /* reset device, purging any pending irq / data */ 1560 regmap_write(s->regmap, SC16IS7XX_IOCONTROL_REG << SC16IS7XX_REG_SHIFT, 1561 SC16IS7XX_IOCONTROL_SRESET_BIT); 1562 1563 for (i = 0; i < devtype->nr_uart; ++i) { 1564 s->p[i].line = i; 1565 /* Initialize port data */ 1566 s->p[i].port.dev = dev; 1567 s->p[i].port.irq = irq; 1568 s->p[i].port.type = PORT_SC16IS7XX; 1569 s->p[i].port.fifosize = SC16IS7XX_FIFO_SIZE; 1570 s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY; 1571 s->p[i].port.iobase = i; 1572 /* 1573 * Use all ones as membase to make sure uart_configure_port() in 1574 * serial_core.c does not abort for SPI/I2C devices where the 1575 * membase address is not applicable. 1576 */ 1577 s->p[i].port.membase = (void __iomem *)~0; 1578 s->p[i].port.iotype = UPIO_PORT; 1579 s->p[i].port.uartclk = freq; 1580 s->p[i].port.rs485_config = sc16is7xx_config_rs485; 1581 s->p[i].port.rs485_supported = sc16is7xx_rs485_supported; 1582 s->p[i].port.ops = &sc16is7xx_ops; 1583 s->p[i].old_mctrl = 0; 1584 s->p[i].port.line = sc16is7xx_alloc_line(); 1585 1586 if (s->p[i].port.line >= SC16IS7XX_MAX_DEVS) { 1587 ret = -ENOMEM; 1588 goto out_ports; 1589 } 1590 1591 ret = uart_get_rs485_mode(&s->p[i].port); 1592 if (ret) 1593 goto out_ports; 1594 1595 /* Disable all interrupts */ 1596 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_IER_REG, 0); 1597 /* Disable TX/RX */ 1598 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_EFCR_REG, 1599 SC16IS7XX_EFCR_RXDISABLE_BIT | 1600 SC16IS7XX_EFCR_TXDISABLE_BIT); 1601 1602 /* Initialize kthread work structs */ 1603 kthread_init_work(&s->p[i].tx_work, sc16is7xx_tx_proc); 1604 kthread_init_work(&s->p[i].reg_work, sc16is7xx_reg_proc); 1605 kthread_init_delayed_work(&s->p[i].ms_work, sc16is7xx_ms_proc); 1606 /* Register port */ 1607 uart_add_one_port(&sc16is7xx_uart, &s->p[i].port); 1608 1609 /* Enable EFR */ 1610 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_LCR_REG, 1611 SC16IS7XX_LCR_CONF_MODE_B); 1612 1613 regcache_cache_bypass(s->regmap, true); 1614 1615 /* Enable write access to enhanced features */ 1616 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_EFR_REG, 1617 SC16IS7XX_EFR_ENABLE_BIT); 1618 1619 regcache_cache_bypass(s->regmap, false); 1620 1621 /* Restore access to general registers */ 1622 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_LCR_REG, 0x00); 1623 1624 /* Go to suspend mode */ 1625 sc16is7xx_power(&s->p[i].port, 0); 1626 } 1627 1628 sc16is7xx_setup_irda_ports(s); 1629 1630 ret = sc16is7xx_setup_mctrl_ports(s); 1631 if (ret) 1632 goto out_ports; 1633 1634 #ifdef CONFIG_GPIOLIB 1635 ret = sc16is7xx_setup_gpio_chip(s); 1636 if (ret) 1637 goto out_ports; 1638 #endif 1639 1640 /* 1641 * Setup interrupt. We first try to acquire the IRQ line as level IRQ. 1642 * If that succeeds, we can allow sharing the interrupt as well. 1643 * In case the interrupt controller doesn't support that, we fall 1644 * back to a non-shared falling-edge trigger. 1645 */ 1646 ret = devm_request_threaded_irq(dev, irq, NULL, sc16is7xx_irq, 1647 IRQF_TRIGGER_LOW | IRQF_SHARED | 1648 IRQF_ONESHOT, 1649 dev_name(dev), s); 1650 if (!ret) 1651 return 0; 1652 1653 ret = devm_request_threaded_irq(dev, irq, NULL, sc16is7xx_irq, 1654 IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 1655 dev_name(dev), s); 1656 if (!ret) 1657 return 0; 1658 1659 #ifdef CONFIG_GPIOLIB 1660 if (s->gpio_valid_mask) 1661 gpiochip_remove(&s->gpio); 1662 #endif 1663 1664 out_ports: 1665 for (i--; i >= 0; i--) { 1666 uart_remove_one_port(&sc16is7xx_uart, &s->p[i].port); 1667 clear_bit(s->p[i].port.line, &sc16is7xx_lines); 1668 } 1669 1670 kthread_stop(s->kworker_task); 1671 1672 out_clk: 1673 clk_disable_unprepare(s->clk); 1674 1675 return ret; 1676 } 1677 1678 static void sc16is7xx_remove(struct device *dev) 1679 { 1680 struct sc16is7xx_port *s = dev_get_drvdata(dev); 1681 int i; 1682 1683 #ifdef CONFIG_GPIOLIB 1684 if (s->gpio_valid_mask) 1685 gpiochip_remove(&s->gpio); 1686 #endif 1687 1688 for (i = 0; i < s->devtype->nr_uart; i++) { 1689 kthread_cancel_delayed_work_sync(&s->p[i].ms_work); 1690 uart_remove_one_port(&sc16is7xx_uart, &s->p[i].port); 1691 clear_bit(s->p[i].port.line, &sc16is7xx_lines); 1692 sc16is7xx_power(&s->p[i].port, 0); 1693 } 1694 1695 kthread_flush_worker(&s->kworker); 1696 kthread_stop(s->kworker_task); 1697 1698 clk_disable_unprepare(s->clk); 1699 } 1700 1701 static const struct of_device_id __maybe_unused sc16is7xx_dt_ids[] = { 1702 { .compatible = "nxp,sc16is740", .data = &sc16is74x_devtype, }, 1703 { .compatible = "nxp,sc16is741", .data = &sc16is74x_devtype, }, 1704 { .compatible = "nxp,sc16is750", .data = &sc16is750_devtype, }, 1705 { .compatible = "nxp,sc16is752", .data = &sc16is752_devtype, }, 1706 { .compatible = "nxp,sc16is760", .data = &sc16is760_devtype, }, 1707 { .compatible = "nxp,sc16is762", .data = &sc16is762_devtype, }, 1708 { } 1709 }; 1710 MODULE_DEVICE_TABLE(of, sc16is7xx_dt_ids); 1711 1712 static struct regmap_config regcfg = { 1713 .reg_bits = 7, 1714 .pad_bits = 1, 1715 .val_bits = 8, 1716 .cache_type = REGCACHE_RBTREE, 1717 .volatile_reg = sc16is7xx_regmap_volatile, 1718 .precious_reg = sc16is7xx_regmap_precious, 1719 }; 1720 1721 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI 1722 static int sc16is7xx_spi_probe(struct spi_device *spi) 1723 { 1724 const struct sc16is7xx_devtype *devtype; 1725 struct regmap *regmap; 1726 int ret; 1727 1728 /* Setup SPI bus */ 1729 spi->bits_per_word = 8; 1730 /* only supports mode 0 on SC16IS762 */ 1731 spi->mode = spi->mode ? : SPI_MODE_0; 1732 spi->max_speed_hz = spi->max_speed_hz ? : 15000000; 1733 ret = spi_setup(spi); 1734 if (ret) 1735 return ret; 1736 1737 if (spi->dev.of_node) { 1738 devtype = device_get_match_data(&spi->dev); 1739 if (!devtype) 1740 return -ENODEV; 1741 } else { 1742 const struct spi_device_id *id_entry = spi_get_device_id(spi); 1743 1744 devtype = (struct sc16is7xx_devtype *)id_entry->driver_data; 1745 } 1746 1747 regcfg.max_register = (0xf << SC16IS7XX_REG_SHIFT) | 1748 (devtype->nr_uart - 1); 1749 regmap = devm_regmap_init_spi(spi, ®cfg); 1750 1751 return sc16is7xx_probe(&spi->dev, devtype, regmap, spi->irq); 1752 } 1753 1754 static void sc16is7xx_spi_remove(struct spi_device *spi) 1755 { 1756 sc16is7xx_remove(&spi->dev); 1757 } 1758 1759 static const struct spi_device_id sc16is7xx_spi_id_table[] = { 1760 { "sc16is74x", (kernel_ulong_t)&sc16is74x_devtype, }, 1761 { "sc16is740", (kernel_ulong_t)&sc16is74x_devtype, }, 1762 { "sc16is741", (kernel_ulong_t)&sc16is74x_devtype, }, 1763 { "sc16is750", (kernel_ulong_t)&sc16is750_devtype, }, 1764 { "sc16is752", (kernel_ulong_t)&sc16is752_devtype, }, 1765 { "sc16is760", (kernel_ulong_t)&sc16is760_devtype, }, 1766 { "sc16is762", (kernel_ulong_t)&sc16is762_devtype, }, 1767 { } 1768 }; 1769 1770 MODULE_DEVICE_TABLE(spi, sc16is7xx_spi_id_table); 1771 1772 static struct spi_driver sc16is7xx_spi_uart_driver = { 1773 .driver = { 1774 .name = SC16IS7XX_NAME, 1775 .of_match_table = sc16is7xx_dt_ids, 1776 }, 1777 .probe = sc16is7xx_spi_probe, 1778 .remove = sc16is7xx_spi_remove, 1779 .id_table = sc16is7xx_spi_id_table, 1780 }; 1781 1782 MODULE_ALIAS("spi:sc16is7xx"); 1783 #endif 1784 1785 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C 1786 static int sc16is7xx_i2c_probe(struct i2c_client *i2c) 1787 { 1788 const struct i2c_device_id *id = i2c_client_get_device_id(i2c); 1789 const struct sc16is7xx_devtype *devtype; 1790 struct regmap *regmap; 1791 1792 if (i2c->dev.of_node) { 1793 devtype = device_get_match_data(&i2c->dev); 1794 if (!devtype) 1795 return -ENODEV; 1796 } else { 1797 devtype = (struct sc16is7xx_devtype *)id->driver_data; 1798 } 1799 1800 regcfg.max_register = (0xf << SC16IS7XX_REG_SHIFT) | 1801 (devtype->nr_uart - 1); 1802 regmap = devm_regmap_init_i2c(i2c, ®cfg); 1803 1804 return sc16is7xx_probe(&i2c->dev, devtype, regmap, i2c->irq); 1805 } 1806 1807 static void sc16is7xx_i2c_remove(struct i2c_client *client) 1808 { 1809 sc16is7xx_remove(&client->dev); 1810 } 1811 1812 static const struct i2c_device_id sc16is7xx_i2c_id_table[] = { 1813 { "sc16is74x", (kernel_ulong_t)&sc16is74x_devtype, }, 1814 { "sc16is740", (kernel_ulong_t)&sc16is74x_devtype, }, 1815 { "sc16is741", (kernel_ulong_t)&sc16is74x_devtype, }, 1816 { "sc16is750", (kernel_ulong_t)&sc16is750_devtype, }, 1817 { "sc16is752", (kernel_ulong_t)&sc16is752_devtype, }, 1818 { "sc16is760", (kernel_ulong_t)&sc16is760_devtype, }, 1819 { "sc16is762", (kernel_ulong_t)&sc16is762_devtype, }, 1820 { } 1821 }; 1822 MODULE_DEVICE_TABLE(i2c, sc16is7xx_i2c_id_table); 1823 1824 static struct i2c_driver sc16is7xx_i2c_uart_driver = { 1825 .driver = { 1826 .name = SC16IS7XX_NAME, 1827 .of_match_table = sc16is7xx_dt_ids, 1828 }, 1829 .probe = sc16is7xx_i2c_probe, 1830 .remove = sc16is7xx_i2c_remove, 1831 .id_table = sc16is7xx_i2c_id_table, 1832 }; 1833 1834 #endif 1835 1836 static int __init sc16is7xx_init(void) 1837 { 1838 int ret; 1839 1840 ret = uart_register_driver(&sc16is7xx_uart); 1841 if (ret) { 1842 pr_err("Registering UART driver failed\n"); 1843 return ret; 1844 } 1845 1846 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C 1847 ret = i2c_add_driver(&sc16is7xx_i2c_uart_driver); 1848 if (ret < 0) { 1849 pr_err("failed to init sc16is7xx i2c --> %d\n", ret); 1850 goto err_i2c; 1851 } 1852 #endif 1853 1854 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI 1855 ret = spi_register_driver(&sc16is7xx_spi_uart_driver); 1856 if (ret < 0) { 1857 pr_err("failed to init sc16is7xx spi --> %d\n", ret); 1858 goto err_spi; 1859 } 1860 #endif 1861 return ret; 1862 1863 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI 1864 err_spi: 1865 #endif 1866 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C 1867 i2c_del_driver(&sc16is7xx_i2c_uart_driver); 1868 err_i2c: 1869 #endif 1870 uart_unregister_driver(&sc16is7xx_uart); 1871 return ret; 1872 } 1873 module_init(sc16is7xx_init); 1874 1875 static void __exit sc16is7xx_exit(void) 1876 { 1877 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C 1878 i2c_del_driver(&sc16is7xx_i2c_uart_driver); 1879 #endif 1880 1881 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI 1882 spi_unregister_driver(&sc16is7xx_spi_uart_driver); 1883 #endif 1884 uart_unregister_driver(&sc16is7xx_uart); 1885 } 1886 module_exit(sc16is7xx_exit); 1887 1888 MODULE_LICENSE("GPL"); 1889 MODULE_AUTHOR("Jon Ringle <jringle@gridpoint.com>"); 1890 MODULE_DESCRIPTION("SC16IS7XX serial driver"); 1891