1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Faraday FOTG210 USB OTG controller 4 * 5 * Copyright (C) 2013 Faraday Technology Corporation 6 * Author: Yuan-Hsin Chen <yhchen@faraday-tech.com> 7 */ 8 9 #include <linux/kernel.h> 10 11 #define FOTG210_MAX_NUM_EP 5 /* ep0...ep4 */ 12 #define FOTG210_MAX_FIFO_NUM 4 /* fifo0...fifo4 */ 13 14 /* Global Mask of HC/OTG/DEV interrupt Register(0xC4) */ 15 #define FOTG210_GMIR 0xC4 16 #define GMIR_INT_POLARITY 0x8 /*Active High*/ 17 #define GMIR_MHC_INT 0x4 18 #define GMIR_MOTG_INT 0x2 19 #define GMIR_MDEV_INT 0x1 20 21 /* Device Main Control Register(0x100) */ 22 #define FOTG210_DMCR 0x100 23 #define DMCR_HS_EN (1 << 6) 24 #define DMCR_CHIP_EN (1 << 5) 25 #define DMCR_SFRST (1 << 4) 26 #define DMCR_GOSUSP (1 << 3) 27 #define DMCR_GLINT_EN (1 << 2) 28 #define DMCR_HALF_SPEED (1 << 1) 29 #define DMCR_CAP_RMWAKUP (1 << 0) 30 31 /* Device Address Register(0x104) */ 32 #define FOTG210_DAR 0x104 33 #define DAR_AFT_CONF (1 << 7) 34 35 /* Device Test Register(0x108) */ 36 #define FOTG210_DTR 0x108 37 #define DTR_TST_CLRFF (1 << 0) 38 39 /* PHY Test Mode Selector register(0x114) */ 40 #define FOTG210_PHYTMSR 0x114 41 #define PHYTMSR_TST_PKT (1 << 4) 42 #define PHYTMSR_TST_SE0NAK (1 << 3) 43 #define PHYTMSR_TST_KSTA (1 << 2) 44 #define PHYTMSR_TST_JSTA (1 << 1) 45 #define PHYTMSR_UNPLUG (1 << 0) 46 47 /* Cx configuration and FIFO Empty Status register(0x120) */ 48 #define FOTG210_DCFESR 0x120 49 #define DCFESR_FIFO_EMPTY(fifo) (1 << 8 << (fifo)) 50 #define DCFESR_CX_EMP (1 << 5) 51 #define DCFESR_CX_CLR (1 << 3) 52 #define DCFESR_CX_STL (1 << 2) 53 #define DCFESR_TST_PKDONE (1 << 1) 54 #define DCFESR_CX_DONE (1 << 0) 55 56 /* Device IDLE Counter Register(0x124) */ 57 #define FOTG210_DICR 0x124 58 59 /* Device Mask of Interrupt Group Register (0x130) */ 60 #define FOTG210_DMIGR 0x130 61 #define DMIGR_MINT_G0 (1 << 0) 62 63 /* Device Mask of Interrupt Source Group 0(0x134) */ 64 #define FOTG210_DMISGR0 0x134 65 #define DMISGR0_MCX_COMEND (1 << 3) 66 #define DMISGR0_MCX_OUT_INT (1 << 2) 67 #define DMISGR0_MCX_IN_INT (1 << 1) 68 #define DMISGR0_MCX_SETUP_INT (1 << 0) 69 70 /* Device Mask of Interrupt Source Group 1 Register(0x138)*/ 71 #define FOTG210_DMISGR1 0x138 72 #define DMISGR1_MF3_IN_INT (1 << 19) 73 #define DMISGR1_MF2_IN_INT (1 << 18) 74 #define DMISGR1_MF1_IN_INT (1 << 17) 75 #define DMISGR1_MF0_IN_INT (1 << 16) 76 #define DMISGR1_MF_IN_INT(fifo) (1 << (16 + (fifo))) 77 #define DMISGR1_MF3_SPK_INT (1 << 7) 78 #define DMISGR1_MF3_OUT_INT (1 << 6) 79 #define DMISGR1_MF2_SPK_INT (1 << 5) 80 #define DMISGR1_MF2_OUT_INT (1 << 4) 81 #define DMISGR1_MF1_SPK_INT (1 << 3) 82 #define DMISGR1_MF1_OUT_INT (1 << 2) 83 #define DMISGR1_MF0_SPK_INT (1 << 1) 84 #define DMISGR1_MF0_OUT_INT (1 << 0) 85 #define DMISGR1_MF_OUTSPK_INT(fifo) (0x3 << (fifo) * 2) 86 87 /* Device Mask of Interrupt Source Group 2 Register (0x13C) */ 88 #define FOTG210_DMISGR2 0x13C 89 #define DMISGR2_MDMA_ERROR (1 << 8) 90 #define DMISGR2_MDMA_CMPLT (1 << 7) 91 92 /* Device Interrupt group Register (0x140) */ 93 #define FOTG210_DIGR 0x140 94 #define DIGR_INT_G2 (1 << 2) 95 #define DIGR_INT_G1 (1 << 1) 96 #define DIGR_INT_G0 (1 << 0) 97 98 /* Device Interrupt Source Group 0 Register (0x144) */ 99 #define FOTG210_DISGR0 0x144 100 #define DISGR0_CX_COMABT_INT (1 << 5) 101 #define DISGR0_CX_COMFAIL_INT (1 << 4) 102 #define DISGR0_CX_COMEND_INT (1 << 3) 103 #define DISGR0_CX_OUT_INT (1 << 2) 104 #define DISGR0_CX_IN_INT (1 << 1) 105 #define DISGR0_CX_SETUP_INT (1 << 0) 106 107 /* Device Interrupt Source Group 1 Register (0x148) */ 108 #define FOTG210_DISGR1 0x148 109 #define DISGR1_OUT_INT(fifo) (1 << ((fifo) * 2)) 110 #define DISGR1_SPK_INT(fifo) (1 << 1 << ((fifo) * 2)) 111 #define DISGR1_IN_INT(fifo) (1 << 16 << (fifo)) 112 113 /* Device Interrupt Source Group 2 Register (0x14C) */ 114 #define FOTG210_DISGR2 0x14C 115 #define DISGR2_DMA_ERROR (1 << 8) 116 #define DISGR2_DMA_CMPLT (1 << 7) 117 #define DISGR2_RX0BYTE_INT (1 << 6) 118 #define DISGR2_TX0BYTE_INT (1 << 5) 119 #define DISGR2_ISO_SEQ_ABORT_INT (1 << 4) 120 #define DISGR2_ISO_SEQ_ERR_INT (1 << 3) 121 #define DISGR2_RESM_INT (1 << 2) 122 #define DISGR2_SUSP_INT (1 << 1) 123 #define DISGR2_USBRST_INT (1 << 0) 124 125 /* Device Receive Zero-Length Data Packet Register (0x150)*/ 126 #define FOTG210_RX0BYTE 0x150 127 #define RX0BYTE_EP8 (1 << 7) 128 #define RX0BYTE_EP7 (1 << 6) 129 #define RX0BYTE_EP6 (1 << 5) 130 #define RX0BYTE_EP5 (1 << 4) 131 #define RX0BYTE_EP4 (1 << 3) 132 #define RX0BYTE_EP3 (1 << 2) 133 #define RX0BYTE_EP2 (1 << 1) 134 #define RX0BYTE_EP1 (1 << 0) 135 136 /* Device Transfer Zero-Length Data Packet Register (0x154)*/ 137 #define FOTG210_TX0BYTE 0x154 138 #define TX0BYTE_EP8 (1 << 7) 139 #define TX0BYTE_EP7 (1 << 6) 140 #define TX0BYTE_EP6 (1 << 5) 141 #define TX0BYTE_EP5 (1 << 4) 142 #define TX0BYTE_EP4 (1 << 3) 143 #define TX0BYTE_EP3 (1 << 2) 144 #define TX0BYTE_EP2 (1 << 1) 145 #define TX0BYTE_EP1 (1 << 0) 146 147 /* Device IN Endpoint x MaxPacketSize Register(0x160+4*(x-1)) */ 148 #define FOTG210_INEPMPSR(ep) (0x160 + 4 * ((ep) - 1)) 149 #define INOUTEPMPSR_MPS(mps) ((mps) & 0x2FF) 150 #define INOUTEPMPSR_STL_EP (1 << 11) 151 #define INOUTEPMPSR_RESET_TSEQ (1 << 12) 152 153 /* Device OUT Endpoint x MaxPacketSize Register(0x180+4*(x-1)) */ 154 #define FOTG210_OUTEPMPSR(ep) (0x180 + 4 * ((ep) - 1)) 155 156 /* Device Endpoint 1~4 Map Register (0x1A0) */ 157 #define FOTG210_EPMAP 0x1A0 158 #define EPMAP_FIFONO(ep, dir) \ 159 ((((ep) - 1) << ((ep) - 1) * 8) << ((dir) ? 0 : 4)) 160 #define EPMAP_FIFONOMSK(ep, dir) \ 161 ((3 << ((ep) - 1) * 8) << ((dir) ? 0 : 4)) 162 163 /* Device FIFO Map Register (0x1A8) */ 164 #define FOTG210_FIFOMAP 0x1A8 165 #define FIFOMAP_DIROUT(fifo) (0x0 << 4 << (fifo) * 8) 166 #define FIFOMAP_DIRIN(fifo) (0x1 << 4 << (fifo) * 8) 167 #define FIFOMAP_BIDIR(fifo) (0x2 << 4 << (fifo) * 8) 168 #define FIFOMAP_NA(fifo) (0x3 << 4 << (fifo) * 8) 169 #define FIFOMAP_EPNO(ep) ((ep) << ((ep) - 1) * 8) 170 #define FIFOMAP_EPNOMSK(ep) (0xF << ((ep) - 1) * 8) 171 172 /* Device FIFO Confuguration Register (0x1AC) */ 173 #define FOTG210_FIFOCF 0x1AC 174 #define FIFOCF_TYPE(type, fifo) ((type) << (fifo) * 8) 175 #define FIFOCF_BLK_SIN(fifo) (0x0 << (fifo) * 8 << 2) 176 #define FIFOCF_BLK_DUB(fifo) (0x1 << (fifo) * 8 << 2) 177 #define FIFOCF_BLK_TRI(fifo) (0x2 << (fifo) * 8 << 2) 178 #define FIFOCF_BLKSZ_512(fifo) (0x0 << (fifo) * 8 << 4) 179 #define FIFOCF_BLKSZ_1024(fifo) (0x1 << (fifo) * 8 << 4) 180 #define FIFOCF_FIFO_EN(fifo) (0x1 << (fifo) * 8 << 5) 181 182 /* Device FIFO n Instruction and Byte Count Register (0x1B0+4*n) */ 183 #define FOTG210_FIBCR(fifo) (0x1B0 + (fifo) * 4) 184 #define FIBCR_BCFX 0x7FF 185 #define FIBCR_FFRST (1 << 12) 186 187 /* Device DMA Target FIFO Number Register (0x1C0) */ 188 #define FOTG210_DMATFNR 0x1C0 189 #define DMATFNR_ACC_CXF (1 << 4) 190 #define DMATFNR_ACC_F3 (1 << 3) 191 #define DMATFNR_ACC_F2 (1 << 2) 192 #define DMATFNR_ACC_F1 (1 << 1) 193 #define DMATFNR_ACC_F0 (1 << 0) 194 #define DMATFNR_ACC_FN(fifo) (1 << (fifo)) 195 #define DMATFNR_DISDMA 0 196 197 /* Device DMA Controller Parameter setting 1 Register (0x1C8) */ 198 #define FOTG210_DMACPSR1 0x1C8 199 #define DMACPSR1_DMA_LEN(len) (((len) & 0xFFFF) << 8) 200 #define DMACPSR1_DMA_ABORT (1 << 3) 201 #define DMACPSR1_DMA_TYPE(dir_in) (((dir_in) ? 1 : 0) << 1) 202 #define DMACPSR1_DMA_START (1 << 0) 203 204 /* Device DMA Controller Parameter setting 2 Register (0x1CC) */ 205 #define FOTG210_DMACPSR2 0x1CC 206 207 /* Device DMA Controller Parameter setting 3 Register (0x1CC) */ 208 #define FOTG210_CXPORT 0x1D0 209 210 struct fotg210_request { 211 struct usb_request req; 212 struct list_head queue; 213 }; 214 215 struct fotg210_ep { 216 struct usb_ep ep; 217 struct fotg210_udc *fotg210; 218 219 struct list_head queue; 220 unsigned stall:1; 221 unsigned wedged:1; 222 unsigned use_dma:1; 223 224 unsigned char epnum; 225 unsigned char type; 226 unsigned char dir_in; 227 unsigned int maxp; 228 const struct usb_endpoint_descriptor *desc; 229 }; 230 231 struct fotg210_udc { 232 spinlock_t lock; /* protect the struct */ 233 void __iomem *reg; 234 struct clk *pclk; 235 236 unsigned long irq_trigger; 237 238 struct device *dev; 239 struct usb_phy *phy; 240 struct usb_gadget gadget; 241 struct usb_gadget_driver *driver; 242 243 struct fotg210_ep *ep[FOTG210_MAX_NUM_EP]; 244 245 struct usb_request *ep0_req; /* for internal request */ 246 __le16 ep0_data; 247 u8 ep0_dir; /* 0/0x80 out/in */ 248 249 u8 reenum; /* if re-enumeration */ 250 }; 251 252 #define gadget_to_fotg210(g) container_of((g), struct fotg210_udc, gadget) 253