1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * xHCI host controller driver PCI Bus Glue. 4 * 5 * Copyright (C) 2008 Intel Corp. 6 * 7 * Author: Sarah Sharp 8 * Some code borrowed from the Linux EHCI driver. 9 */ 10 11 #include <linux/pci.h> 12 #include <linux/slab.h> 13 #include <linux/module.h> 14 #include <linux/acpi.h> 15 #include <linux/reset.h> 16 #include <linux/suspend.h> 17 18 #include "xhci.h" 19 #include "xhci-trace.h" 20 #include "xhci-pci.h" 21 22 #define SSIC_PORT_NUM 2 23 #define SSIC_PORT_CFG2 0x880c 24 #define SSIC_PORT_CFG2_OFFSET 0x30 25 #define PROG_DONE (1 << 30) 26 #define SSIC_PORT_UNUSED (1 << 31) 27 #define SPARSE_DISABLE_BIT 17 28 #define SPARSE_CNTL_ENABLE 0xC12C 29 30 /* Device for a quirk */ 31 #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73 32 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000 33 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009 0x1009 34 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1100 0x1100 35 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400 36 37 #define PCI_VENDOR_ID_ETRON 0x1b6f 38 #define PCI_DEVICE_ID_EJ168 0x7023 39 40 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31 41 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31 42 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI 0x9cb1 43 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5 44 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f 45 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f 46 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI 0x0aa8 47 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI 0x1aa8 48 #define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8 49 #define PCI_DEVICE_ID_INTEL_DNV_XHCI 0x19d0 50 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI 0x15b5 51 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI 0x15b6 52 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI 0x15c1 53 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI 0x15db 54 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI 0x15d4 55 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI 0x15e9 56 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI 0x15ec 57 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI 0x15f0 58 #define PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI 0x8a13 59 #define PCI_DEVICE_ID_INTEL_CML_XHCI 0xa3af 60 #define PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI 0x9a13 61 #define PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI 0x1138 62 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI 0x51ed 63 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_N_PCH_XHCI 0x54ed 64 65 #define PCI_DEVICE_ID_AMD_RENOIR_XHCI 0x1639 66 #define PCI_DEVICE_ID_AMD_PROMONTORYA_4 0x43b9 67 #define PCI_DEVICE_ID_AMD_PROMONTORYA_3 0x43ba 68 #define PCI_DEVICE_ID_AMD_PROMONTORYA_2 0x43bb 69 #define PCI_DEVICE_ID_AMD_PROMONTORYA_1 0x43bc 70 71 #define PCI_DEVICE_ID_ASMEDIA_1042_XHCI 0x1042 72 #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI 0x1142 73 #define PCI_DEVICE_ID_ASMEDIA_1142_XHCI 0x1242 74 #define PCI_DEVICE_ID_ASMEDIA_2142_XHCI 0x2142 75 #define PCI_DEVICE_ID_ASMEDIA_3242_XHCI 0x3242 76 77 static const char hcd_name[] = "xhci_hcd"; 78 79 static struct hc_driver __read_mostly xhci_pci_hc_driver; 80 81 static int xhci_pci_setup(struct usb_hcd *hcd); 82 static int xhci_pci_run(struct usb_hcd *hcd); 83 static int xhci_pci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev, 84 struct usb_tt *tt, gfp_t mem_flags); 85 86 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = { 87 .reset = xhci_pci_setup, 88 .start = xhci_pci_run, 89 .update_hub_device = xhci_pci_update_hub_device, 90 }; 91 92 static void xhci_msix_sync_irqs(struct xhci_hcd *xhci) 93 { 94 struct usb_hcd *hcd = xhci_to_hcd(xhci); 95 96 if (hcd->msix_enabled) { 97 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 98 int i; 99 100 for (i = 0; i < xhci->msix_count; i++) 101 synchronize_irq(pci_irq_vector(pdev, i)); 102 } 103 } 104 105 /* Free any IRQs and disable MSI-X */ 106 static void xhci_cleanup_msix(struct xhci_hcd *xhci) 107 { 108 struct usb_hcd *hcd = xhci_to_hcd(xhci); 109 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 110 111 /* return if using legacy interrupt */ 112 if (hcd->irq > 0) 113 return; 114 115 if (hcd->msix_enabled) { 116 int i; 117 118 for (i = 0; i < xhci->msix_count; i++) 119 free_irq(pci_irq_vector(pdev, i), xhci_to_hcd(xhci)); 120 } else { 121 free_irq(pci_irq_vector(pdev, 0), xhci_to_hcd(xhci)); 122 } 123 124 pci_free_irq_vectors(pdev); 125 hcd->msix_enabled = 0; 126 } 127 128 /* 129 * Set up MSI 130 */ 131 static int xhci_setup_msi(struct xhci_hcd *xhci) 132 { 133 int ret; 134 /* 135 * TODO:Check with MSI Soc for sysdev 136 */ 137 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller); 138 139 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI); 140 if (ret < 0) { 141 xhci_dbg_trace(xhci, trace_xhci_dbg_init, 142 "failed to allocate MSI entry"); 143 return ret; 144 } 145 146 ret = request_irq(pdev->irq, xhci_msi_irq, 147 0, "xhci_hcd", xhci_to_hcd(xhci)); 148 if (ret) { 149 xhci_dbg_trace(xhci, trace_xhci_dbg_init, 150 "disable MSI interrupt"); 151 pci_free_irq_vectors(pdev); 152 } 153 154 return ret; 155 } 156 157 /* 158 * Set up MSI-X 159 */ 160 static int xhci_setup_msix(struct xhci_hcd *xhci) 161 { 162 int i, ret; 163 struct usb_hcd *hcd = xhci_to_hcd(xhci); 164 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 165 166 /* 167 * calculate number of msi-x vectors supported. 168 * - HCS_MAX_INTRS: the max number of interrupts the host can handle, 169 * with max number of interrupters based on the xhci HCSPARAMS1. 170 * - num_online_cpus: maximum msi-x vectors per CPUs core. 171 * Add additional 1 vector to ensure always available interrupt. 172 */ 173 xhci->msix_count = min(num_online_cpus() + 1, 174 HCS_MAX_INTRS(xhci->hcs_params1)); 175 176 ret = pci_alloc_irq_vectors(pdev, xhci->msix_count, xhci->msix_count, 177 PCI_IRQ_MSIX); 178 if (ret < 0) { 179 xhci_dbg_trace(xhci, trace_xhci_dbg_init, 180 "Failed to enable MSI-X"); 181 return ret; 182 } 183 184 for (i = 0; i < xhci->msix_count; i++) { 185 ret = request_irq(pci_irq_vector(pdev, i), xhci_msi_irq, 0, 186 "xhci_hcd", xhci_to_hcd(xhci)); 187 if (ret) 188 goto disable_msix; 189 } 190 191 hcd->msix_enabled = 1; 192 return ret; 193 194 disable_msix: 195 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "disable MSI-X interrupt"); 196 while (--i >= 0) 197 free_irq(pci_irq_vector(pdev, i), xhci_to_hcd(xhci)); 198 pci_free_irq_vectors(pdev); 199 return ret; 200 } 201 202 static int xhci_try_enable_msi(struct usb_hcd *hcd) 203 { 204 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 205 struct pci_dev *pdev; 206 int ret; 207 208 pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller); 209 /* 210 * Some Fresco Logic host controllers advertise MSI, but fail to 211 * generate interrupts. Don't even try to enable MSI. 212 */ 213 if (xhci->quirks & XHCI_BROKEN_MSI) 214 goto legacy_irq; 215 216 /* unregister the legacy interrupt */ 217 if (hcd->irq) 218 free_irq(hcd->irq, hcd); 219 hcd->irq = 0; 220 221 ret = xhci_setup_msix(xhci); 222 if (ret) 223 /* fall back to msi*/ 224 ret = xhci_setup_msi(xhci); 225 226 if (!ret) { 227 hcd->msi_enabled = 1; 228 return 0; 229 } 230 231 if (!pdev->irq) { 232 xhci_err(xhci, "No msi-x/msi found and no IRQ in BIOS\n"); 233 return -EINVAL; 234 } 235 236 legacy_irq: 237 if (!strlen(hcd->irq_descr)) 238 snprintf(hcd->irq_descr, sizeof(hcd->irq_descr), "%s:usb%d", 239 hcd->driver->description, hcd->self.busnum); 240 241 /* fall back to legacy interrupt*/ 242 ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED, 243 hcd->irq_descr, hcd); 244 if (ret) { 245 xhci_err(xhci, "request interrupt %d failed\n", 246 pdev->irq); 247 return ret; 248 } 249 hcd->irq = pdev->irq; 250 return 0; 251 } 252 253 static int xhci_pci_run(struct usb_hcd *hcd) 254 { 255 int ret; 256 257 if (usb_hcd_is_primary_hcd(hcd)) { 258 ret = xhci_try_enable_msi(hcd); 259 if (ret) 260 return ret; 261 } 262 263 return xhci_run(hcd); 264 } 265 266 static void xhci_pci_stop(struct usb_hcd *hcd) 267 { 268 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 269 270 xhci_stop(hcd); 271 272 if (usb_hcd_is_primary_hcd(hcd)) 273 xhci_cleanup_msix(xhci); 274 } 275 276 /* called after powerup, by probe or system-pm "wakeup" */ 277 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev) 278 { 279 /* 280 * TODO: Implement finding debug ports later. 281 * TODO: see if there are any quirks that need to be added to handle 282 * new extended capabilities. 283 */ 284 285 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */ 286 if (!pci_set_mwi(pdev)) 287 xhci_dbg(xhci, "MWI active\n"); 288 289 xhci_dbg(xhci, "Finished xhci_pci_reinit\n"); 290 return 0; 291 } 292 293 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci) 294 { 295 struct pci_dev *pdev = to_pci_dev(dev); 296 struct xhci_driver_data *driver_data; 297 const struct pci_device_id *id; 298 299 id = pci_match_id(to_pci_driver(pdev->dev.driver)->id_table, pdev); 300 301 if (id && id->driver_data) { 302 driver_data = (struct xhci_driver_data *)id->driver_data; 303 xhci->quirks |= driver_data->quirks; 304 } 305 306 /* Look for vendor-specific quirks */ 307 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 308 (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK || 309 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) { 310 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && 311 pdev->revision == 0x0) { 312 xhci->quirks |= XHCI_RESET_EP_QUIRK; 313 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 314 "XHCI_RESET_EP_QUIRK for this evaluation HW is deprecated"); 315 } 316 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && 317 pdev->revision == 0x4) { 318 xhci->quirks |= XHCI_SLOW_SUSPEND; 319 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 320 "QUIRK: Fresco Logic xHC revision %u" 321 "must be suspended extra slowly", 322 pdev->revision); 323 } 324 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK) 325 xhci->quirks |= XHCI_BROKEN_STREAMS; 326 /* Fresco Logic confirms: all revisions of this chip do not 327 * support MSI, even though some of them claim to in their PCI 328 * capabilities. 329 */ 330 xhci->quirks |= XHCI_BROKEN_MSI; 331 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 332 "QUIRK: Fresco Logic revision %u " 333 "has broken MSI implementation", 334 pdev->revision); 335 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 336 } 337 338 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 339 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009) 340 xhci->quirks |= XHCI_BROKEN_STREAMS; 341 342 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 343 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1100) 344 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 345 346 if (pdev->vendor == PCI_VENDOR_ID_NEC) 347 xhci->quirks |= XHCI_NEC_HOST; 348 349 if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96) 350 xhci->quirks |= XHCI_AMD_0x96_HOST; 351 352 /* AMD PLL quirk */ 353 if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_quirk_pll_check()) 354 xhci->quirks |= XHCI_AMD_PLL_FIX; 355 356 if (pdev->vendor == PCI_VENDOR_ID_AMD && 357 (pdev->device == 0x145c || 358 pdev->device == 0x15e0 || 359 pdev->device == 0x15e1 || 360 pdev->device == 0x43bb)) 361 xhci->quirks |= XHCI_SUSPEND_DELAY; 362 363 if (pdev->vendor == PCI_VENDOR_ID_AMD && 364 (pdev->device == 0x15e0 || pdev->device == 0x15e1)) 365 xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND; 366 367 if (pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x15e5) { 368 xhci->quirks |= XHCI_DISABLE_SPARSE; 369 xhci->quirks |= XHCI_RESET_ON_RESUME; 370 } 371 372 if (pdev->vendor == PCI_VENDOR_ID_AMD) 373 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 374 375 if ((pdev->vendor == PCI_VENDOR_ID_AMD) && 376 ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) || 377 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) || 378 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) || 379 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1))) 380 xhci->quirks |= XHCI_U2_DISABLE_WAKE; 381 382 if (pdev->vendor == PCI_VENDOR_ID_AMD && 383 pdev->device == PCI_DEVICE_ID_AMD_RENOIR_XHCI) 384 xhci->quirks |= XHCI_BROKEN_D3COLD_S2I; 385 386 if (pdev->vendor == PCI_VENDOR_ID_INTEL) { 387 xhci->quirks |= XHCI_LPM_SUPPORT; 388 xhci->quirks |= XHCI_INTEL_HOST; 389 xhci->quirks |= XHCI_AVOID_BEI; 390 } 391 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 392 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) { 393 xhci->quirks |= XHCI_EP_LIMIT_QUIRK; 394 xhci->limit_active_eps = 64; 395 xhci->quirks |= XHCI_SW_BW_CHECKING; 396 /* 397 * PPT desktop boards DH77EB and DH77DF will power back on after 398 * a few seconds of being shutdown. The fix for this is to 399 * switch the ports from xHCI to EHCI on shutdown. We can't use 400 * DMI information to find those particular boards (since each 401 * vendor will change the board name), so we have to key off all 402 * PPT chipsets. 403 */ 404 xhci->quirks |= XHCI_SPURIOUS_REBOOT; 405 } 406 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 407 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI || 408 pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) { 409 xhci->quirks |= XHCI_SPURIOUS_REBOOT; 410 xhci->quirks |= XHCI_SPURIOUS_WAKEUP; 411 } 412 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 413 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 414 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI || 415 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 416 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI || 417 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI || 418 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI || 419 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI || 420 pdev->device == PCI_DEVICE_ID_INTEL_CML_XHCI)) { 421 xhci->quirks |= XHCI_PME_STUCK_QUIRK; 422 } 423 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 424 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) 425 xhci->quirks |= XHCI_SSIC_PORT_UNUSED; 426 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 427 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 428 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 429 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI)) 430 xhci->quirks |= XHCI_INTEL_USB_ROLE_SW; 431 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 432 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 433 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 434 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI || 435 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI || 436 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI)) 437 xhci->quirks |= XHCI_MISSING_CAS; 438 439 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 440 (pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI || 441 pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_N_PCH_XHCI)) 442 xhci->quirks |= XHCI_RESET_TO_DEFAULT; 443 444 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 445 (pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI || 446 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI || 447 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI || 448 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI || 449 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI || 450 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI || 451 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI || 452 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI || 453 pdev->device == PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI || 454 pdev->device == PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI || 455 pdev->device == PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI)) 456 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW; 457 458 if (pdev->vendor == PCI_VENDOR_ID_ETRON && 459 pdev->device == PCI_DEVICE_ID_EJ168) { 460 xhci->quirks |= XHCI_RESET_ON_RESUME; 461 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 462 xhci->quirks |= XHCI_BROKEN_STREAMS; 463 } 464 if (pdev->vendor == PCI_VENDOR_ID_RENESAS && 465 pdev->device == 0x0014) { 466 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 467 xhci->quirks |= XHCI_ZERO_64B_REGS; 468 } 469 if (pdev->vendor == PCI_VENDOR_ID_RENESAS && 470 pdev->device == 0x0015) { 471 xhci->quirks |= XHCI_RESET_ON_RESUME; 472 xhci->quirks |= XHCI_ZERO_64B_REGS; 473 } 474 if (pdev->vendor == PCI_VENDOR_ID_VIA) 475 xhci->quirks |= XHCI_RESET_ON_RESUME; 476 477 /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */ 478 if (pdev->vendor == PCI_VENDOR_ID_VIA && 479 pdev->device == 0x3432) 480 xhci->quirks |= XHCI_BROKEN_STREAMS; 481 482 if (pdev->vendor == PCI_VENDOR_ID_VIA && pdev->device == 0x3483) 483 xhci->quirks |= XHCI_LPM_SUPPORT; 484 485 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 486 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042_XHCI) { 487 /* 488 * try to tame the ASMedia 1042 controller which reports 0.96 489 * but appears to behave more like 1.0 490 */ 491 xhci->quirks |= XHCI_SPURIOUS_SUCCESS; 492 xhci->quirks |= XHCI_BROKEN_STREAMS; 493 } 494 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 495 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) { 496 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 497 xhci->quirks |= XHCI_NO_64BIT_SUPPORT; 498 } 499 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 500 (pdev->device == PCI_DEVICE_ID_ASMEDIA_1142_XHCI || 501 pdev->device == PCI_DEVICE_ID_ASMEDIA_2142_XHCI || 502 pdev->device == PCI_DEVICE_ID_ASMEDIA_3242_XHCI)) 503 xhci->quirks |= XHCI_NO_64BIT_SUPPORT; 504 505 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 506 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) 507 xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL; 508 509 if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241) 510 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7; 511 512 if ((pdev->vendor == PCI_VENDOR_ID_BROADCOM || 513 pdev->vendor == PCI_VENDOR_ID_CAVIUM) && 514 pdev->device == 0x9026) 515 xhci->quirks |= XHCI_RESET_PLL_ON_DISCONNECT; 516 517 if (pdev->vendor == PCI_VENDOR_ID_AMD && 518 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2 || 519 pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4)) 520 xhci->quirks |= XHCI_NO_SOFT_RETRY; 521 522 if (pdev->vendor == PCI_VENDOR_ID_ZHAOXIN) { 523 xhci->quirks |= XHCI_ZHAOXIN_HOST; 524 xhci->quirks |= XHCI_LPM_SUPPORT; 525 526 if (pdev->device == 0x9202) { 527 xhci->quirks |= XHCI_RESET_ON_RESUME; 528 xhci->quirks |= XHCI_ZHAOXIN_TRB_FETCH; 529 } 530 531 if (pdev->device == 0x9203) 532 xhci->quirks |= XHCI_ZHAOXIN_TRB_FETCH; 533 } 534 535 /* xHC spec requires PCI devices to support D3hot and D3cold */ 536 if (xhci->hci_version >= 0x120) 537 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW; 538 539 if (xhci->quirks & XHCI_RESET_ON_RESUME) 540 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 541 "QUIRK: Resetting on resume"); 542 } 543 544 #ifdef CONFIG_ACPI 545 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) 546 { 547 static const guid_t intel_dsm_guid = 548 GUID_INIT(0xac340cb7, 0xe901, 0x45bf, 549 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23); 550 union acpi_object *obj; 551 552 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1, 553 NULL); 554 ACPI_FREE(obj); 555 } 556 557 static void xhci_find_lpm_incapable_ports(struct usb_hcd *hcd, struct usb_device *hdev) 558 { 559 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 560 struct xhci_hub *rhub = &xhci->usb3_rhub; 561 int ret; 562 int i; 563 564 /* This is not the usb3 roothub we are looking for */ 565 if (hcd != rhub->hcd) 566 return; 567 568 if (hdev->maxchild > rhub->num_ports) { 569 dev_err(&hdev->dev, "USB3 roothub port number mismatch\n"); 570 return; 571 } 572 573 for (i = 0; i < hdev->maxchild; i++) { 574 ret = usb_acpi_port_lpm_incapable(hdev, i); 575 576 dev_dbg(&hdev->dev, "port-%d disable U1/U2 _DSM: %d\n", i + 1, ret); 577 578 if (ret >= 0) { 579 rhub->ports[i]->lpm_incapable = ret; 580 continue; 581 } 582 } 583 } 584 585 #else 586 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { } 587 static void xhci_find_lpm_incapable_ports(struct usb_hcd *hcd, struct usb_device *hdev) { } 588 #endif /* CONFIG_ACPI */ 589 590 /* called during probe() after chip reset completes */ 591 static int xhci_pci_setup(struct usb_hcd *hcd) 592 { 593 struct xhci_hcd *xhci; 594 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 595 int retval; 596 597 xhci = hcd_to_xhci(hcd); 598 if (!xhci->sbrn) 599 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn); 600 601 /* imod_interval is the interrupt moderation value in nanoseconds. */ 602 xhci->imod_interval = 40000; 603 604 retval = xhci_gen_setup(hcd, xhci_pci_quirks); 605 if (retval) 606 return retval; 607 608 if (!usb_hcd_is_primary_hcd(hcd)) 609 return 0; 610 611 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 612 xhci_pme_acpi_rtd3_enable(pdev); 613 614 xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn); 615 616 /* Find any debug ports */ 617 return xhci_pci_reinit(xhci, pdev); 618 } 619 620 static int xhci_pci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev, 621 struct usb_tt *tt, gfp_t mem_flags) 622 { 623 /* Check if acpi claims some USB3 roothub ports are lpm incapable */ 624 if (!hdev->parent) 625 xhci_find_lpm_incapable_ports(hcd, hdev); 626 627 return xhci_update_hub_device(hcd, hdev, tt, mem_flags); 628 } 629 630 /* 631 * We need to register our own PCI probe function (instead of the USB core's 632 * function) in order to create a second roothub under xHCI. 633 */ 634 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) 635 { 636 int retval; 637 struct xhci_hcd *xhci; 638 struct usb_hcd *hcd; 639 struct xhci_driver_data *driver_data; 640 struct reset_control *reset; 641 642 driver_data = (struct xhci_driver_data *)id->driver_data; 643 if (driver_data && driver_data->quirks & XHCI_RENESAS_FW_QUIRK) { 644 retval = renesas_xhci_check_request_fw(dev, id); 645 if (retval) 646 return retval; 647 } 648 649 reset = devm_reset_control_get_optional_exclusive(&dev->dev, NULL); 650 if (IS_ERR(reset)) 651 return PTR_ERR(reset); 652 reset_control_reset(reset); 653 654 /* Prevent runtime suspending between USB-2 and USB-3 initialization */ 655 pm_runtime_get_noresume(&dev->dev); 656 657 /* Register the USB 2.0 roothub. 658 * FIXME: USB core must know to register the USB 2.0 roothub first. 659 * This is sort of silly, because we could just set the HCD driver flags 660 * to say USB 2.0, but I'm not sure what the implications would be in 661 * the other parts of the HCD code. 662 */ 663 retval = usb_hcd_pci_probe(dev, &xhci_pci_hc_driver); 664 665 if (retval) 666 goto put_runtime_pm; 667 668 /* USB 2.0 roothub is stored in the PCI device now. */ 669 hcd = dev_get_drvdata(&dev->dev); 670 xhci = hcd_to_xhci(hcd); 671 xhci->reset = reset; 672 xhci->shared_hcd = usb_create_shared_hcd(&xhci_pci_hc_driver, &dev->dev, 673 pci_name(dev), hcd); 674 if (!xhci->shared_hcd) { 675 retval = -ENOMEM; 676 goto dealloc_usb2_hcd; 677 } 678 679 retval = xhci_ext_cap_init(xhci); 680 if (retval) 681 goto put_usb3_hcd; 682 683 retval = usb_add_hcd(xhci->shared_hcd, dev->irq, 684 IRQF_SHARED); 685 if (retval) 686 goto put_usb3_hcd; 687 /* Roothub already marked as USB 3.0 speed */ 688 689 if (!(xhci->quirks & XHCI_BROKEN_STREAMS) && 690 HCC_MAX_PSA(xhci->hcc_params) >= 4) 691 xhci->shared_hcd->can_do_streams = 1; 692 693 /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */ 694 pm_runtime_put_noidle(&dev->dev); 695 696 if (pci_choose_state(dev, PMSG_SUSPEND) == PCI_D0) 697 pm_runtime_forbid(&dev->dev); 698 else if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW) 699 pm_runtime_allow(&dev->dev); 700 701 dma_set_max_seg_size(&dev->dev, UINT_MAX); 702 703 return 0; 704 705 put_usb3_hcd: 706 usb_put_hcd(xhci->shared_hcd); 707 dealloc_usb2_hcd: 708 usb_hcd_pci_remove(dev); 709 put_runtime_pm: 710 pm_runtime_put_noidle(&dev->dev); 711 return retval; 712 } 713 714 static void xhci_pci_remove(struct pci_dev *dev) 715 { 716 struct xhci_hcd *xhci; 717 718 xhci = hcd_to_xhci(pci_get_drvdata(dev)); 719 720 xhci->xhc_state |= XHCI_STATE_REMOVING; 721 722 if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW) 723 pm_runtime_forbid(&dev->dev); 724 725 if (xhci->shared_hcd) { 726 usb_remove_hcd(xhci->shared_hcd); 727 usb_put_hcd(xhci->shared_hcd); 728 xhci->shared_hcd = NULL; 729 } 730 731 /* Workaround for spurious wakeups at shutdown with HSW */ 732 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP) 733 pci_set_power_state(dev, PCI_D3hot); 734 735 usb_hcd_pci_remove(dev); 736 } 737 738 /* 739 * In some Intel xHCI controllers, in order to get D3 working, 740 * through a vendor specific SSIC CONFIG register at offset 0x883c, 741 * SSIC PORT need to be marked as "unused" before putting xHCI 742 * into D3. After D3 exit, the SSIC port need to be marked as "used". 743 * Without this change, xHCI might not enter D3 state. 744 */ 745 static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend) 746 { 747 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 748 u32 val; 749 void __iomem *reg; 750 int i; 751 752 for (i = 0; i < SSIC_PORT_NUM; i++) { 753 reg = (void __iomem *) xhci->cap_regs + 754 SSIC_PORT_CFG2 + 755 i * SSIC_PORT_CFG2_OFFSET; 756 757 /* Notify SSIC that SSIC profile programming is not done. */ 758 val = readl(reg) & ~PROG_DONE; 759 writel(val, reg); 760 761 /* Mark SSIC port as unused(suspend) or used(resume) */ 762 val = readl(reg); 763 if (suspend) 764 val |= SSIC_PORT_UNUSED; 765 else 766 val &= ~SSIC_PORT_UNUSED; 767 writel(val, reg); 768 769 /* Notify SSIC that SSIC profile programming is done */ 770 val = readl(reg) | PROG_DONE; 771 writel(val, reg); 772 readl(reg); 773 } 774 } 775 776 /* 777 * Make sure PME works on some Intel xHCI controllers by writing 1 to clear 778 * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4 779 */ 780 static void xhci_pme_quirk(struct usb_hcd *hcd) 781 { 782 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 783 void __iomem *reg; 784 u32 val; 785 786 reg = (void __iomem *) xhci->cap_regs + 0x80a4; 787 val = readl(reg); 788 writel(val | BIT(28), reg); 789 readl(reg); 790 } 791 792 static void xhci_sparse_control_quirk(struct usb_hcd *hcd) 793 { 794 u32 reg; 795 796 reg = readl(hcd->regs + SPARSE_CNTL_ENABLE); 797 reg &= ~BIT(SPARSE_DISABLE_BIT); 798 writel(reg, hcd->regs + SPARSE_CNTL_ENABLE); 799 } 800 801 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup) 802 { 803 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 804 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 805 int ret; 806 807 /* 808 * Systems with the TI redriver that loses port status change events 809 * need to have the registers polled during D3, so avoid D3cold. 810 */ 811 if (xhci->quirks & XHCI_COMP_MODE_QUIRK) 812 pci_d3cold_disable(pdev); 813 814 #ifdef CONFIG_SUSPEND 815 /* d3cold is broken, but only when s2idle is used */ 816 if (pm_suspend_target_state == PM_SUSPEND_TO_IDLE && 817 xhci->quirks & (XHCI_BROKEN_D3COLD_S2I)) 818 pci_d3cold_disable(pdev); 819 #endif 820 821 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 822 xhci_pme_quirk(hcd); 823 824 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED) 825 xhci_ssic_port_unused_quirk(hcd, true); 826 827 if (xhci->quirks & XHCI_DISABLE_SPARSE) 828 xhci_sparse_control_quirk(hcd); 829 830 ret = xhci_suspend(xhci, do_wakeup); 831 832 /* synchronize irq when using MSI-X */ 833 xhci_msix_sync_irqs(xhci); 834 835 if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED)) 836 xhci_ssic_port_unused_quirk(hcd, false); 837 838 return ret; 839 } 840 841 static int xhci_pci_resume(struct usb_hcd *hcd, pm_message_t msg) 842 { 843 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 844 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 845 int retval = 0; 846 847 reset_control_reset(xhci->reset); 848 849 /* The BIOS on systems with the Intel Panther Point chipset may or may 850 * not support xHCI natively. That means that during system resume, it 851 * may switch the ports back to EHCI so that users can use their 852 * keyboard to select a kernel from GRUB after resume from hibernate. 853 * 854 * The BIOS is supposed to remember whether the OS had xHCI ports 855 * enabled before resume, and switch the ports back to xHCI when the 856 * BIOS/OS semaphore is written, but we all know we can't trust BIOS 857 * writers. 858 * 859 * Unconditionally switch the ports back to xHCI after a system resume. 860 * It should not matter whether the EHCI or xHCI controller is 861 * resumed first. It's enough to do the switchover in xHCI because 862 * USB core won't notice anything as the hub driver doesn't start 863 * running again until after all the devices (including both EHCI and 864 * xHCI host controllers) have been resumed. 865 */ 866 867 if (pdev->vendor == PCI_VENDOR_ID_INTEL) 868 usb_enable_intel_xhci_ports(pdev); 869 870 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED) 871 xhci_ssic_port_unused_quirk(hcd, false); 872 873 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 874 xhci_pme_quirk(hcd); 875 876 retval = xhci_resume(xhci, msg); 877 return retval; 878 } 879 880 static int xhci_pci_poweroff_late(struct usb_hcd *hcd, bool do_wakeup) 881 { 882 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 883 struct xhci_port *port; 884 struct usb_device *udev; 885 unsigned int slot_id; 886 u32 portsc; 887 int i; 888 889 /* 890 * Systems with XHCI_RESET_TO_DEFAULT quirk have boot firmware that 891 * cause significant boot delay if usb ports are in suspended U3 state 892 * during boot. Some USB devices survive in U3 state over S4 hibernate 893 * 894 * Disable ports that are in U3 if remote wake is not enabled for either 895 * host controller or connected device 896 */ 897 898 if (!(xhci->quirks & XHCI_RESET_TO_DEFAULT)) 899 return 0; 900 901 for (i = 0; i < HCS_MAX_PORTS(xhci->hcs_params1); i++) { 902 port = &xhci->hw_ports[i]; 903 portsc = readl(port->addr); 904 905 if ((portsc & PORT_PLS_MASK) != XDEV_U3) 906 continue; 907 908 slot_id = xhci_find_slot_id_by_port(port->rhub->hcd, xhci, 909 port->hcd_portnum + 1); 910 if (!slot_id || !xhci->devs[slot_id]) { 911 xhci_err(xhci, "No dev for slot_id %d for port %d-%d in U3\n", 912 slot_id, port->rhub->hcd->self.busnum, port->hcd_portnum + 1); 913 continue; 914 } 915 916 udev = xhci->devs[slot_id]->udev; 917 918 /* if wakeup is enabled then don't disable the port */ 919 if (udev->do_remote_wakeup && do_wakeup) 920 continue; 921 922 xhci_dbg(xhci, "port %d-%d in U3 without wakeup, disable it\n", 923 port->rhub->hcd->self.busnum, port->hcd_portnum + 1); 924 portsc = xhci_port_state_to_neutral(portsc); 925 writel(portsc | PORT_PE, port->addr); 926 } 927 928 return 0; 929 } 930 931 static void xhci_pci_shutdown(struct usb_hcd *hcd) 932 { 933 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 934 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 935 936 xhci_shutdown(hcd); 937 xhci_cleanup_msix(xhci); 938 939 /* Yet another workaround for spurious wakeups at shutdown with HSW */ 940 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP) 941 pci_set_power_state(pdev, PCI_D3hot); 942 } 943 944 /*-------------------------------------------------------------------------*/ 945 946 static const struct xhci_driver_data reneses_data = { 947 .quirks = XHCI_RENESAS_FW_QUIRK, 948 .firmware = "renesas_usb_fw.mem", 949 }; 950 951 /* PCI driver selection metadata; PCI hotplugging uses this */ 952 static const struct pci_device_id pci_ids[] = { 953 { PCI_DEVICE(0x1912, 0x0014), 954 .driver_data = (unsigned long)&reneses_data, 955 }, 956 { PCI_DEVICE(0x1912, 0x0015), 957 .driver_data = (unsigned long)&reneses_data, 958 }, 959 /* handle any USB 3.0 xHCI controller */ 960 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0), 961 }, 962 { /* end: all zeroes */ } 963 }; 964 MODULE_DEVICE_TABLE(pci, pci_ids); 965 966 /* 967 * Without CONFIG_USB_XHCI_PCI_RENESAS renesas_xhci_check_request_fw() won't 968 * load firmware, so don't encumber the xhci-pci driver with it. 969 */ 970 #if IS_ENABLED(CONFIG_USB_XHCI_PCI_RENESAS) 971 MODULE_FIRMWARE("renesas_usb_fw.mem"); 972 #endif 973 974 /* pci driver glue; this is a "new style" PCI driver module */ 975 static struct pci_driver xhci_pci_driver = { 976 .name = hcd_name, 977 .id_table = pci_ids, 978 979 .probe = xhci_pci_probe, 980 .remove = xhci_pci_remove, 981 /* suspend and resume implemented later */ 982 983 .shutdown = usb_hcd_pci_shutdown, 984 .driver = { 985 .pm = pm_ptr(&usb_hcd_pci_pm_ops), 986 }, 987 }; 988 989 static int __init xhci_pci_init(void) 990 { 991 xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides); 992 xhci_pci_hc_driver.pci_suspend = pm_ptr(xhci_pci_suspend); 993 xhci_pci_hc_driver.pci_resume = pm_ptr(xhci_pci_resume); 994 xhci_pci_hc_driver.pci_poweroff_late = pm_ptr(xhci_pci_poweroff_late); 995 xhci_pci_hc_driver.shutdown = pm_ptr(xhci_pci_shutdown); 996 xhci_pci_hc_driver.stop = xhci_pci_stop; 997 return pci_register_driver(&xhci_pci_driver); 998 } 999 module_init(xhci_pci_init); 1000 1001 static void __exit xhci_pci_exit(void) 1002 { 1003 pci_unregister_driver(&xhci_pci_driver); 1004 } 1005 module_exit(xhci_pci_exit); 1006 1007 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver"); 1008 MODULE_LICENSE("GPL"); 1009