1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * NVIDIA Tegra xHCI host controller driver 4 * 5 * Copyright (C) 2014 NVIDIA Corporation 6 * Copyright (C) 2014 Google, Inc. 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/firmware.h> 13 #include <linux/interrupt.h> 14 #include <linux/kernel.h> 15 #include <linux/module.h> 16 #include <linux/of_device.h> 17 #include <linux/phy/phy.h> 18 #include <linux/phy/tegra/xusb.h> 19 #include <linux/platform_device.h> 20 #include <linux/pm.h> 21 #include <linux/pm_domain.h> 22 #include <linux/pm_runtime.h> 23 #include <linux/regulator/consumer.h> 24 #include <linux/reset.h> 25 #include <linux/slab.h> 26 #include <soc/tegra/pmc.h> 27 28 #include "xhci.h" 29 30 #define TEGRA_XHCI_SS_HIGH_SPEED 120000000 31 #define TEGRA_XHCI_SS_LOW_SPEED 12000000 32 33 /* FPCI CFG registers */ 34 #define XUSB_CFG_1 0x004 35 #define XUSB_IO_SPACE_EN BIT(0) 36 #define XUSB_MEM_SPACE_EN BIT(1) 37 #define XUSB_BUS_MASTER_EN BIT(2) 38 #define XUSB_CFG_4 0x010 39 #define XUSB_BASE_ADDR_SHIFT 15 40 #define XUSB_BASE_ADDR_MASK 0x1ffff 41 #define XUSB_CFG_ARU_C11_CSBRANGE 0x41c 42 #define XUSB_CFG_CSB_BASE_ADDR 0x800 43 44 /* FPCI mailbox registers */ 45 #define XUSB_CFG_ARU_MBOX_CMD 0x0e4 46 #define MBOX_DEST_FALC BIT(27) 47 #define MBOX_DEST_PME BIT(28) 48 #define MBOX_DEST_SMI BIT(29) 49 #define MBOX_DEST_XHCI BIT(30) 50 #define MBOX_INT_EN BIT(31) 51 #define XUSB_CFG_ARU_MBOX_DATA_IN 0x0e8 52 #define CMD_DATA_SHIFT 0 53 #define CMD_DATA_MASK 0xffffff 54 #define CMD_TYPE_SHIFT 24 55 #define CMD_TYPE_MASK 0xff 56 #define XUSB_CFG_ARU_MBOX_DATA_OUT 0x0ec 57 #define XUSB_CFG_ARU_MBOX_OWNER 0x0f0 58 #define MBOX_OWNER_NONE 0 59 #define MBOX_OWNER_FW 1 60 #define MBOX_OWNER_SW 2 61 #define XUSB_CFG_ARU_SMI_INTR 0x428 62 #define MBOX_SMI_INTR_FW_HANG BIT(1) 63 #define MBOX_SMI_INTR_EN BIT(3) 64 65 /* IPFS registers */ 66 #define IPFS_XUSB_HOST_CONFIGURATION_0 0x180 67 #define IPFS_EN_FPCI BIT(0) 68 #define IPFS_XUSB_HOST_INTR_MASK_0 0x188 69 #define IPFS_IP_INT_MASK BIT(16) 70 #define IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0 0x1bc 71 72 #define CSB_PAGE_SELECT_MASK 0x7fffff 73 #define CSB_PAGE_SELECT_SHIFT 9 74 #define CSB_PAGE_OFFSET_MASK 0x1ff 75 #define CSB_PAGE_SELECT(addr) ((addr) >> (CSB_PAGE_SELECT_SHIFT) & \ 76 CSB_PAGE_SELECT_MASK) 77 #define CSB_PAGE_OFFSET(addr) ((addr) & CSB_PAGE_OFFSET_MASK) 78 79 /* Falcon CSB registers */ 80 #define XUSB_FALC_CPUCTL 0x100 81 #define CPUCTL_STARTCPU BIT(1) 82 #define CPUCTL_STATE_HALTED BIT(4) 83 #define CPUCTL_STATE_STOPPED BIT(5) 84 #define XUSB_FALC_BOOTVEC 0x104 85 #define XUSB_FALC_DMACTL 0x10c 86 #define XUSB_FALC_IMFILLRNG1 0x154 87 #define IMFILLRNG1_TAG_MASK 0xffff 88 #define IMFILLRNG1_TAG_LO_SHIFT 0 89 #define IMFILLRNG1_TAG_HI_SHIFT 16 90 #define XUSB_FALC_IMFILLCTL 0x158 91 92 /* MP CSB registers */ 93 #define XUSB_CSB_MP_ILOAD_ATTR 0x101a00 94 #define XUSB_CSB_MP_ILOAD_BASE_LO 0x101a04 95 #define XUSB_CSB_MP_ILOAD_BASE_HI 0x101a08 96 #define XUSB_CSB_MP_L2IMEMOP_SIZE 0x101a10 97 #define L2IMEMOP_SIZE_SRC_OFFSET_SHIFT 8 98 #define L2IMEMOP_SIZE_SRC_OFFSET_MASK 0x3ff 99 #define L2IMEMOP_SIZE_SRC_COUNT_SHIFT 24 100 #define L2IMEMOP_SIZE_SRC_COUNT_MASK 0xff 101 #define XUSB_CSB_MP_L2IMEMOP_TRIG 0x101a14 102 #define L2IMEMOP_ACTION_SHIFT 24 103 #define L2IMEMOP_INVALIDATE_ALL (0x40 << L2IMEMOP_ACTION_SHIFT) 104 #define L2IMEMOP_LOAD_LOCKED_RESULT (0x11 << L2IMEMOP_ACTION_SHIFT) 105 #define XUSB_CSB_MP_APMAP 0x10181c 106 #define APMAP_BOOTPATH BIT(31) 107 108 #define IMEM_BLOCK_SIZE 256 109 110 struct tegra_xusb_fw_header { 111 __le32 boot_loadaddr_in_imem; 112 __le32 boot_codedfi_offset; 113 __le32 boot_codetag; 114 __le32 boot_codesize; 115 __le32 phys_memaddr; 116 __le16 reqphys_memsize; 117 __le16 alloc_phys_memsize; 118 __le32 rodata_img_offset; 119 __le32 rodata_section_start; 120 __le32 rodata_section_end; 121 __le32 main_fnaddr; 122 __le32 fwimg_cksum; 123 __le32 fwimg_created_time; 124 __le32 imem_resident_start; 125 __le32 imem_resident_end; 126 __le32 idirect_start; 127 __le32 idirect_end; 128 __le32 l2_imem_start; 129 __le32 l2_imem_end; 130 __le32 version_id; 131 u8 init_ddirect; 132 u8 reserved[3]; 133 __le32 phys_addr_log_buffer; 134 __le32 total_log_entries; 135 __le32 dequeue_ptr; 136 __le32 dummy_var[2]; 137 __le32 fwimg_len; 138 u8 magic[8]; 139 __le32 ss_low_power_entry_timeout; 140 u8 num_hsic_port; 141 u8 padding[139]; /* Pad to 256 bytes */ 142 }; 143 144 struct tegra_xusb_phy_type { 145 const char *name; 146 unsigned int num; 147 }; 148 149 struct tegra_xusb_soc { 150 const char *firmware; 151 const char * const *supply_names; 152 unsigned int num_supplies; 153 const struct tegra_xusb_phy_type *phy_types; 154 unsigned int num_types; 155 156 struct { 157 struct { 158 unsigned int offset; 159 unsigned int count; 160 } usb2, ulpi, hsic, usb3; 161 } ports; 162 163 bool scale_ss_clock; 164 bool has_ipfs; 165 }; 166 167 struct tegra_xusb { 168 struct device *dev; 169 void __iomem *regs; 170 struct usb_hcd *hcd; 171 172 struct mutex lock; 173 174 int xhci_irq; 175 int mbox_irq; 176 177 void __iomem *ipfs_base; 178 void __iomem *fpci_base; 179 180 const struct tegra_xusb_soc *soc; 181 182 struct regulator_bulk_data *supplies; 183 184 struct tegra_xusb_padctl *padctl; 185 186 struct clk *host_clk; 187 struct clk *falcon_clk; 188 struct clk *ss_clk; 189 struct clk *ss_src_clk; 190 struct clk *hs_src_clk; 191 struct clk *fs_src_clk; 192 struct clk *pll_u_480m; 193 struct clk *clk_m; 194 struct clk *pll_e; 195 196 struct reset_control *host_rst; 197 struct reset_control *ss_rst; 198 199 struct device *genpd_dev_host; 200 struct device *genpd_dev_ss; 201 struct device_link *genpd_dl_host; 202 struct device_link *genpd_dl_ss; 203 204 struct phy **phys; 205 unsigned int num_phys; 206 207 /* Firmware loading related */ 208 struct { 209 size_t size; 210 void *virt; 211 dma_addr_t phys; 212 } fw; 213 }; 214 215 static struct hc_driver __read_mostly tegra_xhci_hc_driver; 216 217 static inline u32 fpci_readl(struct tegra_xusb *tegra, unsigned int offset) 218 { 219 return readl(tegra->fpci_base + offset); 220 } 221 222 static inline void fpci_writel(struct tegra_xusb *tegra, u32 value, 223 unsigned int offset) 224 { 225 writel(value, tegra->fpci_base + offset); 226 } 227 228 static inline u32 ipfs_readl(struct tegra_xusb *tegra, unsigned int offset) 229 { 230 return readl(tegra->ipfs_base + offset); 231 } 232 233 static inline void ipfs_writel(struct tegra_xusb *tegra, u32 value, 234 unsigned int offset) 235 { 236 writel(value, tegra->ipfs_base + offset); 237 } 238 239 static u32 csb_readl(struct tegra_xusb *tegra, unsigned int offset) 240 { 241 u32 page = CSB_PAGE_SELECT(offset); 242 u32 ofs = CSB_PAGE_OFFSET(offset); 243 244 fpci_writel(tegra, page, XUSB_CFG_ARU_C11_CSBRANGE); 245 246 return fpci_readl(tegra, XUSB_CFG_CSB_BASE_ADDR + ofs); 247 } 248 249 static void csb_writel(struct tegra_xusb *tegra, u32 value, 250 unsigned int offset) 251 { 252 u32 page = CSB_PAGE_SELECT(offset); 253 u32 ofs = CSB_PAGE_OFFSET(offset); 254 255 fpci_writel(tegra, page, XUSB_CFG_ARU_C11_CSBRANGE); 256 fpci_writel(tegra, value, XUSB_CFG_CSB_BASE_ADDR + ofs); 257 } 258 259 static int tegra_xusb_set_ss_clk(struct tegra_xusb *tegra, 260 unsigned long rate) 261 { 262 unsigned long new_parent_rate, old_parent_rate; 263 struct clk *clk = tegra->ss_src_clk; 264 unsigned int div; 265 int err; 266 267 if (clk_get_rate(clk) == rate) 268 return 0; 269 270 switch (rate) { 271 case TEGRA_XHCI_SS_HIGH_SPEED: 272 /* 273 * Reparent to PLLU_480M. Set divider first to avoid 274 * overclocking. 275 */ 276 old_parent_rate = clk_get_rate(clk_get_parent(clk)); 277 new_parent_rate = clk_get_rate(tegra->pll_u_480m); 278 div = new_parent_rate / rate; 279 280 err = clk_set_rate(clk, old_parent_rate / div); 281 if (err) 282 return err; 283 284 err = clk_set_parent(clk, tegra->pll_u_480m); 285 if (err) 286 return err; 287 288 /* 289 * The rate should already be correct, but set it again just 290 * to be sure. 291 */ 292 err = clk_set_rate(clk, rate); 293 if (err) 294 return err; 295 296 break; 297 298 case TEGRA_XHCI_SS_LOW_SPEED: 299 /* Reparent to CLK_M */ 300 err = clk_set_parent(clk, tegra->clk_m); 301 if (err) 302 return err; 303 304 err = clk_set_rate(clk, rate); 305 if (err) 306 return err; 307 308 break; 309 310 default: 311 dev_err(tegra->dev, "Invalid SS rate: %lu Hz\n", rate); 312 return -EINVAL; 313 } 314 315 if (clk_get_rate(clk) != rate) { 316 dev_err(tegra->dev, "SS clock doesn't match requested rate\n"); 317 return -EINVAL; 318 } 319 320 return 0; 321 } 322 323 static unsigned long extract_field(u32 value, unsigned int start, 324 unsigned int count) 325 { 326 return (value >> start) & ((1 << count) - 1); 327 } 328 329 /* Command requests from the firmware */ 330 enum tegra_xusb_mbox_cmd { 331 MBOX_CMD_MSG_ENABLED = 1, 332 MBOX_CMD_INC_FALC_CLOCK, 333 MBOX_CMD_DEC_FALC_CLOCK, 334 MBOX_CMD_INC_SSPI_CLOCK, 335 MBOX_CMD_DEC_SSPI_CLOCK, 336 MBOX_CMD_SET_BW, /* no ACK/NAK required */ 337 MBOX_CMD_SET_SS_PWR_GATING, 338 MBOX_CMD_SET_SS_PWR_UNGATING, 339 MBOX_CMD_SAVE_DFE_CTLE_CTX, 340 MBOX_CMD_AIRPLANE_MODE_ENABLED, /* unused */ 341 MBOX_CMD_AIRPLANE_MODE_DISABLED, /* unused */ 342 MBOX_CMD_START_HSIC_IDLE, 343 MBOX_CMD_STOP_HSIC_IDLE, 344 MBOX_CMD_DBC_WAKE_STACK, /* unused */ 345 MBOX_CMD_HSIC_PRETEND_CONNECT, 346 MBOX_CMD_RESET_SSPI, 347 MBOX_CMD_DISABLE_SS_LFPS_DETECTION, 348 MBOX_CMD_ENABLE_SS_LFPS_DETECTION, 349 350 MBOX_CMD_MAX, 351 352 /* Response message to above commands */ 353 MBOX_CMD_ACK = 128, 354 MBOX_CMD_NAK 355 }; 356 357 struct tegra_xusb_mbox_msg { 358 u32 cmd; 359 u32 data; 360 }; 361 362 static inline u32 tegra_xusb_mbox_pack(const struct tegra_xusb_mbox_msg *msg) 363 { 364 return (msg->cmd & CMD_TYPE_MASK) << CMD_TYPE_SHIFT | 365 (msg->data & CMD_DATA_MASK) << CMD_DATA_SHIFT; 366 } 367 static inline void tegra_xusb_mbox_unpack(struct tegra_xusb_mbox_msg *msg, 368 u32 value) 369 { 370 msg->cmd = (value >> CMD_TYPE_SHIFT) & CMD_TYPE_MASK; 371 msg->data = (value >> CMD_DATA_SHIFT) & CMD_DATA_MASK; 372 } 373 374 static bool tegra_xusb_mbox_cmd_requires_ack(enum tegra_xusb_mbox_cmd cmd) 375 { 376 switch (cmd) { 377 case MBOX_CMD_SET_BW: 378 case MBOX_CMD_ACK: 379 case MBOX_CMD_NAK: 380 return false; 381 382 default: 383 return true; 384 } 385 } 386 387 static int tegra_xusb_mbox_send(struct tegra_xusb *tegra, 388 const struct tegra_xusb_mbox_msg *msg) 389 { 390 bool wait_for_idle = false; 391 u32 value; 392 393 /* 394 * Acquire the mailbox. The firmware still owns the mailbox for 395 * ACK/NAK messages. 396 */ 397 if (!(msg->cmd == MBOX_CMD_ACK || msg->cmd == MBOX_CMD_NAK)) { 398 value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_OWNER); 399 if (value != MBOX_OWNER_NONE) { 400 dev_err(tegra->dev, "mailbox is busy\n"); 401 return -EBUSY; 402 } 403 404 fpci_writel(tegra, MBOX_OWNER_SW, XUSB_CFG_ARU_MBOX_OWNER); 405 406 value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_OWNER); 407 if (value != MBOX_OWNER_SW) { 408 dev_err(tegra->dev, "failed to acquire mailbox\n"); 409 return -EBUSY; 410 } 411 412 wait_for_idle = true; 413 } 414 415 value = tegra_xusb_mbox_pack(msg); 416 fpci_writel(tegra, value, XUSB_CFG_ARU_MBOX_DATA_IN); 417 418 value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_CMD); 419 value |= MBOX_INT_EN | MBOX_DEST_FALC; 420 fpci_writel(tegra, value, XUSB_CFG_ARU_MBOX_CMD); 421 422 if (wait_for_idle) { 423 unsigned long timeout = jiffies + msecs_to_jiffies(250); 424 425 while (time_before(jiffies, timeout)) { 426 value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_OWNER); 427 if (value == MBOX_OWNER_NONE) 428 break; 429 430 usleep_range(10, 20); 431 } 432 433 if (time_after(jiffies, timeout)) 434 value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_OWNER); 435 436 if (value != MBOX_OWNER_NONE) 437 return -ETIMEDOUT; 438 } 439 440 return 0; 441 } 442 443 static irqreturn_t tegra_xusb_mbox_irq(int irq, void *data) 444 { 445 struct tegra_xusb *tegra = data; 446 u32 value; 447 448 /* clear mailbox interrupts */ 449 value = fpci_readl(tegra, XUSB_CFG_ARU_SMI_INTR); 450 fpci_writel(tegra, value, XUSB_CFG_ARU_SMI_INTR); 451 452 if (value & MBOX_SMI_INTR_FW_HANG) 453 dev_err(tegra->dev, "controller firmware hang\n"); 454 455 return IRQ_WAKE_THREAD; 456 } 457 458 static void tegra_xusb_mbox_handle(struct tegra_xusb *tegra, 459 const struct tegra_xusb_mbox_msg *msg) 460 { 461 struct tegra_xusb_padctl *padctl = tegra->padctl; 462 const struct tegra_xusb_soc *soc = tegra->soc; 463 struct device *dev = tegra->dev; 464 struct tegra_xusb_mbox_msg rsp; 465 unsigned long mask; 466 unsigned int port; 467 bool idle, enable; 468 int err = 0; 469 470 memset(&rsp, 0, sizeof(rsp)); 471 472 switch (msg->cmd) { 473 case MBOX_CMD_INC_FALC_CLOCK: 474 case MBOX_CMD_DEC_FALC_CLOCK: 475 rsp.data = clk_get_rate(tegra->falcon_clk) / 1000; 476 if (rsp.data != msg->data) 477 rsp.cmd = MBOX_CMD_NAK; 478 else 479 rsp.cmd = MBOX_CMD_ACK; 480 481 break; 482 483 case MBOX_CMD_INC_SSPI_CLOCK: 484 case MBOX_CMD_DEC_SSPI_CLOCK: 485 if (tegra->soc->scale_ss_clock) { 486 err = tegra_xusb_set_ss_clk(tegra, msg->data * 1000); 487 if (err < 0) 488 rsp.cmd = MBOX_CMD_NAK; 489 else 490 rsp.cmd = MBOX_CMD_ACK; 491 492 rsp.data = clk_get_rate(tegra->ss_src_clk) / 1000; 493 } else { 494 rsp.cmd = MBOX_CMD_ACK; 495 rsp.data = msg->data; 496 } 497 498 break; 499 500 case MBOX_CMD_SET_BW: 501 /* 502 * TODO: Request bandwidth once EMC scaling is supported. 503 * Ignore for now since ACK/NAK is not required for SET_BW 504 * messages. 505 */ 506 break; 507 508 case MBOX_CMD_SAVE_DFE_CTLE_CTX: 509 err = tegra_xusb_padctl_usb3_save_context(padctl, msg->data); 510 if (err < 0) { 511 dev_err(dev, "failed to save context for USB3#%u: %d\n", 512 msg->data, err); 513 rsp.cmd = MBOX_CMD_NAK; 514 } else { 515 rsp.cmd = MBOX_CMD_ACK; 516 } 517 518 rsp.data = msg->data; 519 break; 520 521 case MBOX_CMD_START_HSIC_IDLE: 522 case MBOX_CMD_STOP_HSIC_IDLE: 523 if (msg->cmd == MBOX_CMD_STOP_HSIC_IDLE) 524 idle = false; 525 else 526 idle = true; 527 528 mask = extract_field(msg->data, 1 + soc->ports.hsic.offset, 529 soc->ports.hsic.count); 530 531 for_each_set_bit(port, &mask, 32) { 532 err = tegra_xusb_padctl_hsic_set_idle(padctl, port, 533 idle); 534 if (err < 0) 535 break; 536 } 537 538 if (err < 0) { 539 dev_err(dev, "failed to set HSIC#%u %s: %d\n", port, 540 idle ? "idle" : "busy", err); 541 rsp.cmd = MBOX_CMD_NAK; 542 } else { 543 rsp.cmd = MBOX_CMD_ACK; 544 } 545 546 rsp.data = msg->data; 547 break; 548 549 case MBOX_CMD_DISABLE_SS_LFPS_DETECTION: 550 case MBOX_CMD_ENABLE_SS_LFPS_DETECTION: 551 if (msg->cmd == MBOX_CMD_DISABLE_SS_LFPS_DETECTION) 552 enable = false; 553 else 554 enable = true; 555 556 mask = extract_field(msg->data, 1 + soc->ports.usb3.offset, 557 soc->ports.usb3.count); 558 559 for_each_set_bit(port, &mask, soc->ports.usb3.count) { 560 err = tegra_xusb_padctl_usb3_set_lfps_detect(padctl, 561 port, 562 enable); 563 if (err < 0) 564 break; 565 } 566 567 if (err < 0) { 568 dev_err(dev, 569 "failed to %s LFPS detection on USB3#%u: %d\n", 570 enable ? "enable" : "disable", port, err); 571 rsp.cmd = MBOX_CMD_NAK; 572 } else { 573 rsp.cmd = MBOX_CMD_ACK; 574 } 575 576 rsp.data = msg->data; 577 break; 578 579 default: 580 dev_warn(dev, "unknown message: %#x\n", msg->cmd); 581 break; 582 } 583 584 if (rsp.cmd) { 585 const char *cmd = (rsp.cmd == MBOX_CMD_ACK) ? "ACK" : "NAK"; 586 587 err = tegra_xusb_mbox_send(tegra, &rsp); 588 if (err < 0) 589 dev_err(dev, "failed to send %s: %d\n", cmd, err); 590 } 591 } 592 593 static irqreturn_t tegra_xusb_mbox_thread(int irq, void *data) 594 { 595 struct tegra_xusb *tegra = data; 596 struct tegra_xusb_mbox_msg msg; 597 u32 value; 598 599 mutex_lock(&tegra->lock); 600 601 value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_DATA_OUT); 602 tegra_xusb_mbox_unpack(&msg, value); 603 604 value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_CMD); 605 value &= ~MBOX_DEST_SMI; 606 fpci_writel(tegra, value, XUSB_CFG_ARU_MBOX_CMD); 607 608 /* clear mailbox owner if no ACK/NAK is required */ 609 if (!tegra_xusb_mbox_cmd_requires_ack(msg.cmd)) 610 fpci_writel(tegra, MBOX_OWNER_NONE, XUSB_CFG_ARU_MBOX_OWNER); 611 612 tegra_xusb_mbox_handle(tegra, &msg); 613 614 mutex_unlock(&tegra->lock); 615 return IRQ_HANDLED; 616 } 617 618 static void tegra_xusb_config(struct tegra_xusb *tegra, 619 struct resource *regs) 620 { 621 u32 value; 622 623 if (tegra->soc->has_ipfs) { 624 value = ipfs_readl(tegra, IPFS_XUSB_HOST_CONFIGURATION_0); 625 value |= IPFS_EN_FPCI; 626 ipfs_writel(tegra, value, IPFS_XUSB_HOST_CONFIGURATION_0); 627 628 usleep_range(10, 20); 629 } 630 631 /* Program BAR0 space */ 632 value = fpci_readl(tegra, XUSB_CFG_4); 633 value &= ~(XUSB_BASE_ADDR_MASK << XUSB_BASE_ADDR_SHIFT); 634 value |= regs->start & (XUSB_BASE_ADDR_MASK << XUSB_BASE_ADDR_SHIFT); 635 fpci_writel(tegra, value, XUSB_CFG_4); 636 637 usleep_range(100, 200); 638 639 /* Enable bus master */ 640 value = fpci_readl(tegra, XUSB_CFG_1); 641 value |= XUSB_IO_SPACE_EN | XUSB_MEM_SPACE_EN | XUSB_BUS_MASTER_EN; 642 fpci_writel(tegra, value, XUSB_CFG_1); 643 644 if (tegra->soc->has_ipfs) { 645 /* Enable interrupt assertion */ 646 value = ipfs_readl(tegra, IPFS_XUSB_HOST_INTR_MASK_0); 647 value |= IPFS_IP_INT_MASK; 648 ipfs_writel(tegra, value, IPFS_XUSB_HOST_INTR_MASK_0); 649 650 /* Set hysteresis */ 651 ipfs_writel(tegra, 0x80, IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0); 652 } 653 } 654 655 static int tegra_xusb_clk_enable(struct tegra_xusb *tegra) 656 { 657 int err; 658 659 err = clk_prepare_enable(tegra->pll_e); 660 if (err < 0) 661 return err; 662 663 err = clk_prepare_enable(tegra->host_clk); 664 if (err < 0) 665 goto disable_plle; 666 667 err = clk_prepare_enable(tegra->ss_clk); 668 if (err < 0) 669 goto disable_host; 670 671 err = clk_prepare_enable(tegra->falcon_clk); 672 if (err < 0) 673 goto disable_ss; 674 675 err = clk_prepare_enable(tegra->fs_src_clk); 676 if (err < 0) 677 goto disable_falc; 678 679 err = clk_prepare_enable(tegra->hs_src_clk); 680 if (err < 0) 681 goto disable_fs_src; 682 683 if (tegra->soc->scale_ss_clock) { 684 err = tegra_xusb_set_ss_clk(tegra, TEGRA_XHCI_SS_HIGH_SPEED); 685 if (err < 0) 686 goto disable_hs_src; 687 } 688 689 return 0; 690 691 disable_hs_src: 692 clk_disable_unprepare(tegra->hs_src_clk); 693 disable_fs_src: 694 clk_disable_unprepare(tegra->fs_src_clk); 695 disable_falc: 696 clk_disable_unprepare(tegra->falcon_clk); 697 disable_ss: 698 clk_disable_unprepare(tegra->ss_clk); 699 disable_host: 700 clk_disable_unprepare(tegra->host_clk); 701 disable_plle: 702 clk_disable_unprepare(tegra->pll_e); 703 return err; 704 } 705 706 static void tegra_xusb_clk_disable(struct tegra_xusb *tegra) 707 { 708 clk_disable_unprepare(tegra->pll_e); 709 clk_disable_unprepare(tegra->host_clk); 710 clk_disable_unprepare(tegra->ss_clk); 711 clk_disable_unprepare(tegra->falcon_clk); 712 clk_disable_unprepare(tegra->fs_src_clk); 713 clk_disable_unprepare(tegra->hs_src_clk); 714 } 715 716 static int tegra_xusb_phy_enable(struct tegra_xusb *tegra) 717 { 718 unsigned int i; 719 int err; 720 721 for (i = 0; i < tegra->num_phys; i++) { 722 err = phy_init(tegra->phys[i]); 723 if (err) 724 goto disable_phy; 725 726 err = phy_power_on(tegra->phys[i]); 727 if (err) { 728 phy_exit(tegra->phys[i]); 729 goto disable_phy; 730 } 731 } 732 733 return 0; 734 735 disable_phy: 736 while (i--) { 737 phy_power_off(tegra->phys[i]); 738 phy_exit(tegra->phys[i]); 739 } 740 741 return err; 742 } 743 744 static void tegra_xusb_phy_disable(struct tegra_xusb *tegra) 745 { 746 unsigned int i; 747 748 for (i = 0; i < tegra->num_phys; i++) { 749 phy_power_off(tegra->phys[i]); 750 phy_exit(tegra->phys[i]); 751 } 752 } 753 754 static int tegra_xusb_runtime_suspend(struct device *dev) 755 { 756 struct tegra_xusb *tegra = dev_get_drvdata(dev); 757 758 tegra_xusb_phy_disable(tegra); 759 regulator_bulk_disable(tegra->soc->num_supplies, tegra->supplies); 760 tegra_xusb_clk_disable(tegra); 761 762 return 0; 763 } 764 765 static int tegra_xusb_runtime_resume(struct device *dev) 766 { 767 struct tegra_xusb *tegra = dev_get_drvdata(dev); 768 int err; 769 770 err = tegra_xusb_clk_enable(tegra); 771 if (err) { 772 dev_err(dev, "failed to enable clocks: %d\n", err); 773 return err; 774 } 775 776 err = regulator_bulk_enable(tegra->soc->num_supplies, tegra->supplies); 777 if (err) { 778 dev_err(dev, "failed to enable regulators: %d\n", err); 779 goto disable_clk; 780 } 781 782 err = tegra_xusb_phy_enable(tegra); 783 if (err < 0) { 784 dev_err(dev, "failed to enable PHYs: %d\n", err); 785 goto disable_regulator; 786 } 787 788 return 0; 789 790 disable_regulator: 791 regulator_bulk_disable(tegra->soc->num_supplies, tegra->supplies); 792 disable_clk: 793 tegra_xusb_clk_disable(tegra); 794 return err; 795 } 796 797 static int tegra_xusb_load_firmware(struct tegra_xusb *tegra) 798 { 799 unsigned int code_tag_blocks, code_size_blocks, code_blocks; 800 struct tegra_xusb_fw_header *header; 801 struct device *dev = tegra->dev; 802 const struct firmware *fw; 803 unsigned long timeout; 804 time64_t timestamp; 805 struct tm time; 806 u64 address; 807 u32 value; 808 int err; 809 810 err = request_firmware(&fw, tegra->soc->firmware, tegra->dev); 811 if (err < 0) { 812 dev_err(tegra->dev, "failed to request firmware: %d\n", err); 813 return err; 814 } 815 816 /* Load Falcon controller with its firmware. */ 817 header = (struct tegra_xusb_fw_header *)fw->data; 818 tegra->fw.size = le32_to_cpu(header->fwimg_len); 819 820 tegra->fw.virt = dma_alloc_coherent(tegra->dev, tegra->fw.size, 821 &tegra->fw.phys, GFP_KERNEL); 822 if (!tegra->fw.virt) { 823 dev_err(tegra->dev, "failed to allocate memory for firmware\n"); 824 release_firmware(fw); 825 return -ENOMEM; 826 } 827 828 header = (struct tegra_xusb_fw_header *)tegra->fw.virt; 829 memcpy(tegra->fw.virt, fw->data, tegra->fw.size); 830 release_firmware(fw); 831 832 if (csb_readl(tegra, XUSB_CSB_MP_ILOAD_BASE_LO) != 0) { 833 dev_info(dev, "Firmware already loaded, Falcon state %#x\n", 834 csb_readl(tegra, XUSB_FALC_CPUCTL)); 835 return 0; 836 } 837 838 /* Program the size of DFI into ILOAD_ATTR. */ 839 csb_writel(tegra, tegra->fw.size, XUSB_CSB_MP_ILOAD_ATTR); 840 841 /* 842 * Boot code of the firmware reads the ILOAD_BASE registers 843 * to get to the start of the DFI in system memory. 844 */ 845 address = tegra->fw.phys + sizeof(*header); 846 csb_writel(tegra, address >> 32, XUSB_CSB_MP_ILOAD_BASE_HI); 847 csb_writel(tegra, address, XUSB_CSB_MP_ILOAD_BASE_LO); 848 849 /* Set BOOTPATH to 1 in APMAP. */ 850 csb_writel(tegra, APMAP_BOOTPATH, XUSB_CSB_MP_APMAP); 851 852 /* Invalidate L2IMEM. */ 853 csb_writel(tegra, L2IMEMOP_INVALIDATE_ALL, XUSB_CSB_MP_L2IMEMOP_TRIG); 854 855 /* 856 * Initiate fetch of bootcode from system memory into L2IMEM. 857 * Program bootcode location and size in system memory. 858 */ 859 code_tag_blocks = DIV_ROUND_UP(le32_to_cpu(header->boot_codetag), 860 IMEM_BLOCK_SIZE); 861 code_size_blocks = DIV_ROUND_UP(le32_to_cpu(header->boot_codesize), 862 IMEM_BLOCK_SIZE); 863 code_blocks = code_tag_blocks + code_size_blocks; 864 865 value = ((code_tag_blocks & L2IMEMOP_SIZE_SRC_OFFSET_MASK) << 866 L2IMEMOP_SIZE_SRC_OFFSET_SHIFT) | 867 ((code_size_blocks & L2IMEMOP_SIZE_SRC_COUNT_MASK) << 868 L2IMEMOP_SIZE_SRC_COUNT_SHIFT); 869 csb_writel(tegra, value, XUSB_CSB_MP_L2IMEMOP_SIZE); 870 871 /* Trigger L2IMEM load operation. */ 872 csb_writel(tegra, L2IMEMOP_LOAD_LOCKED_RESULT, 873 XUSB_CSB_MP_L2IMEMOP_TRIG); 874 875 /* Setup Falcon auto-fill. */ 876 csb_writel(tegra, code_size_blocks, XUSB_FALC_IMFILLCTL); 877 878 value = ((code_tag_blocks & IMFILLRNG1_TAG_MASK) << 879 IMFILLRNG1_TAG_LO_SHIFT) | 880 ((code_blocks & IMFILLRNG1_TAG_MASK) << 881 IMFILLRNG1_TAG_HI_SHIFT); 882 csb_writel(tegra, value, XUSB_FALC_IMFILLRNG1); 883 884 csb_writel(tegra, 0, XUSB_FALC_DMACTL); 885 886 msleep(50); 887 888 csb_writel(tegra, le32_to_cpu(header->boot_codetag), 889 XUSB_FALC_BOOTVEC); 890 891 /* Boot Falcon CPU and wait for it to enter the STOPPED (idle) state. */ 892 timeout = jiffies + msecs_to_jiffies(5); 893 894 csb_writel(tegra, CPUCTL_STARTCPU, XUSB_FALC_CPUCTL); 895 896 while (time_before(jiffies, timeout)) { 897 if (csb_readl(tegra, XUSB_FALC_CPUCTL) == CPUCTL_STATE_STOPPED) 898 break; 899 900 usleep_range(100, 200); 901 } 902 903 if (csb_readl(tegra, XUSB_FALC_CPUCTL) != CPUCTL_STATE_STOPPED) { 904 dev_err(dev, "Falcon failed to start, state: %#x\n", 905 csb_readl(tegra, XUSB_FALC_CPUCTL)); 906 return -EIO; 907 } 908 909 timestamp = le32_to_cpu(header->fwimg_created_time); 910 time64_to_tm(timestamp, 0, &time); 911 912 dev_info(dev, "Firmware timestamp: %ld-%02d-%02d %02d:%02d:%02d UTC\n", 913 time.tm_year + 1900, time.tm_mon + 1, time.tm_mday, 914 time.tm_hour, time.tm_min, time.tm_sec); 915 916 return 0; 917 } 918 919 static void tegra_xusb_powerdomain_remove(struct device *dev, 920 struct tegra_xusb *tegra) 921 { 922 if (tegra->genpd_dl_ss) 923 device_link_del(tegra->genpd_dl_ss); 924 if (tegra->genpd_dl_host) 925 device_link_del(tegra->genpd_dl_host); 926 if (!IS_ERR_OR_NULL(tegra->genpd_dev_ss)) 927 dev_pm_domain_detach(tegra->genpd_dev_ss, true); 928 if (!IS_ERR_OR_NULL(tegra->genpd_dev_host)) 929 dev_pm_domain_detach(tegra->genpd_dev_host, true); 930 } 931 932 static int tegra_xusb_powerdomain_init(struct device *dev, 933 struct tegra_xusb *tegra) 934 { 935 int err; 936 937 tegra->genpd_dev_host = dev_pm_domain_attach_by_name(dev, "xusb_host"); 938 if (IS_ERR(tegra->genpd_dev_host)) { 939 err = PTR_ERR(tegra->genpd_dev_host); 940 dev_err(dev, "failed to get host pm-domain: %d\n", err); 941 return err; 942 } 943 944 tegra->genpd_dev_ss = dev_pm_domain_attach_by_name(dev, "xusb_ss"); 945 if (IS_ERR(tegra->genpd_dev_ss)) { 946 err = PTR_ERR(tegra->genpd_dev_ss); 947 dev_err(dev, "failed to get superspeed pm-domain: %d\n", err); 948 return err; 949 } 950 951 tegra->genpd_dl_host = device_link_add(dev, tegra->genpd_dev_host, 952 DL_FLAG_PM_RUNTIME | 953 DL_FLAG_STATELESS); 954 if (!tegra->genpd_dl_host) { 955 dev_err(dev, "adding host device link failed!\n"); 956 return -ENODEV; 957 } 958 959 tegra->genpd_dl_ss = device_link_add(dev, tegra->genpd_dev_ss, 960 DL_FLAG_PM_RUNTIME | 961 DL_FLAG_STATELESS); 962 if (!tegra->genpd_dl_ss) { 963 dev_err(dev, "adding superspeed device link failed!\n"); 964 return -ENODEV; 965 } 966 967 return 0; 968 } 969 970 static int tegra_xusb_probe(struct platform_device *pdev) 971 { 972 struct tegra_xusb_mbox_msg msg; 973 struct resource *res, *regs; 974 struct tegra_xusb *tegra; 975 struct xhci_hcd *xhci; 976 unsigned int i, j, k; 977 struct phy *phy; 978 int err; 979 980 BUILD_BUG_ON(sizeof(struct tegra_xusb_fw_header) != 256); 981 982 tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL); 983 if (!tegra) 984 return -ENOMEM; 985 986 tegra->soc = of_device_get_match_data(&pdev->dev); 987 mutex_init(&tegra->lock); 988 tegra->dev = &pdev->dev; 989 990 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 991 tegra->regs = devm_ioremap_resource(&pdev->dev, regs); 992 if (IS_ERR(tegra->regs)) 993 return PTR_ERR(tegra->regs); 994 995 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 996 tegra->fpci_base = devm_ioremap_resource(&pdev->dev, res); 997 if (IS_ERR(tegra->fpci_base)) 998 return PTR_ERR(tegra->fpci_base); 999 1000 if (tegra->soc->has_ipfs) { 1001 res = platform_get_resource(pdev, IORESOURCE_MEM, 2); 1002 tegra->ipfs_base = devm_ioremap_resource(&pdev->dev, res); 1003 if (IS_ERR(tegra->ipfs_base)) 1004 return PTR_ERR(tegra->ipfs_base); 1005 } 1006 1007 tegra->xhci_irq = platform_get_irq(pdev, 0); 1008 if (tegra->xhci_irq < 0) 1009 return tegra->xhci_irq; 1010 1011 tegra->mbox_irq = platform_get_irq(pdev, 1); 1012 if (tegra->mbox_irq < 0) 1013 return tegra->mbox_irq; 1014 1015 tegra->padctl = tegra_xusb_padctl_get(&pdev->dev); 1016 if (IS_ERR(tegra->padctl)) 1017 return PTR_ERR(tegra->padctl); 1018 1019 tegra->host_clk = devm_clk_get(&pdev->dev, "xusb_host"); 1020 if (IS_ERR(tegra->host_clk)) { 1021 err = PTR_ERR(tegra->host_clk); 1022 dev_err(&pdev->dev, "failed to get xusb_host: %d\n", err); 1023 goto put_padctl; 1024 } 1025 1026 tegra->falcon_clk = devm_clk_get(&pdev->dev, "xusb_falcon_src"); 1027 if (IS_ERR(tegra->falcon_clk)) { 1028 err = PTR_ERR(tegra->falcon_clk); 1029 dev_err(&pdev->dev, "failed to get xusb_falcon_src: %d\n", err); 1030 goto put_padctl; 1031 } 1032 1033 tegra->ss_clk = devm_clk_get(&pdev->dev, "xusb_ss"); 1034 if (IS_ERR(tegra->ss_clk)) { 1035 err = PTR_ERR(tegra->ss_clk); 1036 dev_err(&pdev->dev, "failed to get xusb_ss: %d\n", err); 1037 goto put_padctl; 1038 } 1039 1040 tegra->ss_src_clk = devm_clk_get(&pdev->dev, "xusb_ss_src"); 1041 if (IS_ERR(tegra->ss_src_clk)) { 1042 err = PTR_ERR(tegra->ss_src_clk); 1043 dev_err(&pdev->dev, "failed to get xusb_ss_src: %d\n", err); 1044 goto put_padctl; 1045 } 1046 1047 tegra->hs_src_clk = devm_clk_get(&pdev->dev, "xusb_hs_src"); 1048 if (IS_ERR(tegra->hs_src_clk)) { 1049 err = PTR_ERR(tegra->hs_src_clk); 1050 dev_err(&pdev->dev, "failed to get xusb_hs_src: %d\n", err); 1051 goto put_padctl; 1052 } 1053 1054 tegra->fs_src_clk = devm_clk_get(&pdev->dev, "xusb_fs_src"); 1055 if (IS_ERR(tegra->fs_src_clk)) { 1056 err = PTR_ERR(tegra->fs_src_clk); 1057 dev_err(&pdev->dev, "failed to get xusb_fs_src: %d\n", err); 1058 goto put_padctl; 1059 } 1060 1061 tegra->pll_u_480m = devm_clk_get(&pdev->dev, "pll_u_480m"); 1062 if (IS_ERR(tegra->pll_u_480m)) { 1063 err = PTR_ERR(tegra->pll_u_480m); 1064 dev_err(&pdev->dev, "failed to get pll_u_480m: %d\n", err); 1065 goto put_padctl; 1066 } 1067 1068 tegra->clk_m = devm_clk_get(&pdev->dev, "clk_m"); 1069 if (IS_ERR(tegra->clk_m)) { 1070 err = PTR_ERR(tegra->clk_m); 1071 dev_err(&pdev->dev, "failed to get clk_m: %d\n", err); 1072 goto put_padctl; 1073 } 1074 1075 tegra->pll_e = devm_clk_get(&pdev->dev, "pll_e"); 1076 if (IS_ERR(tegra->pll_e)) { 1077 err = PTR_ERR(tegra->pll_e); 1078 dev_err(&pdev->dev, "failed to get pll_e: %d\n", err); 1079 goto put_padctl; 1080 } 1081 1082 if (!of_property_read_bool(pdev->dev.of_node, "power-domains")) { 1083 tegra->host_rst = devm_reset_control_get(&pdev->dev, 1084 "xusb_host"); 1085 if (IS_ERR(tegra->host_rst)) { 1086 err = PTR_ERR(tegra->host_rst); 1087 dev_err(&pdev->dev, 1088 "failed to get xusb_host reset: %d\n", err); 1089 goto put_padctl; 1090 } 1091 1092 tegra->ss_rst = devm_reset_control_get(&pdev->dev, "xusb_ss"); 1093 if (IS_ERR(tegra->ss_rst)) { 1094 err = PTR_ERR(tegra->ss_rst); 1095 dev_err(&pdev->dev, "failed to get xusb_ss reset: %d\n", 1096 err); 1097 goto put_padctl; 1098 } 1099 1100 err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_XUSBA, 1101 tegra->ss_clk, 1102 tegra->ss_rst); 1103 if (err) { 1104 dev_err(&pdev->dev, 1105 "failed to enable XUSBA domain: %d\n", err); 1106 goto put_padctl; 1107 } 1108 1109 err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_XUSBC, 1110 tegra->host_clk, 1111 tegra->host_rst); 1112 if (err) { 1113 tegra_powergate_power_off(TEGRA_POWERGATE_XUSBA); 1114 dev_err(&pdev->dev, 1115 "failed to enable XUSBC domain: %d\n", err); 1116 goto put_padctl; 1117 } 1118 } else { 1119 err = tegra_xusb_powerdomain_init(&pdev->dev, tegra); 1120 if (err) 1121 goto put_powerdomains; 1122 } 1123 1124 tegra->supplies = devm_kcalloc(&pdev->dev, tegra->soc->num_supplies, 1125 sizeof(*tegra->supplies), GFP_KERNEL); 1126 if (!tegra->supplies) { 1127 err = -ENOMEM; 1128 goto put_powerdomains; 1129 } 1130 1131 for (i = 0; i < tegra->soc->num_supplies; i++) 1132 tegra->supplies[i].supply = tegra->soc->supply_names[i]; 1133 1134 err = devm_regulator_bulk_get(&pdev->dev, tegra->soc->num_supplies, 1135 tegra->supplies); 1136 if (err) { 1137 dev_err(&pdev->dev, "failed to get regulators: %d\n", err); 1138 goto put_powerdomains; 1139 } 1140 1141 for (i = 0; i < tegra->soc->num_types; i++) 1142 tegra->num_phys += tegra->soc->phy_types[i].num; 1143 1144 tegra->phys = devm_kcalloc(&pdev->dev, tegra->num_phys, 1145 sizeof(*tegra->phys), GFP_KERNEL); 1146 if (!tegra->phys) { 1147 err = -ENOMEM; 1148 goto put_powerdomains; 1149 } 1150 1151 for (i = 0, k = 0; i < tegra->soc->num_types; i++) { 1152 char prop[8]; 1153 1154 for (j = 0; j < tegra->soc->phy_types[i].num; j++) { 1155 snprintf(prop, sizeof(prop), "%s-%d", 1156 tegra->soc->phy_types[i].name, j); 1157 1158 phy = devm_phy_optional_get(&pdev->dev, prop); 1159 if (IS_ERR(phy)) { 1160 dev_err(&pdev->dev, 1161 "failed to get PHY %s: %ld\n", prop, 1162 PTR_ERR(phy)); 1163 err = PTR_ERR(phy); 1164 goto put_powerdomains; 1165 } 1166 1167 tegra->phys[k++] = phy; 1168 } 1169 } 1170 1171 tegra->hcd = usb_create_hcd(&tegra_xhci_hc_driver, &pdev->dev, 1172 dev_name(&pdev->dev)); 1173 if (!tegra->hcd) { 1174 err = -ENOMEM; 1175 goto put_powerdomains; 1176 } 1177 1178 /* 1179 * This must happen after usb_create_hcd(), because usb_create_hcd() 1180 * will overwrite the drvdata of the device with the hcd it creates. 1181 */ 1182 platform_set_drvdata(pdev, tegra); 1183 1184 pm_runtime_enable(&pdev->dev); 1185 if (pm_runtime_enabled(&pdev->dev)) 1186 err = pm_runtime_get_sync(&pdev->dev); 1187 else 1188 err = tegra_xusb_runtime_resume(&pdev->dev); 1189 1190 if (err < 0) { 1191 dev_err(&pdev->dev, "failed to enable device: %d\n", err); 1192 goto disable_rpm; 1193 } 1194 1195 tegra_xusb_config(tegra, regs); 1196 1197 /* 1198 * The XUSB Falcon microcontroller can only address 40 bits, so set 1199 * the DMA mask accordingly. 1200 */ 1201 err = dma_set_mask_and_coherent(tegra->dev, DMA_BIT_MASK(40)); 1202 if (err < 0) { 1203 dev_err(&pdev->dev, "failed to set DMA mask: %d\n", err); 1204 goto put_rpm; 1205 } 1206 1207 err = tegra_xusb_load_firmware(tegra); 1208 if (err < 0) { 1209 dev_err(&pdev->dev, "failed to load firmware: %d\n", err); 1210 goto put_rpm; 1211 } 1212 1213 tegra->hcd->regs = tegra->regs; 1214 tegra->hcd->rsrc_start = regs->start; 1215 tegra->hcd->rsrc_len = resource_size(regs); 1216 1217 err = usb_add_hcd(tegra->hcd, tegra->xhci_irq, IRQF_SHARED); 1218 if (err < 0) { 1219 dev_err(&pdev->dev, "failed to add USB HCD: %d\n", err); 1220 goto put_rpm; 1221 } 1222 1223 device_wakeup_enable(tegra->hcd->self.controller); 1224 1225 xhci = hcd_to_xhci(tegra->hcd); 1226 1227 xhci->shared_hcd = usb_create_shared_hcd(&tegra_xhci_hc_driver, 1228 &pdev->dev, 1229 dev_name(&pdev->dev), 1230 tegra->hcd); 1231 if (!xhci->shared_hcd) { 1232 dev_err(&pdev->dev, "failed to create shared HCD\n"); 1233 err = -ENOMEM; 1234 goto remove_usb2; 1235 } 1236 1237 err = usb_add_hcd(xhci->shared_hcd, tegra->xhci_irq, IRQF_SHARED); 1238 if (err < 0) { 1239 dev_err(&pdev->dev, "failed to add shared HCD: %d\n", err); 1240 goto put_usb3; 1241 } 1242 1243 mutex_lock(&tegra->lock); 1244 1245 /* Enable firmware messages from controller. */ 1246 msg.cmd = MBOX_CMD_MSG_ENABLED; 1247 msg.data = 0; 1248 1249 err = tegra_xusb_mbox_send(tegra, &msg); 1250 if (err < 0) { 1251 dev_err(&pdev->dev, "failed to enable messages: %d\n", err); 1252 mutex_unlock(&tegra->lock); 1253 goto remove_usb3; 1254 } 1255 1256 mutex_unlock(&tegra->lock); 1257 1258 err = devm_request_threaded_irq(&pdev->dev, tegra->mbox_irq, 1259 tegra_xusb_mbox_irq, 1260 tegra_xusb_mbox_thread, 0, 1261 dev_name(&pdev->dev), tegra); 1262 if (err < 0) { 1263 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err); 1264 goto remove_usb3; 1265 } 1266 1267 return 0; 1268 1269 remove_usb3: 1270 usb_remove_hcd(xhci->shared_hcd); 1271 put_usb3: 1272 usb_put_hcd(xhci->shared_hcd); 1273 remove_usb2: 1274 usb_remove_hcd(tegra->hcd); 1275 put_rpm: 1276 if (!pm_runtime_status_suspended(&pdev->dev)) 1277 tegra_xusb_runtime_suspend(&pdev->dev); 1278 disable_rpm: 1279 pm_runtime_disable(&pdev->dev); 1280 usb_put_hcd(tegra->hcd); 1281 put_powerdomains: 1282 if (!of_property_read_bool(pdev->dev.of_node, "power-domains")) { 1283 tegra_powergate_power_off(TEGRA_POWERGATE_XUSBC); 1284 tegra_powergate_power_off(TEGRA_POWERGATE_XUSBA); 1285 } else { 1286 tegra_xusb_powerdomain_remove(&pdev->dev, tegra); 1287 } 1288 put_padctl: 1289 tegra_xusb_padctl_put(tegra->padctl); 1290 return err; 1291 } 1292 1293 static int tegra_xusb_remove(struct platform_device *pdev) 1294 { 1295 struct tegra_xusb *tegra = platform_get_drvdata(pdev); 1296 struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd); 1297 1298 usb_remove_hcd(xhci->shared_hcd); 1299 usb_put_hcd(xhci->shared_hcd); 1300 xhci->shared_hcd = NULL; 1301 usb_remove_hcd(tegra->hcd); 1302 usb_put_hcd(tegra->hcd); 1303 1304 dma_free_coherent(&pdev->dev, tegra->fw.size, tegra->fw.virt, 1305 tegra->fw.phys); 1306 1307 pm_runtime_put_sync(&pdev->dev); 1308 pm_runtime_disable(&pdev->dev); 1309 1310 if (!of_property_read_bool(pdev->dev.of_node, "power-domains")) { 1311 tegra_powergate_power_off(TEGRA_POWERGATE_XUSBC); 1312 tegra_powergate_power_off(TEGRA_POWERGATE_XUSBA); 1313 } else { 1314 tegra_xusb_powerdomain_remove(&pdev->dev, tegra); 1315 } 1316 1317 tegra_xusb_padctl_put(tegra->padctl); 1318 1319 return 0; 1320 } 1321 1322 #ifdef CONFIG_PM_SLEEP 1323 static int tegra_xusb_suspend(struct device *dev) 1324 { 1325 struct tegra_xusb *tegra = dev_get_drvdata(dev); 1326 struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd); 1327 bool wakeup = device_may_wakeup(dev); 1328 1329 /* TODO: Powergate controller across suspend/resume. */ 1330 return xhci_suspend(xhci, wakeup); 1331 } 1332 1333 static int tegra_xusb_resume(struct device *dev) 1334 { 1335 struct tegra_xusb *tegra = dev_get_drvdata(dev); 1336 struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd); 1337 1338 return xhci_resume(xhci, 0); 1339 } 1340 #endif 1341 1342 static const struct dev_pm_ops tegra_xusb_pm_ops = { 1343 SET_RUNTIME_PM_OPS(tegra_xusb_runtime_suspend, 1344 tegra_xusb_runtime_resume, NULL) 1345 SET_SYSTEM_SLEEP_PM_OPS(tegra_xusb_suspend, tegra_xusb_resume) 1346 }; 1347 1348 static const char * const tegra124_supply_names[] = { 1349 "avddio-pex", 1350 "dvddio-pex", 1351 "avdd-usb", 1352 "avdd-pll-utmip", 1353 "avdd-pll-erefe", 1354 "avdd-usb-ss-pll", 1355 "hvdd-usb-ss", 1356 "hvdd-usb-ss-pll-e", 1357 }; 1358 1359 static const struct tegra_xusb_phy_type tegra124_phy_types[] = { 1360 { .name = "usb3", .num = 2, }, 1361 { .name = "usb2", .num = 3, }, 1362 { .name = "hsic", .num = 2, }, 1363 }; 1364 1365 static const struct tegra_xusb_soc tegra124_soc = { 1366 .firmware = "nvidia/tegra124/xusb.bin", 1367 .supply_names = tegra124_supply_names, 1368 .num_supplies = ARRAY_SIZE(tegra124_supply_names), 1369 .phy_types = tegra124_phy_types, 1370 .num_types = ARRAY_SIZE(tegra124_phy_types), 1371 .ports = { 1372 .usb2 = { .offset = 4, .count = 4, }, 1373 .hsic = { .offset = 6, .count = 2, }, 1374 .usb3 = { .offset = 0, .count = 2, }, 1375 }, 1376 .scale_ss_clock = true, 1377 .has_ipfs = true, 1378 }; 1379 MODULE_FIRMWARE("nvidia/tegra124/xusb.bin"); 1380 1381 static const char * const tegra210_supply_names[] = { 1382 "dvddio-pex", 1383 "hvddio-pex", 1384 "avdd-usb", 1385 "avdd-pll-utmip", 1386 "avdd-pll-uerefe", 1387 "dvdd-pex-pll", 1388 "hvdd-pex-pll-e", 1389 }; 1390 1391 static const struct tegra_xusb_phy_type tegra210_phy_types[] = { 1392 { .name = "usb3", .num = 4, }, 1393 { .name = "usb2", .num = 4, }, 1394 { .name = "hsic", .num = 1, }, 1395 }; 1396 1397 static const struct tegra_xusb_soc tegra210_soc = { 1398 .firmware = "nvidia/tegra210/xusb.bin", 1399 .supply_names = tegra210_supply_names, 1400 .num_supplies = ARRAY_SIZE(tegra210_supply_names), 1401 .phy_types = tegra210_phy_types, 1402 .num_types = ARRAY_SIZE(tegra210_phy_types), 1403 .ports = { 1404 .usb2 = { .offset = 4, .count = 4, }, 1405 .hsic = { .offset = 8, .count = 1, }, 1406 .usb3 = { .offset = 0, .count = 4, }, 1407 }, 1408 .scale_ss_clock = false, 1409 .has_ipfs = true, 1410 }; 1411 MODULE_FIRMWARE("nvidia/tegra210/xusb.bin"); 1412 1413 static const char * const tegra186_supply_names[] = { 1414 }; 1415 1416 static const struct tegra_xusb_phy_type tegra186_phy_types[] = { 1417 { .name = "usb3", .num = 3, }, 1418 { .name = "usb2", .num = 3, }, 1419 { .name = "hsic", .num = 1, }, 1420 }; 1421 1422 static const struct tegra_xusb_soc tegra186_soc = { 1423 .firmware = "nvidia/tegra186/xusb.bin", 1424 .supply_names = tegra186_supply_names, 1425 .num_supplies = ARRAY_SIZE(tegra186_supply_names), 1426 .phy_types = tegra186_phy_types, 1427 .num_types = ARRAY_SIZE(tegra186_phy_types), 1428 .ports = { 1429 .usb3 = { .offset = 0, .count = 3, }, 1430 .usb2 = { .offset = 3, .count = 3, }, 1431 .hsic = { .offset = 6, .count = 1, }, 1432 }, 1433 .scale_ss_clock = false, 1434 .has_ipfs = false, 1435 }; 1436 1437 static const struct of_device_id tegra_xusb_of_match[] = { 1438 { .compatible = "nvidia,tegra124-xusb", .data = &tegra124_soc }, 1439 { .compatible = "nvidia,tegra210-xusb", .data = &tegra210_soc }, 1440 { .compatible = "nvidia,tegra186-xusb", .data = &tegra186_soc }, 1441 { }, 1442 }; 1443 MODULE_DEVICE_TABLE(of, tegra_xusb_of_match); 1444 1445 static struct platform_driver tegra_xusb_driver = { 1446 .probe = tegra_xusb_probe, 1447 .remove = tegra_xusb_remove, 1448 .driver = { 1449 .name = "tegra-xusb", 1450 .pm = &tegra_xusb_pm_ops, 1451 .of_match_table = tegra_xusb_of_match, 1452 }, 1453 }; 1454 1455 static void tegra_xhci_quirks(struct device *dev, struct xhci_hcd *xhci) 1456 { 1457 xhci->quirks |= XHCI_PLAT; 1458 } 1459 1460 static int tegra_xhci_setup(struct usb_hcd *hcd) 1461 { 1462 return xhci_gen_setup(hcd, tegra_xhci_quirks); 1463 } 1464 1465 static const struct xhci_driver_overrides tegra_xhci_overrides __initconst = { 1466 .reset = tegra_xhci_setup, 1467 }; 1468 1469 static int __init tegra_xusb_init(void) 1470 { 1471 xhci_init_driver(&tegra_xhci_hc_driver, &tegra_xhci_overrides); 1472 1473 return platform_driver_register(&tegra_xusb_driver); 1474 } 1475 module_init(tegra_xusb_init); 1476 1477 static void __exit tegra_xusb_exit(void) 1478 { 1479 platform_driver_unregister(&tegra_xusb_driver); 1480 } 1481 module_exit(tegra_xusb_exit); 1482 1483 MODULE_AUTHOR("Andrew Bresticker <abrestic@chromium.org>"); 1484 MODULE_DESCRIPTION("NVIDIA Tegra XUSB xHCI host-controller driver"); 1485 MODULE_LICENSE("GPL v2"); 1486