129e9ead2SNishad Kamdar /* SPDX-License-Identifier: GPL-2.0 */ 27ef077a8SLaurent Pinchart /* 37ef077a8SLaurent Pinchart * Driver for the NXP ISP1760 chip 47ef077a8SLaurent Pinchart * 560d789f3SRui Miguel Silva * Copyright 2021 Linaro, Rui Miguel Silva 67ef077a8SLaurent Pinchart * Copyright 2014 Laurent Pinchart 77ef077a8SLaurent Pinchart * Copyright 2007 Sebastian Siewior 87ef077a8SLaurent Pinchart * 97ef077a8SLaurent Pinchart * Contacts: 107ef077a8SLaurent Pinchart * Sebastian Siewior <bigeasy@linutronix.de> 117ef077a8SLaurent Pinchart * Laurent Pinchart <laurent.pinchart@ideasonboard.com> 1260d789f3SRui Miguel Silva * Rui Miguel Silva <rui.silva@linaro.org> 137ef077a8SLaurent Pinchart */ 147ef077a8SLaurent Pinchart 151da9e1c0SRui Miguel Silva #ifndef _ISP176x_REGS_H_ 161da9e1c0SRui Miguel Silva #define _ISP176x_REGS_H_ 177ef077a8SLaurent Pinchart 187ef077a8SLaurent Pinchart /* ----------------------------------------------------------------------------- 197ef077a8SLaurent Pinchart * Host Controller 207ef077a8SLaurent Pinchart */ 217ef077a8SLaurent Pinchart 2260d789f3SRui Miguel Silva /* ISP1760/31 */ 237ef077a8SLaurent Pinchart /* EHCI capability registers */ 241da9e1c0SRui Miguel Silva #define ISP176x_HC_VERSION 0x002 251da9e1c0SRui Miguel Silva #define ISP176x_HC_HCSPARAMS 0x004 261da9e1c0SRui Miguel Silva #define ISP176x_HC_HCCPARAMS 0x008 277ef077a8SLaurent Pinchart 287ef077a8SLaurent Pinchart /* EHCI operational registers */ 291da9e1c0SRui Miguel Silva #define ISP176x_HC_USBCMD 0x020 301da9e1c0SRui Miguel Silva #define ISP176x_HC_USBSTS 0x024 311da9e1c0SRui Miguel Silva #define ISP176x_HC_FRINDEX 0x02c 327ef077a8SLaurent Pinchart 331da9e1c0SRui Miguel Silva #define ISP176x_HC_CONFIGFLAG 0x060 341da9e1c0SRui Miguel Silva #define ISP176x_HC_PORTSC1 0x064 357ef077a8SLaurent Pinchart 361da9e1c0SRui Miguel Silva #define ISP176x_HC_ISO_PTD_DONEMAP 0x130 371da9e1c0SRui Miguel Silva #define ISP176x_HC_ISO_PTD_SKIPMAP 0x134 381da9e1c0SRui Miguel Silva #define ISP176x_HC_ISO_PTD_LASTPTD 0x138 391da9e1c0SRui Miguel Silva #define ISP176x_HC_INT_PTD_DONEMAP 0x140 401da9e1c0SRui Miguel Silva #define ISP176x_HC_INT_PTD_SKIPMAP 0x144 411da9e1c0SRui Miguel Silva #define ISP176x_HC_INT_PTD_LASTPTD 0x148 421da9e1c0SRui Miguel Silva #define ISP176x_HC_ATL_PTD_DONEMAP 0x150 431da9e1c0SRui Miguel Silva #define ISP176x_HC_ATL_PTD_SKIPMAP 0x154 441da9e1c0SRui Miguel Silva #define ISP176x_HC_ATL_PTD_LASTPTD 0x158 457ef077a8SLaurent Pinchart 467ef077a8SLaurent Pinchart /* Configuration Register */ 471da9e1c0SRui Miguel Silva #define ISP176x_HC_HW_MODE_CTRL 0x300 481da9e1c0SRui Miguel Silva #define ISP176x_HC_CHIP_ID 0x304 491da9e1c0SRui Miguel Silva #define ISP176x_HC_SCRATCH 0x308 501da9e1c0SRui Miguel Silva #define ISP176x_HC_RESET 0x30c 511da9e1c0SRui Miguel Silva #define ISP176x_HC_BUFFER_STATUS 0x334 521da9e1c0SRui Miguel Silva #define ISP176x_HC_MEMORY 0x33c 537ef077a8SLaurent Pinchart 547ef077a8SLaurent Pinchart /* Interrupt Register */ 551da9e1c0SRui Miguel Silva #define ISP176x_HC_INTERRUPT 0x310 561da9e1c0SRui Miguel Silva #define ISP176x_HC_INTERRUPT_ENABLE 0x314 571da9e1c0SRui Miguel Silva #define ISP176x_HC_ISO_IRQ_MASK_OR 0x318 581da9e1c0SRui Miguel Silva #define ISP176x_HC_INT_IRQ_MASK_OR 0x31c 591da9e1c0SRui Miguel Silva #define ISP176x_HC_ATL_IRQ_MASK_OR 0x320 601da9e1c0SRui Miguel Silva #define ISP176x_HC_ISO_IRQ_MASK_AND 0x324 611da9e1c0SRui Miguel Silva #define ISP176x_HC_INT_IRQ_MASK_AND 0x328 621da9e1c0SRui Miguel Silva #define ISP176x_HC_ATL_IRQ_MASK_AND 0x32c 637ef077a8SLaurent Pinchart 6460d789f3SRui Miguel Silva #define ISP176x_HC_OTG_CTRL_SET 0x374 6560d789f3SRui Miguel Silva #define ISP176x_HC_OTG_CTRL_CLEAR 0x376 6660d789f3SRui Miguel Silva 671da9e1c0SRui Miguel Silva enum isp176x_host_controller_fields { 6860d789f3SRui Miguel Silva /* HC_PORTSC1 */ 6960d789f3SRui Miguel Silva PORT_OWNER, PORT_POWER, PORT_LSTATUS, PORT_RESET, PORT_SUSPEND, 7060d789f3SRui Miguel Silva PORT_RESUME, PORT_PE, PORT_CSC, PORT_CONNECT, 711da9e1c0SRui Miguel Silva /* HC_HCSPARAMS */ 721da9e1c0SRui Miguel Silva HCS_PPC, HCS_N_PORTS, 731da9e1c0SRui Miguel Silva /* HC_HCCPARAMS */ 741da9e1c0SRui Miguel Silva HCC_ISOC_CACHE, HCC_ISOC_THRES, 751da9e1c0SRui Miguel Silva /* HC_USBCMD */ 761da9e1c0SRui Miguel Silva CMD_LRESET, CMD_RESET, CMD_RUN, 771da9e1c0SRui Miguel Silva /* HC_USBSTS */ 781da9e1c0SRui Miguel Silva STS_PCD, 791da9e1c0SRui Miguel Silva /* HC_FRINDEX */ 801da9e1c0SRui Miguel Silva HC_FRINDEX, 811da9e1c0SRui Miguel Silva /* HC_CONFIGFLAG */ 821da9e1c0SRui Miguel Silva FLAG_CF, 8360d789f3SRui Miguel Silva /* ISO/INT/ATL PTD */ 8460d789f3SRui Miguel Silva HC_ISO_PTD_DONEMAP, HC_ISO_PTD_SKIPMAP, HC_ISO_PTD_LASTPTD, 8560d789f3SRui Miguel Silva HC_INT_PTD_DONEMAP, HC_INT_PTD_SKIPMAP, HC_INT_PTD_LASTPTD, 8660d789f3SRui Miguel Silva HC_ATL_PTD_DONEMAP, HC_ATL_PTD_SKIPMAP, HC_ATL_PTD_LASTPTD, 871da9e1c0SRui Miguel Silva /* HC_HW_MODE_CTRL */ 881da9e1c0SRui Miguel Silva ALL_ATX_RESET, HW_ANA_DIGI_OC, HW_DEV_DMA, HW_COMN_IRQ, HW_COMN_DMA, 891da9e1c0SRui Miguel Silva HW_DATA_BUS_WIDTH, HW_DACK_POL_HIGH, HW_DREQ_POL_HIGH, HW_INTR_HIGH_ACT, 9060d789f3SRui Miguel Silva HW_INTF_LOCK, HW_INTR_EDGE_TRIG, HW_GLOBAL_INTR_EN, 9160d789f3SRui Miguel Silva /* HC_CHIP_ID */ 9260d789f3SRui Miguel Silva HC_CHIP_ID_HIGH, HC_CHIP_ID_LOW, HC_CHIP_REV, 9360d789f3SRui Miguel Silva /* HC_SCRATCH */ 9460d789f3SRui Miguel Silva HC_SCRATCH, 951da9e1c0SRui Miguel Silva /* HC_RESET */ 9660d789f3SRui Miguel Silva SW_RESET_RESET_ATX, SW_RESET_RESET_HC, SW_RESET_RESET_ALL, 971da9e1c0SRui Miguel Silva /* HC_BUFFER_STATUS */ 9860d789f3SRui Miguel Silva ISO_BUF_FILL, INT_BUF_FILL, ATL_BUF_FILL, 991da9e1c0SRui Miguel Silva /* HC_MEMORY */ 1001da9e1c0SRui Miguel Silva MEM_BANK_SEL, MEM_START_ADDR, 10160d789f3SRui Miguel Silva /* HC_DATA */ 10260d789f3SRui Miguel Silva HC_DATA, 10360d789f3SRui Miguel Silva /* HC_INTERRUPT */ 10460d789f3SRui Miguel Silva HC_INTERRUPT, 1051da9e1c0SRui Miguel Silva /* HC_INTERRUPT_ENABLE */ 10660d789f3SRui Miguel Silva HC_INT_IRQ_ENABLE, HC_ATL_IRQ_ENABLE, 10760d789f3SRui Miguel Silva /* INTERRUPT MASKS */ 10860d789f3SRui Miguel Silva HC_ISO_IRQ_MASK_OR, HC_INT_IRQ_MASK_OR, HC_ATL_IRQ_MASK_OR, 10960d789f3SRui Miguel Silva HC_ISO_IRQ_MASK_AND, HC_INT_IRQ_MASK_AND, HC_ATL_IRQ_MASK_AND, 11060d789f3SRui Miguel Silva /* HW_OTG_CTRL_SET */ 11160d789f3SRui Miguel Silva HW_OTG_DISABLE, HW_SW_SEL_HC_DC, HW_VBUS_DRV, HW_SEL_CP_EXT, 11260d789f3SRui Miguel Silva HW_DM_PULLDOWN, HW_DP_PULLDOWN, HW_DP_PULLUP, HW_HC_2_DIS, 11360d789f3SRui Miguel Silva /* HW_OTG_CTRL_CLR */ 11460d789f3SRui Miguel Silva HW_OTG_DISABLE_CLEAR, HW_SW_SEL_HC_DC_CLEAR, HW_VBUS_DRV_CLEAR, 11560d789f3SRui Miguel Silva HW_SEL_CP_EXT_CLEAR, HW_DM_PULLDOWN_CLEAR, HW_DP_PULLDOWN_CLEAR, 11660d789f3SRui Miguel Silva HW_DP_PULLUP_CLEAR, HW_HC_2_DIS_CLEAR, 1171da9e1c0SRui Miguel Silva /* Last element */ 1181da9e1c0SRui Miguel Silva HC_FIELD_MAX, 1191da9e1c0SRui Miguel Silva }; 1207ef077a8SLaurent Pinchart 12160d789f3SRui Miguel Silva /* ISP1763 */ 12260d789f3SRui Miguel Silva /* EHCI operational registers */ 12360d789f3SRui Miguel Silva #define ISP1763_HC_USBCMD 0x8c 12460d789f3SRui Miguel Silva #define ISP1763_HC_USBSTS 0x90 12560d789f3SRui Miguel Silva #define ISP1763_HC_FRINDEX 0x98 12660d789f3SRui Miguel Silva 12760d789f3SRui Miguel Silva #define ISP1763_HC_CONFIGFLAG 0x9c 12860d789f3SRui Miguel Silva #define ISP1763_HC_PORTSC1 0xa0 12960d789f3SRui Miguel Silva 13060d789f3SRui Miguel Silva #define ISP1763_HC_ISO_PTD_DONEMAP 0xa4 13160d789f3SRui Miguel Silva #define ISP1763_HC_ISO_PTD_SKIPMAP 0xa6 13260d789f3SRui Miguel Silva #define ISP1763_HC_ISO_PTD_LASTPTD 0xa8 13360d789f3SRui Miguel Silva #define ISP1763_HC_INT_PTD_DONEMAP 0xaa 13460d789f3SRui Miguel Silva #define ISP1763_HC_INT_PTD_SKIPMAP 0xac 13560d789f3SRui Miguel Silva #define ISP1763_HC_INT_PTD_LASTPTD 0xae 13660d789f3SRui Miguel Silva #define ISP1763_HC_ATL_PTD_DONEMAP 0xb0 13760d789f3SRui Miguel Silva #define ISP1763_HC_ATL_PTD_SKIPMAP 0xb2 13860d789f3SRui Miguel Silva #define ISP1763_HC_ATL_PTD_LASTPTD 0xb4 13960d789f3SRui Miguel Silva 14060d789f3SRui Miguel Silva /* Configuration Register */ 14160d789f3SRui Miguel Silva #define ISP1763_HC_HW_MODE_CTRL 0xb6 14260d789f3SRui Miguel Silva #define ISP1763_HC_CHIP_REV 0x70 14360d789f3SRui Miguel Silva #define ISP1763_HC_CHIP_ID 0x72 14460d789f3SRui Miguel Silva #define ISP1763_HC_SCRATCH 0x78 14560d789f3SRui Miguel Silva #define ISP1763_HC_RESET 0xb8 14660d789f3SRui Miguel Silva #define ISP1763_HC_BUFFER_STATUS 0xba 14760d789f3SRui Miguel Silva #define ISP1763_HC_MEMORY 0xc4 14860d789f3SRui Miguel Silva #define ISP1763_HC_DATA 0xc6 14960d789f3SRui Miguel Silva 15060d789f3SRui Miguel Silva /* Interrupt Register */ 15160d789f3SRui Miguel Silva #define ISP1763_HC_INTERRUPT 0xd4 15260d789f3SRui Miguel Silva #define ISP1763_HC_INTERRUPT_ENABLE 0xd6 15360d789f3SRui Miguel Silva #define ISP1763_HC_ISO_IRQ_MASK_OR 0xd8 15460d789f3SRui Miguel Silva #define ISP1763_HC_INT_IRQ_MASK_OR 0xda 15560d789f3SRui Miguel Silva #define ISP1763_HC_ATL_IRQ_MASK_OR 0xdc 15660d789f3SRui Miguel Silva #define ISP1763_HC_ISO_IRQ_MASK_AND 0xde 15760d789f3SRui Miguel Silva #define ISP1763_HC_INT_IRQ_MASK_AND 0xe0 15860d789f3SRui Miguel Silva #define ISP1763_HC_ATL_IRQ_MASK_AND 0xe2 15960d789f3SRui Miguel Silva 16060d789f3SRui Miguel Silva #define ISP1763_HC_OTG_CTRL_SET 0xe4 16160d789f3SRui Miguel Silva #define ISP1763_HC_OTG_CTRL_CLEAR 0xe6 16260d789f3SRui Miguel Silva 1637ef077a8SLaurent Pinchart /* ----------------------------------------------------------------------------- 1647ef077a8SLaurent Pinchart * Peripheral Controller 1657ef077a8SLaurent Pinchart */ 1667ef077a8SLaurent Pinchart 1677ef077a8SLaurent Pinchart #define DC_IEPTX(n) (1 << (11 + 2 * (n))) 1687ef077a8SLaurent Pinchart #define DC_IEPRX(n) (1 << (10 + 2 * (n))) 1697ef077a8SLaurent Pinchart #define DC_IEPRXTX(n) (3 << (10 + 2 * (n))) 1701da9e1c0SRui Miguel Silva 1711da9e1c0SRui Miguel Silva #define ISP176x_DC_CDBGMOD_ACK BIT(6) 1721da9e1c0SRui Miguel Silva #define ISP176x_DC_DDBGMODIN_ACK BIT(4) 1731da9e1c0SRui Miguel Silva #define ISP176x_DC_DDBGMODOUT_ACK BIT(2) 1741da9e1c0SRui Miguel Silva 1751da9e1c0SRui Miguel Silva #define ISP176x_DC_IEP0SETUP BIT(8) 1761da9e1c0SRui Miguel Silva #define ISP176x_DC_IEVBUS BIT(7) 1771da9e1c0SRui Miguel Silva #define ISP176x_DC_IEHS_STA BIT(5) 1781da9e1c0SRui Miguel Silva #define ISP176x_DC_IERESM BIT(4) 1791da9e1c0SRui Miguel Silva #define ISP176x_DC_IESUSP BIT(3) 1801da9e1c0SRui Miguel Silva #define ISP176x_DC_IEBRST BIT(0) 1811da9e1c0SRui Miguel Silva 1821da9e1c0SRui Miguel Silva #define ISP176x_DC_ENDPTYP_ISOC 0x01 1831da9e1c0SRui Miguel Silva #define ISP176x_DC_ENDPTYP_BULK 0x02 1841da9e1c0SRui Miguel Silva #define ISP176x_DC_ENDPTYP_INTERRUPT 0x03 1851da9e1c0SRui Miguel Silva 1861da9e1c0SRui Miguel Silva /* Initialization Registers */ 1871da9e1c0SRui Miguel Silva #define ISP176x_DC_ADDRESS 0x0200 1881da9e1c0SRui Miguel Silva #define ISP176x_DC_MODE 0x020c 1891da9e1c0SRui Miguel Silva #define ISP176x_DC_INTCONF 0x0210 1901da9e1c0SRui Miguel Silva #define ISP176x_DC_DEBUG 0x0212 1911da9e1c0SRui Miguel Silva #define ISP176x_DC_INTENABLE 0x0214 1927ef077a8SLaurent Pinchart 1937ef077a8SLaurent Pinchart /* Data Flow Registers */ 1941da9e1c0SRui Miguel Silva #define ISP176x_DC_EPMAXPKTSZ 0x0204 1951da9e1c0SRui Miguel Silva #define ISP176x_DC_EPTYPE 0x0208 1967ef077a8SLaurent Pinchart 1971da9e1c0SRui Miguel Silva #define ISP176x_DC_BUFLEN 0x021c 1981da9e1c0SRui Miguel Silva #define ISP176x_DC_BUFSTAT 0x021e 1991da9e1c0SRui Miguel Silva #define ISP176x_DC_DATAPORT 0x0220 2007ef077a8SLaurent Pinchart 2011da9e1c0SRui Miguel Silva #define ISP176x_DC_CTRLFUNC 0x0228 2021da9e1c0SRui Miguel Silva #define ISP176x_DC_EPINDEX 0x022c 2037ef077a8SLaurent Pinchart 2047ef077a8SLaurent Pinchart /* DMA Registers */ 2051da9e1c0SRui Miguel Silva #define ISP176x_DC_DMACMD 0x0230 2061da9e1c0SRui Miguel Silva #define ISP176x_DC_DMATXCOUNT 0x0234 2071da9e1c0SRui Miguel Silva #define ISP176x_DC_DMACONF 0x0238 2081da9e1c0SRui Miguel Silva #define ISP176x_DC_DMAHW 0x023c 2091da9e1c0SRui Miguel Silva #define ISP176x_DC_DMAINTREASON 0x0250 2101da9e1c0SRui Miguel Silva #define ISP176x_DC_DMAINTEN 0x0254 2111da9e1c0SRui Miguel Silva #define ISP176x_DC_DMAEP 0x0258 2121da9e1c0SRui Miguel Silva #define ISP176x_DC_DMABURSTCOUNT 0x0264 2137ef077a8SLaurent Pinchart 2147ef077a8SLaurent Pinchart /* General Registers */ 2151da9e1c0SRui Miguel Silva #define ISP176x_DC_INTERRUPT 0x0218 2161da9e1c0SRui Miguel Silva #define ISP176x_DC_CHIPID 0x0270 2171da9e1c0SRui Miguel Silva #define ISP176x_DC_FRAMENUM 0x0274 2181da9e1c0SRui Miguel Silva #define ISP176x_DC_SCRATCH 0x0278 2191da9e1c0SRui Miguel Silva #define ISP176x_DC_UNLOCKDEV 0x027c 2201da9e1c0SRui Miguel Silva #define ISP176x_DC_INTPULSEWIDTH 0x0280 2211da9e1c0SRui Miguel Silva #define ISP176x_DC_TESTMODE 0x0284 2221da9e1c0SRui Miguel Silva 2231da9e1c0SRui Miguel Silva enum isp176x_device_controller_fields { 2241da9e1c0SRui Miguel Silva /* DC_ADDRESS */ 2251da9e1c0SRui Miguel Silva DC_DEVEN, DC_DEVADDR, 2261da9e1c0SRui Miguel Silva /* DC_MODE */ 2271da9e1c0SRui Miguel Silva DC_VBUSSTAT, DC_SFRESET, DC_GLINTENA, 2281da9e1c0SRui Miguel Silva /* DC_INTCONF */ 2291da9e1c0SRui Miguel Silva DC_CDBGMOD_ACK, DC_DDBGMODIN_ACK, DC_DDBGMODOUT_ACK, DC_INTPOL, 2301da9e1c0SRui Miguel Silva /* DC_INTENABLE */ 2311da9e1c0SRui Miguel Silva DC_IEPRXTX_7, DC_IEPRXTX_6, DC_IEPRXTX_5, DC_IEPRXTX_4, DC_IEPRXTX_3, 2321da9e1c0SRui Miguel Silva DC_IEPRXTX_2, DC_IEPRXTX_1, DC_IEPRXTX_0, 2331da9e1c0SRui Miguel Silva DC_IEP0SETUP, DC_IEVBUS, DC_IEHS_STA, DC_IERESM, DC_IESUSP, DC_IEBRST, 2341da9e1c0SRui Miguel Silva /* DC_EPINDEX */ 2351da9e1c0SRui Miguel Silva DC_EP0SETUP, DC_ENDPIDX, DC_EPDIR, 2361da9e1c0SRui Miguel Silva /* DC_CTRLFUNC */ 2371da9e1c0SRui Miguel Silva DC_CLBUF, DC_VENDP, DC_DSEN, DC_STATUS, DC_STALL, 2381da9e1c0SRui Miguel Silva /* DC_BUFLEN */ 2391da9e1c0SRui Miguel Silva DC_BUFLEN, 2401da9e1c0SRui Miguel Silva /* DC_EPMAXPKTSZ */ 2411da9e1c0SRui Miguel Silva DC_FFOSZ, 2421da9e1c0SRui Miguel Silva /* DC_EPTYPE */ 2431da9e1c0SRui Miguel Silva DC_EPENABLE, DC_ENDPTYP, 2441da9e1c0SRui Miguel Silva /* DC_FRAMENUM */ 2451da9e1c0SRui Miguel Silva DC_FRAMENUM, DC_UFRAMENUM, 246*d369c918SRui Miguel Silva /* DC_CHIP_ID */ 247*d369c918SRui Miguel Silva DC_CHIP_ID_HIGH, DC_CHIP_ID_LOW, 248*d369c918SRui Miguel Silva /* DC_SCRATCH */ 249*d369c918SRui Miguel Silva DC_SCRATCH, 2501da9e1c0SRui Miguel Silva /* Last element */ 2511da9e1c0SRui Miguel Silva DC_FIELD_MAX, 2521da9e1c0SRui Miguel Silva }; 2537ef077a8SLaurent Pinchart 254*d369c918SRui Miguel Silva /* ISP1763 */ 255*d369c918SRui Miguel Silva /* Initialization Registers */ 256*d369c918SRui Miguel Silva #define ISP1763_DC_ADDRESS 0x00 257*d369c918SRui Miguel Silva #define ISP1763_DC_MODE 0x0c 258*d369c918SRui Miguel Silva #define ISP1763_DC_INTCONF 0x10 259*d369c918SRui Miguel Silva #define ISP1763_DC_INTENABLE 0x14 260*d369c918SRui Miguel Silva 261*d369c918SRui Miguel Silva /* Data Flow Registers */ 262*d369c918SRui Miguel Silva #define ISP1763_DC_EPMAXPKTSZ 0x04 263*d369c918SRui Miguel Silva #define ISP1763_DC_EPTYPE 0x08 264*d369c918SRui Miguel Silva 265*d369c918SRui Miguel Silva #define ISP1763_DC_BUFLEN 0x1c 266*d369c918SRui Miguel Silva #define ISP1763_DC_BUFSTAT 0x1e 267*d369c918SRui Miguel Silva #define ISP1763_DC_DATAPORT 0x20 268*d369c918SRui Miguel Silva 269*d369c918SRui Miguel Silva #define ISP1763_DC_CTRLFUNC 0x28 270*d369c918SRui Miguel Silva #define ISP1763_DC_EPINDEX 0x2c 271*d369c918SRui Miguel Silva 272*d369c918SRui Miguel Silva /* DMA Registers */ 273*d369c918SRui Miguel Silva #define ISP1763_DC_DMACMD 0x30 274*d369c918SRui Miguel Silva #define ISP1763_DC_DMATXCOUNT 0x34 275*d369c918SRui Miguel Silva #define ISP1763_DC_DMACONF 0x38 276*d369c918SRui Miguel Silva #define ISP1763_DC_DMAHW 0x3c 277*d369c918SRui Miguel Silva #define ISP1763_DC_DMAINTREASON 0x50 278*d369c918SRui Miguel Silva #define ISP1763_DC_DMAINTEN 0x54 279*d369c918SRui Miguel Silva #define ISP1763_DC_DMAEP 0x58 280*d369c918SRui Miguel Silva #define ISP1763_DC_DMABURSTCOUNT 0x64 281*d369c918SRui Miguel Silva 282*d369c918SRui Miguel Silva /* General Registers */ 283*d369c918SRui Miguel Silva #define ISP1763_DC_INTERRUPT 0x18 284*d369c918SRui Miguel Silva #define ISP1763_DC_CHIPID_LOW 0x70 285*d369c918SRui Miguel Silva #define ISP1763_DC_CHIPID_HIGH 0x72 286*d369c918SRui Miguel Silva #define ISP1763_DC_FRAMENUM 0x74 287*d369c918SRui Miguel Silva #define ISP1763_DC_SCRATCH 0x78 288*d369c918SRui Miguel Silva #define ISP1763_DC_UNLOCKDEV 0x7c 289*d369c918SRui Miguel Silva #define ISP1763_DC_INTPULSEWIDTH 0x80 290*d369c918SRui Miguel Silva #define ISP1763_DC_TESTMODE 0x84 291*d369c918SRui Miguel Silva 2927ef077a8SLaurent Pinchart #endif 293