1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2023, Linaro Ltd. All rights reserved. 5 */ 6 #ifndef __QCOM_PMIC_PDPHY_H__ 7 #define __QCOM_PMIC_PDPHY_H__ 8 9 #include <linux/platform_device.h> 10 #include <linux/regmap.h> 11 #include <linux/usb/tcpm.h> 12 13 #define USB_PDPHY_MAX_DATA_OBJ_LEN 28 14 #define USB_PDPHY_MSG_HDR_LEN 2 15 16 /* PD PHY register offsets and bit fields */ 17 #define USB_PDPHY_MSG_CONFIG_REG 0x40 18 #define MSG_CONFIG_PORT_DATA_ROLE BIT(3) 19 #define MSG_CONFIG_PORT_POWER_ROLE BIT(2) 20 #define MSG_CONFIG_SPEC_REV_MASK (BIT(1) | BIT(0)) 21 22 #define USB_PDPHY_EN_CONTROL_REG 0x46 23 #define CONTROL_ENABLE BIT(0) 24 25 #define USB_PDPHY_RX_STATUS_REG 0x4A 26 #define RX_FRAME_TYPE (BIT(0) | BIT(1) | BIT(2)) 27 28 #define USB_PDPHY_FRAME_FILTER_REG 0x4C 29 #define FRAME_FILTER_EN_HARD_RESET BIT(5) 30 #define FRAME_FILTER_EN_SOP BIT(0) 31 32 #define USB_PDPHY_TX_SIZE_REG 0x42 33 #define TX_SIZE_MASK 0xF 34 35 #define USB_PDPHY_TX_CONTROL_REG 0x44 36 #define TX_CONTROL_RETRY_COUNT(n) (((n) & 0x3) << 5) 37 #define TX_CONTROL_FRAME_TYPE(n) (((n) & 0x7) << 2) 38 #define TX_CONTROL_FRAME_TYPE_CABLE_RESET (0x1 << 2) 39 #define TX_CONTROL_SEND_SIGNAL BIT(1) 40 #define TX_CONTROL_SEND_MSG BIT(0) 41 42 #define USB_PDPHY_RX_SIZE_REG 0x48 43 44 #define USB_PDPHY_RX_ACKNOWLEDGE_REG 0x4B 45 #define RX_BUFFER_TOKEN BIT(0) 46 47 #define USB_PDPHY_BIST_MODE_REG 0x4E 48 #define BIST_MODE_MASK 0xF 49 #define BIST_ENABLE BIT(7) 50 #define PD_MSG_BIST 0x3 51 #define PD_BIST_TEST_DATA_MODE 0x8 52 53 #define USB_PDPHY_TX_BUFFER_HDR_REG 0x60 54 #define USB_PDPHY_TX_BUFFER_DATA_REG 0x62 55 56 #define USB_PDPHY_RX_BUFFER_REG 0x80 57 58 /* VDD regulator */ 59 #define VDD_PDPHY_VOL_MIN 2800000 /* uV */ 60 #define VDD_PDPHY_VOL_MAX 3300000 /* uV */ 61 #define VDD_PDPHY_HPM_LOAD 3000 /* uA */ 62 63 /* Message Spec Rev field */ 64 #define PD_MSG_HDR_REV(hdr) (((hdr) >> 6) & 3) 65 66 /* timers */ 67 #define RECEIVER_RESPONSE_TIME 15 /* tReceiverResponse */ 68 #define HARD_RESET_COMPLETE_TIME 5 /* tHardResetComplete */ 69 70 /* Interrupt numbers */ 71 #define PMIC_PDPHY_SIG_TX_IRQ 0x0 72 #define PMIC_PDPHY_SIG_RX_IRQ 0x1 73 #define PMIC_PDPHY_MSG_TX_IRQ 0x2 74 #define PMIC_PDPHY_MSG_RX_IRQ 0x3 75 #define PMIC_PDPHY_MSG_TX_FAIL_IRQ 0x4 76 #define PMIC_PDPHY_MSG_TX_DISCARD_IRQ 0x5 77 #define PMIC_PDPHY_MSG_RX_DISCARD_IRQ 0x6 78 #define PMIC_PDPHY_FR_SWAP_IRQ 0x7 79 80 /* Resources */ 81 #define PMIC_PDPHY_MAX_IRQS 0x08 82 83 struct pmic_typec_pdphy_irq_params { 84 int virq; 85 char *irq_name; 86 }; 87 88 struct pmic_typec_pdphy_resources { 89 unsigned int nr_irqs; 90 struct pmic_typec_pdphy_irq_params irq_params[PMIC_PDPHY_MAX_IRQS]; 91 }; 92 93 /* API */ 94 struct pmic_typec_pdphy; 95 96 struct pmic_typec_pdphy *qcom_pmic_typec_pdphy_alloc(struct device *dev); 97 98 int qcom_pmic_typec_pdphy_probe(struct platform_device *pdev, 99 struct pmic_typec_pdphy *pmic_typec_pdphy, 100 struct pmic_typec_pdphy_resources *res, 101 struct regmap *regmap, 102 u32 base); 103 104 int qcom_pmic_typec_pdphy_start(struct pmic_typec_pdphy *pmic_typec_pdphy, 105 struct tcpm_port *tcpm_port); 106 107 void qcom_pmic_typec_pdphy_stop(struct pmic_typec_pdphy *pmic_typec_pdphy); 108 109 int qcom_pmic_typec_pdphy_set_roles(struct pmic_typec_pdphy *pmic_typec_pdphy, 110 bool power_role_src, bool data_role_host); 111 112 int qcom_pmic_typec_pdphy_set_pd_rx(struct pmic_typec_pdphy *pmic_typec_pdphy, bool on); 113 114 int qcom_pmic_typec_pdphy_pd_transmit(struct pmic_typec_pdphy *pmic_typec_pdphy, 115 enum tcpm_transmit_type type, 116 const struct pd_message *msg, 117 unsigned int negotiated_rev); 118 119 #endif /* __QCOM_PMIC_TYPEC_PDPHY_H__ */ 120