1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2021 HiSilicon Ltd. */
3 
4 #ifndef HISI_ACC_VFIO_PCI_H
5 #define HISI_ACC_VFIO_PCI_H
6 
7 #include <linux/hisi_acc_qm.h>
8 
9 #define MB_POLL_PERIOD_US		10
10 #define MB_POLL_TIMEOUT_US		1000
11 #define QM_CACHE_WB_START		0x204
12 #define QM_CACHE_WB_DONE		0x208
13 #define QM_MB_CMD_PAUSE_QM		0xe
14 #define QM_ABNORMAL_INT_STATUS		0x100008
15 #define QM_IFC_INT_STATUS		0x0028
16 #define SEC_CORE_INT_STATUS		0x301008
17 #define HPRE_HAC_INT_STATUS		0x301800
18 #define HZIP_CORE_INT_STATUS		0x3010AC
19 
20 #define QM_VFT_CFG_RDY			0x10006c
21 #define QM_VFT_CFG_OP_WR		0x100058
22 #define QM_VFT_CFG_TYPE			0x10005c
23 #define QM_VFT_CFG			0x100060
24 #define QM_VFT_CFG_OP_ENABLE		0x100054
25 #define QM_VFT_CFG_DATA_L		0x100064
26 #define QM_VFT_CFG_DATA_H		0x100068
27 
28 #define ERROR_CHECK_TIMEOUT		100
29 #define CHECK_DELAY_TIME		100
30 
31 #define QM_SQC_VFT_BASE_SHIFT_V2	28
32 #define QM_SQC_VFT_BASE_MASK_V2		GENMASK(15, 0)
33 #define QM_SQC_VFT_NUM_SHIFT_V2		45
34 #define QM_SQC_VFT_NUM_MASK_V2		GENMASK(9, 0)
35 
36 /* RW regs */
37 #define QM_REGS_MAX_LEN		7
38 #define QM_REG_ADDR_OFFSET	0x0004
39 
40 #define QM_XQC_ADDR_OFFSET	32U
41 #define QM_VF_AEQ_INT_MASK	0x0004
42 #define QM_VF_EQ_INT_MASK	0x000c
43 #define QM_IFC_INT_SOURCE_V	0x0020
44 #define QM_IFC_INT_MASK		0x0024
45 #define QM_IFC_INT_SET_V	0x002c
46 #define QM_QUE_ISO_CFG_V	0x0030
47 #define QM_PAGE_SIZE		0x0034
48 
49 #define QM_EQC_DW0		0X8000
50 #define QM_AEQC_DW0		0X8020
51 
52 struct acc_vf_data {
53 #define QM_MATCH_SIZE offsetofend(struct acc_vf_data, qm_rsv_state)
54 	/* QM match information */
55 #define ACC_DEV_MAGIC	0XCDCDCDCDFEEDAACC
56 	u64 acc_magic;
57 	u32 qp_num;
58 	u32 dev_id;
59 	u32 que_iso_cfg;
60 	u32 qp_base;
61 	u32 vf_qm_state;
62 	/* QM reserved match information */
63 	u32 qm_rsv_state[3];
64 
65 	/* QM RW regs */
66 	u32 aeq_int_mask;
67 	u32 eq_int_mask;
68 	u32 ifc_int_source;
69 	u32 ifc_int_mask;
70 	u32 ifc_int_set;
71 	u32 page_size;
72 
73 	/* QM_EQC_DW has 7 regs */
74 	u32 qm_eqc_dw[7];
75 
76 	/* QM_AEQC_DW has 7 regs */
77 	u32 qm_aeqc_dw[7];
78 
79 	/* QM reserved 5 regs */
80 	u32 qm_rsv_regs[5];
81 	u32 padding;
82 	/* QM memory init information */
83 	u64 eqe_dma;
84 	u64 aeqe_dma;
85 	u64 sqc_dma;
86 	u64 cqc_dma;
87 };
88 
89 struct hisi_acc_vf_migration_file {
90 	struct file *filp;
91 	struct mutex lock;
92 	bool disabled;
93 
94 	struct acc_vf_data vf_data;
95 	size_t total_length;
96 };
97 
98 struct hisi_acc_vf_core_device {
99 	struct vfio_pci_core_device core_device;
100 	u8 deferred_reset:1;
101 	/* For migration state */
102 	struct mutex state_mutex;
103 	enum vfio_device_mig_state mig_state;
104 	struct pci_dev *pf_dev;
105 	struct pci_dev *vf_dev;
106 	struct hisi_qm *pf_qm;
107 	struct hisi_qm vf_qm;
108 	u32 vf_qm_state;
109 	int vf_id;
110 	/* For reset handler */
111 	spinlock_t reset_lock;
112 	struct hisi_acc_vf_migration_file *resuming_migf;
113 	struct hisi_acc_vf_migration_file *saving_migf;
114 };
115 #endif /* HISI_ACC_VFIO_PCI_H */
116