1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * OMAP5 HDMI CORE IP driver library 4 * 5 * Copyright (C) 2014 Texas Instruments Incorporated 6 * 7 * Authors: 8 * Yong Zhi 9 * Mythri pk 10 * Archit Taneja <archit@ti.com> 11 * Tomi Valkeinen <tomi.valkeinen@ti.com> 12 */ 13 14 #include <linux/kernel.h> 15 #include <linux/module.h> 16 #include <linux/err.h> 17 #include <linux/io.h> 18 #include <linux/delay.h> 19 #include <linux/string.h> 20 #include <linux/seq_file.h> 21 #include <drm/drm_edid.h> 22 #include <sound/asound.h> 23 #include <sound/asoundef.h> 24 25 #include "hdmi5_core.h" 26 27 /* only 24 bit color depth used for now */ 28 static const struct csc_table csc_table_deepcolor[] = { 29 /* HDMI_DEEP_COLOR_24BIT */ 30 [0] = { 7036, 0, 0, 32, 0, 7036, 0, 32, 0, 0, 7036, 32, }, 31 /* HDMI_DEEP_COLOR_30BIT */ 32 [1] = { 7015, 0, 0, 128, 0, 7015, 0, 128, 0, 0, 7015, 128, }, 33 /* HDMI_DEEP_COLOR_36BIT */ 34 [2] = { 7010, 0, 0, 512, 0, 7010, 0, 512, 0, 0, 7010, 512, }, 35 /* FULL RANGE */ 36 [3] = { 8192, 0, 0, 0, 0, 8192, 0, 0, 0, 0, 8192, 0, }, 37 }; 38 39 static void hdmi_core_ddc_init(struct hdmi_core_data *core) 40 { 41 void __iomem *base = core->base; 42 const unsigned long long iclk = 266000000; /* DSS L3 ICLK */ 43 const unsigned ss_scl_high = 4600; /* ns */ 44 const unsigned ss_scl_low = 5400; /* ns */ 45 const unsigned fs_scl_high = 600; /* ns */ 46 const unsigned fs_scl_low = 1300; /* ns */ 47 const unsigned sda_hold = 1000; /* ns */ 48 const unsigned sfr_div = 10; 49 unsigned long long sfr; 50 unsigned v; 51 52 sfr = iclk / sfr_div; /* SFR_DIV */ 53 sfr /= 1000; /* SFR clock in kHz */ 54 55 /* Reset */ 56 REG_FLD_MOD(base, HDMI_CORE_I2CM_SOFTRSTZ, 0, 0, 0); 57 if (hdmi_wait_for_bit_change(base, HDMI_CORE_I2CM_SOFTRSTZ, 58 0, 0, 1) != 1) 59 DSSERR("HDMI I2CM reset failed\n"); 60 61 /* Standard (0) or Fast (1) Mode */ 62 REG_FLD_MOD(base, HDMI_CORE_I2CM_DIV, 0, 3, 3); 63 64 /* Standard Mode SCL High counter */ 65 v = DIV_ROUND_UP_ULL(ss_scl_high * sfr, 1000000); 66 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_1_ADDR, 67 (v >> 8) & 0xff, 7, 0); 68 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_0_ADDR, 69 v & 0xff, 7, 0); 70 71 /* Standard Mode SCL Low counter */ 72 v = DIV_ROUND_UP_ULL(ss_scl_low * sfr, 1000000); 73 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_1_ADDR, 74 (v >> 8) & 0xff, 7, 0); 75 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_0_ADDR, 76 v & 0xff, 7, 0); 77 78 /* Fast Mode SCL High Counter */ 79 v = DIV_ROUND_UP_ULL(fs_scl_high * sfr, 1000000); 80 REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_HCNT_1_ADDR, 81 (v >> 8) & 0xff, 7, 0); 82 REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_HCNT_0_ADDR, 83 v & 0xff, 7, 0); 84 85 /* Fast Mode SCL Low Counter */ 86 v = DIV_ROUND_UP_ULL(fs_scl_low * sfr, 1000000); 87 REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_LCNT_1_ADDR, 88 (v >> 8) & 0xff, 7, 0); 89 REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_LCNT_0_ADDR, 90 v & 0xff, 7, 0); 91 92 /* SDA Hold Time */ 93 v = DIV_ROUND_UP_ULL(sda_hold * sfr, 1000000); 94 REG_FLD_MOD(base, HDMI_CORE_I2CM_SDA_HOLD_ADDR, v & 0xff, 7, 0); 95 96 REG_FLD_MOD(base, HDMI_CORE_I2CM_SLAVE, 0x50, 6, 0); 97 REG_FLD_MOD(base, HDMI_CORE_I2CM_SEGADDR, 0x30, 6, 0); 98 99 /* NACK_POL to high */ 100 REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 7, 7); 101 102 /* NACK_MASK to unmasked */ 103 REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x0, 6, 6); 104 105 /* ARBITRATION_POL to high */ 106 REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 3, 3); 107 108 /* ARBITRATION_MASK to unmasked */ 109 REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x0, 2, 2); 110 111 /* DONE_POL to high */ 112 REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x1, 3, 3); 113 114 /* DONE_MASK to unmasked */ 115 REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x0, 2, 2); 116 } 117 118 static void hdmi_core_ddc_uninit(struct hdmi_core_data *core) 119 { 120 void __iomem *base = core->base; 121 122 /* Mask I2C interrupts */ 123 REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 6, 6); 124 REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 2, 2); 125 REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x1, 2, 2); 126 } 127 128 static int hdmi_core_ddc_edid(struct hdmi_core_data *core, u8 *pedid, u8 ext) 129 { 130 void __iomem *base = core->base; 131 u8 cur_addr; 132 char checksum = 0; 133 const int retries = 1000; 134 u8 seg_ptr = ext / 2; 135 u8 edidbase = ((ext % 2) * 0x80); 136 137 REG_FLD_MOD(base, HDMI_CORE_I2CM_SEGPTR, seg_ptr, 7, 0); 138 139 /* 140 * TODO: We use polling here, although we probably should use proper 141 * interrupts. 142 */ 143 for (cur_addr = 0; cur_addr < 128; ++cur_addr) { 144 int i; 145 146 /* clear ERROR and DONE */ 147 REG_FLD_MOD(base, HDMI_CORE_IH_I2CM_STAT0, 0x3, 1, 0); 148 149 REG_FLD_MOD(base, HDMI_CORE_I2CM_ADDRESS, 150 edidbase + cur_addr, 7, 0); 151 152 if (seg_ptr) 153 REG_FLD_MOD(base, HDMI_CORE_I2CM_OPERATION, 1, 1, 1); 154 else 155 REG_FLD_MOD(base, HDMI_CORE_I2CM_OPERATION, 1, 0, 0); 156 157 for (i = 0; i < retries; ++i) { 158 u32 stat; 159 160 stat = REG_GET(base, HDMI_CORE_IH_I2CM_STAT0, 1, 0); 161 162 /* I2CM_ERROR */ 163 if (stat & 1) { 164 DSSERR("HDMI I2C Master Error\n"); 165 return -EIO; 166 } 167 168 /* I2CM_DONE */ 169 if (stat & (1 << 1)) 170 break; 171 172 usleep_range(250, 1000); 173 } 174 175 if (i == retries) { 176 DSSERR("HDMI I2C timeout reading EDID\n"); 177 return -EIO; 178 } 179 180 pedid[cur_addr] = REG_GET(base, HDMI_CORE_I2CM_DATAI, 7, 0); 181 checksum += pedid[cur_addr]; 182 } 183 184 return 0; 185 186 } 187 188 int hdmi5_read_edid(struct hdmi_core_data *core, u8 *edid, int len) 189 { 190 int r, n, i; 191 int max_ext_blocks = (len / 128) - 1; 192 193 if (len < 128) 194 return -EINVAL; 195 196 hdmi_core_ddc_init(core); 197 198 r = hdmi_core_ddc_edid(core, edid, 0); 199 if (r) 200 goto out; 201 202 n = edid[0x7e]; 203 204 if (n > max_ext_blocks) 205 n = max_ext_blocks; 206 207 for (i = 1; i <= n; i++) { 208 r = hdmi_core_ddc_edid(core, edid + i * EDID_LENGTH, i); 209 if (r) 210 goto out; 211 } 212 213 out: 214 hdmi_core_ddc_uninit(core); 215 216 return r ? r : len; 217 } 218 219 void hdmi5_core_dump(struct hdmi_core_data *core, struct seq_file *s) 220 { 221 222 #define DUMPCORE(r) seq_printf(s, "%-35s %08x\n", #r,\ 223 hdmi_read_reg(core->base, r)) 224 225 DUMPCORE(HDMI_CORE_FC_INVIDCONF); 226 DUMPCORE(HDMI_CORE_FC_INHACTIV0); 227 DUMPCORE(HDMI_CORE_FC_INHACTIV1); 228 DUMPCORE(HDMI_CORE_FC_INHBLANK0); 229 DUMPCORE(HDMI_CORE_FC_INHBLANK1); 230 DUMPCORE(HDMI_CORE_FC_INVACTIV0); 231 DUMPCORE(HDMI_CORE_FC_INVACTIV1); 232 DUMPCORE(HDMI_CORE_FC_INVBLANK); 233 DUMPCORE(HDMI_CORE_FC_HSYNCINDELAY0); 234 DUMPCORE(HDMI_CORE_FC_HSYNCINDELAY1); 235 DUMPCORE(HDMI_CORE_FC_HSYNCINWIDTH0); 236 DUMPCORE(HDMI_CORE_FC_HSYNCINWIDTH1); 237 DUMPCORE(HDMI_CORE_FC_VSYNCINDELAY); 238 DUMPCORE(HDMI_CORE_FC_VSYNCINWIDTH); 239 DUMPCORE(HDMI_CORE_FC_CTRLDUR); 240 DUMPCORE(HDMI_CORE_FC_EXCTRLDUR); 241 DUMPCORE(HDMI_CORE_FC_EXCTRLSPAC); 242 DUMPCORE(HDMI_CORE_FC_CH0PREAM); 243 DUMPCORE(HDMI_CORE_FC_CH1PREAM); 244 DUMPCORE(HDMI_CORE_FC_CH2PREAM); 245 DUMPCORE(HDMI_CORE_FC_AVICONF0); 246 DUMPCORE(HDMI_CORE_FC_AVICONF1); 247 DUMPCORE(HDMI_CORE_FC_AVICONF2); 248 DUMPCORE(HDMI_CORE_FC_AVIVID); 249 DUMPCORE(HDMI_CORE_FC_PRCONF); 250 251 DUMPCORE(HDMI_CORE_MC_CLKDIS); 252 DUMPCORE(HDMI_CORE_MC_SWRSTZREQ); 253 DUMPCORE(HDMI_CORE_MC_FLOWCTRL); 254 DUMPCORE(HDMI_CORE_MC_PHYRSTZ); 255 DUMPCORE(HDMI_CORE_MC_LOCKONCLOCK); 256 257 DUMPCORE(HDMI_CORE_I2CM_SLAVE); 258 DUMPCORE(HDMI_CORE_I2CM_ADDRESS); 259 DUMPCORE(HDMI_CORE_I2CM_DATAO); 260 DUMPCORE(HDMI_CORE_I2CM_DATAI); 261 DUMPCORE(HDMI_CORE_I2CM_OPERATION); 262 DUMPCORE(HDMI_CORE_I2CM_INT); 263 DUMPCORE(HDMI_CORE_I2CM_CTLINT); 264 DUMPCORE(HDMI_CORE_I2CM_DIV); 265 DUMPCORE(HDMI_CORE_I2CM_SEGADDR); 266 DUMPCORE(HDMI_CORE_I2CM_SOFTRSTZ); 267 DUMPCORE(HDMI_CORE_I2CM_SEGPTR); 268 DUMPCORE(HDMI_CORE_I2CM_SS_SCL_HCNT_1_ADDR); 269 DUMPCORE(HDMI_CORE_I2CM_SS_SCL_HCNT_0_ADDR); 270 DUMPCORE(HDMI_CORE_I2CM_SS_SCL_LCNT_1_ADDR); 271 DUMPCORE(HDMI_CORE_I2CM_SS_SCL_LCNT_0_ADDR); 272 DUMPCORE(HDMI_CORE_I2CM_FS_SCL_HCNT_1_ADDR); 273 DUMPCORE(HDMI_CORE_I2CM_FS_SCL_HCNT_0_ADDR); 274 DUMPCORE(HDMI_CORE_I2CM_FS_SCL_LCNT_1_ADDR); 275 DUMPCORE(HDMI_CORE_I2CM_FS_SCL_LCNT_0_ADDR); 276 DUMPCORE(HDMI_CORE_I2CM_SDA_HOLD_ADDR); 277 } 278 279 static void hdmi_core_init(struct hdmi_core_vid_config *video_cfg, 280 struct hdmi_config *cfg) 281 { 282 DSSDBG("hdmi_core_init\n"); 283 284 /* video core */ 285 video_cfg->data_enable_pol = 1; /* It is always 1*/ 286 video_cfg->v_fc_config.timings.hsync_level = cfg->timings.hsync_level; 287 video_cfg->v_fc_config.timings.x_res = cfg->timings.x_res; 288 video_cfg->v_fc_config.timings.hsw = cfg->timings.hsw - 1; 289 video_cfg->v_fc_config.timings.hbp = cfg->timings.hbp; 290 video_cfg->v_fc_config.timings.hfp = cfg->timings.hfp; 291 video_cfg->hblank = cfg->timings.hfp + 292 cfg->timings.hbp + cfg->timings.hsw - 1; 293 video_cfg->v_fc_config.timings.vsync_level = cfg->timings.vsync_level; 294 video_cfg->v_fc_config.timings.y_res = cfg->timings.y_res; 295 video_cfg->v_fc_config.timings.vsw = cfg->timings.vsw; 296 video_cfg->v_fc_config.timings.vfp = cfg->timings.vfp; 297 video_cfg->v_fc_config.timings.vbp = cfg->timings.vbp; 298 video_cfg->vblank_osc = 0; /* Always 0 - need to confirm */ 299 video_cfg->vblank = cfg->timings.vsw + 300 cfg->timings.vfp + cfg->timings.vbp; 301 video_cfg->v_fc_config.hdmi_dvi_mode = cfg->hdmi_dvi_mode; 302 video_cfg->v_fc_config.timings.interlace = cfg->timings.interlace; 303 } 304 305 /* DSS_HDMI_CORE_VIDEO_CONFIG */ 306 static void hdmi_core_video_config(struct hdmi_core_data *core, 307 struct hdmi_core_vid_config *cfg) 308 { 309 void __iomem *base = core->base; 310 unsigned char r = 0; 311 bool vsync_pol, hsync_pol; 312 313 vsync_pol = 314 cfg->v_fc_config.timings.vsync_level == OMAPDSS_SIG_ACTIVE_HIGH; 315 hsync_pol = 316 cfg->v_fc_config.timings.hsync_level == OMAPDSS_SIG_ACTIVE_HIGH; 317 318 /* Set hsync, vsync and data-enable polarity */ 319 r = hdmi_read_reg(base, HDMI_CORE_FC_INVIDCONF); 320 r = FLD_MOD(r, vsync_pol, 6, 6); 321 r = FLD_MOD(r, hsync_pol, 5, 5); 322 r = FLD_MOD(r, cfg->data_enable_pol, 4, 4); 323 r = FLD_MOD(r, cfg->vblank_osc, 1, 1); 324 r = FLD_MOD(r, cfg->v_fc_config.timings.interlace, 0, 0); 325 hdmi_write_reg(base, HDMI_CORE_FC_INVIDCONF, r); 326 327 /* set x resolution */ 328 REG_FLD_MOD(base, HDMI_CORE_FC_INHACTIV1, 329 cfg->v_fc_config.timings.x_res >> 8, 4, 0); 330 REG_FLD_MOD(base, HDMI_CORE_FC_INHACTIV0, 331 cfg->v_fc_config.timings.x_res & 0xFF, 7, 0); 332 333 /* set y resolution */ 334 REG_FLD_MOD(base, HDMI_CORE_FC_INVACTIV1, 335 cfg->v_fc_config.timings.y_res >> 8, 4, 0); 336 REG_FLD_MOD(base, HDMI_CORE_FC_INVACTIV0, 337 cfg->v_fc_config.timings.y_res & 0xFF, 7, 0); 338 339 /* set horizontal blanking pixels */ 340 REG_FLD_MOD(base, HDMI_CORE_FC_INHBLANK1, cfg->hblank >> 8, 4, 0); 341 REG_FLD_MOD(base, HDMI_CORE_FC_INHBLANK0, cfg->hblank & 0xFF, 7, 0); 342 343 /* set vertial blanking pixels */ 344 REG_FLD_MOD(base, HDMI_CORE_FC_INVBLANK, cfg->vblank, 7, 0); 345 346 /* set horizontal sync offset */ 347 REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINDELAY1, 348 cfg->v_fc_config.timings.hfp >> 8, 4, 0); 349 REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINDELAY0, 350 cfg->v_fc_config.timings.hfp & 0xFF, 7, 0); 351 352 /* set vertical sync offset */ 353 REG_FLD_MOD(base, HDMI_CORE_FC_VSYNCINDELAY, 354 cfg->v_fc_config.timings.vfp, 7, 0); 355 356 /* set horizontal sync pulse width */ 357 REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINWIDTH1, 358 (cfg->v_fc_config.timings.hsw >> 8), 1, 0); 359 REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINWIDTH0, 360 cfg->v_fc_config.timings.hsw & 0xFF, 7, 0); 361 362 /* set vertical sync pulse width */ 363 REG_FLD_MOD(base, HDMI_CORE_FC_VSYNCINWIDTH, 364 cfg->v_fc_config.timings.vsw, 5, 0); 365 366 /* select DVI mode */ 367 REG_FLD_MOD(base, HDMI_CORE_FC_INVIDCONF, 368 cfg->v_fc_config.hdmi_dvi_mode, 3, 3); 369 } 370 371 static void hdmi_core_config_video_packetizer(struct hdmi_core_data *core) 372 { 373 void __iomem *base = core->base; 374 int clr_depth = 0; /* 24 bit color depth */ 375 376 /* COLOR_DEPTH */ 377 REG_FLD_MOD(base, HDMI_CORE_VP_PR_CD, clr_depth, 7, 4); 378 /* BYPASS_EN */ 379 REG_FLD_MOD(base, HDMI_CORE_VP_CONF, clr_depth ? 0 : 1, 6, 6); 380 /* PP_EN */ 381 REG_FLD_MOD(base, HDMI_CORE_VP_CONF, clr_depth ? 1 : 0, 5, 5); 382 /* YCC422_EN */ 383 REG_FLD_MOD(base, HDMI_CORE_VP_CONF, 0, 3, 3); 384 /* PP_STUFFING */ 385 REG_FLD_MOD(base, HDMI_CORE_VP_STUFF, clr_depth ? 1 : 0, 1, 1); 386 /* YCC422_STUFFING */ 387 REG_FLD_MOD(base, HDMI_CORE_VP_STUFF, 1, 2, 2); 388 /* OUTPUT_SELECTOR */ 389 REG_FLD_MOD(base, HDMI_CORE_VP_CONF, clr_depth ? 0 : 2, 1, 0); 390 } 391 392 static void hdmi_core_config_csc(struct hdmi_core_data *core) 393 { 394 int clr_depth = 0; /* 24 bit color depth */ 395 396 /* CSC_COLORDEPTH */ 397 REG_FLD_MOD(core->base, HDMI_CORE_CSC_SCALE, clr_depth, 7, 4); 398 } 399 400 static void hdmi_core_config_video_sampler(struct hdmi_core_data *core) 401 { 402 int video_mapping = 1; /* for 24 bit color depth */ 403 404 /* VIDEO_MAPPING */ 405 REG_FLD_MOD(core->base, HDMI_CORE_TX_INVID0, video_mapping, 4, 0); 406 } 407 408 static void hdmi_core_write_avi_infoframe(struct hdmi_core_data *core, 409 struct hdmi_avi_infoframe *frame) 410 { 411 void __iomem *base = core->base; 412 u8 data[HDMI_INFOFRAME_SIZE(AVI)]; 413 u8 *ptr; 414 unsigned y, a, b, s; 415 unsigned c, m, r; 416 unsigned itc, ec, q, sc; 417 unsigned vic; 418 unsigned yq, cn, pr; 419 420 hdmi_avi_infoframe_pack(frame, data, sizeof(data)); 421 422 print_hex_dump_debug("AVI: ", DUMP_PREFIX_NONE, 16, 1, data, 423 HDMI_INFOFRAME_SIZE(AVI), false); 424 425 ptr = data + HDMI_INFOFRAME_HEADER_SIZE; 426 427 y = (ptr[0] >> 5) & 0x3; 428 a = (ptr[0] >> 4) & 0x1; 429 b = (ptr[0] >> 2) & 0x3; 430 s = (ptr[0] >> 0) & 0x3; 431 432 c = (ptr[1] >> 6) & 0x3; 433 m = (ptr[1] >> 4) & 0x3; 434 r = (ptr[1] >> 0) & 0xf; 435 436 itc = (ptr[2] >> 7) & 0x1; 437 ec = (ptr[2] >> 4) & 0x7; 438 q = (ptr[2] >> 2) & 0x3; 439 sc = (ptr[2] >> 0) & 0x3; 440 441 vic = ptr[3]; 442 443 yq = (ptr[4] >> 6) & 0x3; 444 cn = (ptr[4] >> 4) & 0x3; 445 pr = (ptr[4] >> 0) & 0xf; 446 447 hdmi_write_reg(base, HDMI_CORE_FC_AVICONF0, 448 (a << 6) | (s << 4) | (b << 2) | (y << 0)); 449 450 hdmi_write_reg(base, HDMI_CORE_FC_AVICONF1, 451 (c << 6) | (m << 4) | (r << 0)); 452 453 hdmi_write_reg(base, HDMI_CORE_FC_AVICONF2, 454 (itc << 7) | (ec << 4) | (q << 2) | (sc << 0)); 455 456 hdmi_write_reg(base, HDMI_CORE_FC_AVIVID, vic); 457 458 hdmi_write_reg(base, HDMI_CORE_FC_AVICONF3, 459 (yq << 2) | (cn << 0)); 460 461 REG_FLD_MOD(base, HDMI_CORE_FC_PRCONF, pr, 3, 0); 462 } 463 464 static void hdmi_core_csc_config(struct hdmi_core_data *core, 465 struct csc_table csc_coeff) 466 { 467 void __iomem *base = core->base; 468 469 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A1_MSB, csc_coeff.a1 >> 8 , 6, 0); 470 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A1_LSB, csc_coeff.a1, 7, 0); 471 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A2_MSB, csc_coeff.a2 >> 8, 6, 0); 472 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A2_LSB, csc_coeff.a2, 7, 0); 473 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A3_MSB, csc_coeff.a3 >> 8, 6, 0); 474 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A3_LSB, csc_coeff.a3, 7, 0); 475 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A4_MSB, csc_coeff.a4 >> 8, 6, 0); 476 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A4_LSB, csc_coeff.a4, 7, 0); 477 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B1_MSB, csc_coeff.b1 >> 8, 6, 0); 478 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B1_LSB, csc_coeff.b1, 7, 0); 479 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B2_MSB, csc_coeff.b2 >> 8, 6, 0); 480 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B2_LSB, csc_coeff.b2, 7, 0); 481 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B3_MSB, csc_coeff.b3 >> 8, 6, 0); 482 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B3_LSB, csc_coeff.b3, 7, 0); 483 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B4_MSB, csc_coeff.b4 >> 8, 6, 0); 484 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B4_LSB, csc_coeff.b4, 7, 0); 485 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C1_MSB, csc_coeff.c1 >> 8, 6, 0); 486 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C1_LSB, csc_coeff.c1, 7, 0); 487 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C2_MSB, csc_coeff.c2 >> 8, 6, 0); 488 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C2_LSB, csc_coeff.c2, 7, 0); 489 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C3_MSB, csc_coeff.c3 >> 8, 6, 0); 490 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C3_LSB, csc_coeff.c3, 7, 0); 491 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C4_MSB, csc_coeff.c4 >> 8, 6, 0); 492 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C4_LSB, csc_coeff.c4, 7, 0); 493 494 REG_FLD_MOD(base, HDMI_CORE_MC_FLOWCTRL, 0x1, 0, 0); 495 } 496 497 static void hdmi_core_configure_range(struct hdmi_core_data *core) 498 { 499 struct csc_table csc_coeff = { 0 }; 500 501 /* support limited range with 24 bit color depth for now */ 502 csc_coeff = csc_table_deepcolor[0]; 503 504 hdmi_core_csc_config(core, csc_coeff); 505 } 506 507 static void hdmi_core_enable_video_path(struct hdmi_core_data *core) 508 { 509 void __iomem *base = core->base; 510 511 DSSDBG("hdmi_core_enable_video_path\n"); 512 513 REG_FLD_MOD(base, HDMI_CORE_FC_CTRLDUR, 0x0C, 7, 0); 514 REG_FLD_MOD(base, HDMI_CORE_FC_EXCTRLDUR, 0x20, 7, 0); 515 REG_FLD_MOD(base, HDMI_CORE_FC_EXCTRLSPAC, 0x01, 7, 0); 516 REG_FLD_MOD(base, HDMI_CORE_FC_CH0PREAM, 0x0B, 7, 0); 517 REG_FLD_MOD(base, HDMI_CORE_FC_CH1PREAM, 0x16, 5, 0); 518 REG_FLD_MOD(base, HDMI_CORE_FC_CH2PREAM, 0x21, 5, 0); 519 REG_FLD_MOD(base, HDMI_CORE_MC_CLKDIS, 0x00, 0, 0); 520 REG_FLD_MOD(base, HDMI_CORE_MC_CLKDIS, 0x00, 1, 1); 521 } 522 523 static void hdmi_core_mask_interrupts(struct hdmi_core_data *core) 524 { 525 void __iomem *base = core->base; 526 527 /* Master IRQ mask */ 528 REG_FLD_MOD(base, HDMI_CORE_IH_MUTE, 0x3, 1, 0); 529 530 /* Mask all the interrupts in HDMI core */ 531 532 REG_FLD_MOD(base, HDMI_CORE_VP_MASK, 0xff, 7, 0); 533 REG_FLD_MOD(base, HDMI_CORE_FC_MASK0, 0xe7, 7, 0); 534 REG_FLD_MOD(base, HDMI_CORE_FC_MASK1, 0xfb, 7, 0); 535 REG_FLD_MOD(base, HDMI_CORE_FC_MASK2, 0x3, 1, 0); 536 537 REG_FLD_MOD(base, HDMI_CORE_AUD_INT, 0x3, 3, 2); 538 REG_FLD_MOD(base, HDMI_CORE_AUD_GP_MASK, 0x3, 1, 0); 539 540 REG_FLD_MOD(base, HDMI_CORE_CEC_MASK, 0x7f, 6, 0); 541 542 REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 6, 6); 543 REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 2, 2); 544 REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x1, 2, 2); 545 546 REG_FLD_MOD(base, HDMI_CORE_PHY_MASK0, 0xf3, 7, 0); 547 548 REG_FLD_MOD(base, HDMI_CORE_IH_PHY_STAT0, 0xff, 7, 0); 549 550 /* Clear all the current interrupt bits */ 551 552 REG_FLD_MOD(base, HDMI_CORE_IH_VP_STAT0, 0xff, 7, 0); 553 REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT0, 0xe7, 7, 0); 554 REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT1, 0xfb, 7, 0); 555 REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT2, 0x3, 1, 0); 556 557 REG_FLD_MOD(base, HDMI_CORE_IH_AS_STAT0, 0x7, 2, 0); 558 559 REG_FLD_MOD(base, HDMI_CORE_IH_CEC_STAT0, 0x7f, 6, 0); 560 561 REG_FLD_MOD(base, HDMI_CORE_IH_I2CM_STAT0, 0x3, 1, 0); 562 563 REG_FLD_MOD(base, HDMI_CORE_IH_PHY_STAT0, 0xff, 7, 0); 564 } 565 566 static void hdmi_core_enable_interrupts(struct hdmi_core_data *core) 567 { 568 /* Unmute interrupts */ 569 REG_FLD_MOD(core->base, HDMI_CORE_IH_MUTE, 0x0, 1, 0); 570 } 571 572 int hdmi5_core_handle_irqs(struct hdmi_core_data *core) 573 { 574 void __iomem *base = core->base; 575 576 REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT0, 0xff, 7, 0); 577 REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT1, 0xff, 7, 0); 578 REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT2, 0xff, 7, 0); 579 REG_FLD_MOD(base, HDMI_CORE_IH_AS_STAT0, 0xff, 7, 0); 580 REG_FLD_MOD(base, HDMI_CORE_IH_PHY_STAT0, 0xff, 7, 0); 581 REG_FLD_MOD(base, HDMI_CORE_IH_I2CM_STAT0, 0xff, 7, 0); 582 REG_FLD_MOD(base, HDMI_CORE_IH_CEC_STAT0, 0xff, 7, 0); 583 REG_FLD_MOD(base, HDMI_CORE_IH_VP_STAT0, 0xff, 7, 0); 584 REG_FLD_MOD(base, HDMI_CORE_IH_I2CMPHY_STAT0, 0xff, 7, 0); 585 586 return 0; 587 } 588 589 void hdmi5_configure(struct hdmi_core_data *core, struct hdmi_wp_data *wp, 590 struct hdmi_config *cfg) 591 { 592 struct omap_video_timings video_timing; 593 struct hdmi_video_format video_format; 594 struct hdmi_core_vid_config v_core_cfg; 595 596 hdmi_core_mask_interrupts(core); 597 598 hdmi_core_init(&v_core_cfg, cfg); 599 600 hdmi_wp_init_vid_fmt_timings(&video_format, &video_timing, cfg); 601 602 hdmi_wp_video_config_timing(wp, &video_timing); 603 604 /* video config */ 605 video_format.packing_mode = HDMI_PACK_24b_RGB_YUV444_YUV422; 606 607 hdmi_wp_video_config_format(wp, &video_format); 608 609 hdmi_wp_video_config_interface(wp, &video_timing); 610 611 /* support limited range with 24 bit color depth for now */ 612 hdmi_core_configure_range(core); 613 cfg->infoframe.quantization_range = HDMI_QUANTIZATION_RANGE_LIMITED; 614 615 /* 616 * configure core video part, set software reset in the core 617 */ 618 v_core_cfg.packet_mode = HDMI_PACKETMODE24BITPERPIXEL; 619 620 hdmi_core_video_config(core, &v_core_cfg); 621 622 hdmi_core_config_video_packetizer(core); 623 hdmi_core_config_csc(core); 624 hdmi_core_config_video_sampler(core); 625 626 if (cfg->hdmi_dvi_mode == HDMI_HDMI) 627 hdmi_core_write_avi_infoframe(core, &cfg->infoframe); 628 629 hdmi_core_enable_video_path(core); 630 631 hdmi_core_enable_interrupts(core); 632 } 633 634 static void hdmi5_core_audio_config(struct hdmi_core_data *core, 635 struct hdmi_core_audio_config *cfg) 636 { 637 void __iomem *base = core->base; 638 u8 val; 639 640 /* Mute audio before configuring */ 641 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 0xf, 7, 4); 642 643 /* Set the N parameter */ 644 REG_FLD_MOD(base, HDMI_CORE_AUD_N1, cfg->n, 7, 0); 645 REG_FLD_MOD(base, HDMI_CORE_AUD_N2, cfg->n >> 8, 7, 0); 646 REG_FLD_MOD(base, HDMI_CORE_AUD_N3, cfg->n >> 16, 3, 0); 647 648 /* 649 * CTS manual mode. Automatic mode is not supported when using audio 650 * parallel interface. 651 */ 652 REG_FLD_MOD(base, HDMI_CORE_AUD_CTS3, 1, 4, 4); 653 REG_FLD_MOD(base, HDMI_CORE_AUD_CTS1, cfg->cts, 7, 0); 654 REG_FLD_MOD(base, HDMI_CORE_AUD_CTS2, cfg->cts >> 8, 7, 0); 655 REG_FLD_MOD(base, HDMI_CORE_AUD_CTS3, cfg->cts >> 16, 3, 0); 656 657 /* Layout of Audio Sample Packets: 2-channel or multichannels */ 658 if (cfg->layout == HDMI_AUDIO_LAYOUT_2CH) 659 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 0, 0, 0); 660 else 661 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 1, 0, 0); 662 663 /* Configure IEC-609580 Validity bits */ 664 /* Channel 0 is valid */ 665 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, 0, 0, 0); 666 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, 0, 4, 4); 667 668 if (cfg->layout == HDMI_AUDIO_LAYOUT_2CH) 669 val = 1; 670 else 671 val = 0; 672 673 /* Channels 1, 2 setting */ 674 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 1, 1); 675 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 5, 5); 676 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 2, 2); 677 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 6, 6); 678 /* Channel 3 setting */ 679 if (cfg->layout == HDMI_AUDIO_LAYOUT_6CH) 680 val = 1; 681 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 3, 3); 682 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 7, 7); 683 684 /* Configure IEC-60958 User bits */ 685 /* TODO: should be set by user. */ 686 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSU, 0, 7, 0); 687 688 /* Configure IEC-60958 Channel Status word */ 689 /* CGMSA */ 690 val = cfg->iec60958_cfg->status[5] & IEC958_AES5_CON_CGMSA; 691 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(0), val, 5, 4); 692 693 /* Copyright */ 694 val = (cfg->iec60958_cfg->status[0] & 695 IEC958_AES0_CON_NOT_COPYRIGHT) >> 2; 696 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(0), val, 0, 0); 697 698 /* Category */ 699 hdmi_write_reg(base, HDMI_CORE_FC_AUDSCHNLS(1), 700 cfg->iec60958_cfg->status[1]); 701 702 /* PCM audio mode */ 703 val = (cfg->iec60958_cfg->status[0] & IEC958_AES0_CON_MODE) >> 6; 704 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(2), val, 6, 4); 705 706 /* Source number */ 707 val = cfg->iec60958_cfg->status[2] & IEC958_AES2_CON_SOURCE; 708 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(2), val, 3, 0); 709 710 /* Channel number right 0 */ 711 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(3), 2, 3, 0); 712 /* Channel number right 1*/ 713 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(3), 4, 7, 4); 714 /* Channel number right 2 */ 715 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(4), 6, 3, 0); 716 /* Channel number right 3*/ 717 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(4), 8, 7, 4); 718 /* Channel number left 0 */ 719 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(5), 1, 3, 0); 720 /* Channel number left 1*/ 721 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(5), 3, 7, 4); 722 /* Channel number left 2 */ 723 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(6), 5, 3, 0); 724 /* Channel number left 3*/ 725 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(6), 7, 7, 4); 726 727 /* Clock accuracy and sample rate */ 728 hdmi_write_reg(base, HDMI_CORE_FC_AUDSCHNLS(7), 729 cfg->iec60958_cfg->status[3]); 730 731 /* Original sample rate and word length */ 732 hdmi_write_reg(base, HDMI_CORE_FC_AUDSCHNLS(8), 733 cfg->iec60958_cfg->status[4]); 734 735 /* Enable FIFO empty and full interrupts */ 736 REG_FLD_MOD(base, HDMI_CORE_AUD_INT, 3, 3, 2); 737 738 /* Configure GPA */ 739 /* select HBR/SPDIF interfaces */ 740 if (cfg->layout == HDMI_AUDIO_LAYOUT_2CH) { 741 /* select HBR/SPDIF interfaces */ 742 REG_FLD_MOD(base, HDMI_CORE_AUD_CONF0, 0, 5, 5); 743 /* enable two channels in GPA */ 744 REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF1, 3, 7, 0); 745 } else if (cfg->layout == HDMI_AUDIO_LAYOUT_6CH) { 746 /* select HBR/SPDIF interfaces */ 747 REG_FLD_MOD(base, HDMI_CORE_AUD_CONF0, 0, 5, 5); 748 /* enable six channels in GPA */ 749 REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF1, 0x3F, 7, 0); 750 } else { 751 /* select HBR/SPDIF interfaces */ 752 REG_FLD_MOD(base, HDMI_CORE_AUD_CONF0, 0, 5, 5); 753 /* enable eight channels in GPA */ 754 REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF1, 0xFF, 7, 0); 755 } 756 757 /* disable HBR */ 758 REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF2, 0, 0, 0); 759 /* enable PCUV */ 760 REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF2, 1, 1, 1); 761 /* enable GPA FIFO full and empty mask */ 762 REG_FLD_MOD(base, HDMI_CORE_AUD_GP_MASK, 3, 1, 0); 763 /* set polarity of GPA FIFO empty interrupts */ 764 REG_FLD_MOD(base, HDMI_CORE_AUD_GP_POL, 1, 0, 0); 765 766 /* unmute audio */ 767 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 0, 7, 4); 768 } 769 770 static void hdmi5_core_audio_infoframe_cfg(struct hdmi_core_data *core, 771 struct snd_cea_861_aud_if *info_aud) 772 { 773 void __iomem *base = core->base; 774 775 /* channel count and coding type fields in AUDICONF0 are swapped */ 776 hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF0, 777 (info_aud->db1_ct_cc & CEA861_AUDIO_INFOFRAME_DB1CC) << 4 | 778 (info_aud->db1_ct_cc & CEA861_AUDIO_INFOFRAME_DB1CT) >> 4); 779 780 hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF1, info_aud->db2_sf_ss); 781 hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF2, info_aud->db4_ca); 782 hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF3, 783 (info_aud->db5_dminh_lsv & CEA861_AUDIO_INFOFRAME_DB5_DM_INH) >> 3 | 784 (info_aud->db5_dminh_lsv & CEA861_AUDIO_INFOFRAME_DB5_LSV)); 785 } 786 787 int hdmi5_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp, 788 struct omap_dss_audio *audio, u32 pclk) 789 { 790 struct hdmi_audio_format audio_format; 791 struct hdmi_audio_dma audio_dma; 792 struct hdmi_core_audio_config core_cfg; 793 int n, cts, channel_count; 794 unsigned int fs_nr; 795 bool word_length_16b = false; 796 797 if (!audio || !audio->iec || !audio->cea || !core) 798 return -EINVAL; 799 800 core_cfg.iec60958_cfg = audio->iec; 801 802 if (!(audio->iec->status[4] & IEC958_AES4_CON_MAX_WORDLEN_24) && 803 (audio->iec->status[4] & IEC958_AES4_CON_WORDLEN_20_16)) 804 word_length_16b = true; 805 806 /* only 16-bit word length supported atm */ 807 if (!word_length_16b) 808 return -EINVAL; 809 810 switch (audio->iec->status[3] & IEC958_AES3_CON_FS) { 811 case IEC958_AES3_CON_FS_32000: 812 fs_nr = 32000; 813 break; 814 case IEC958_AES3_CON_FS_44100: 815 fs_nr = 44100; 816 break; 817 case IEC958_AES3_CON_FS_48000: 818 fs_nr = 48000; 819 break; 820 case IEC958_AES3_CON_FS_88200: 821 fs_nr = 88200; 822 break; 823 case IEC958_AES3_CON_FS_96000: 824 fs_nr = 96000; 825 break; 826 case IEC958_AES3_CON_FS_176400: 827 fs_nr = 176400; 828 break; 829 case IEC958_AES3_CON_FS_192000: 830 fs_nr = 192000; 831 break; 832 default: 833 return -EINVAL; 834 } 835 836 hdmi_compute_acr(pclk, fs_nr, &n, &cts); 837 core_cfg.n = n; 838 core_cfg.cts = cts; 839 840 /* Audio channels settings */ 841 channel_count = (audio->cea->db1_ct_cc & CEA861_AUDIO_INFOFRAME_DB1CC) 842 + 1; 843 844 if (channel_count == 2) 845 core_cfg.layout = HDMI_AUDIO_LAYOUT_2CH; 846 else if (channel_count == 6) 847 core_cfg.layout = HDMI_AUDIO_LAYOUT_6CH; 848 else 849 core_cfg.layout = HDMI_AUDIO_LAYOUT_8CH; 850 851 /* DMA settings */ 852 if (word_length_16b) 853 audio_dma.transfer_size = 0x10; 854 else 855 audio_dma.transfer_size = 0x20; 856 audio_dma.block_size = 0xC0; 857 audio_dma.mode = HDMI_AUDIO_TRANSF_DMA; 858 audio_dma.fifo_threshold = 0x20; /* in number of samples */ 859 860 /* audio FIFO format settings for 16-bit samples*/ 861 audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_TWOSAMPLES; 862 audio_format.sample_size = HDMI_AUDIO_SAMPLE_16BITS; 863 audio_format.justification = HDMI_AUDIO_JUSTIFY_LEFT; 864 audio_format.sample_order = HDMI_AUDIO_SAMPLE_LEFT_FIRST; 865 866 /* only LPCM atm */ 867 audio_format.type = HDMI_AUDIO_TYPE_LPCM; 868 869 /* only allowed option */ 870 audio_format.sample_order = HDMI_AUDIO_SAMPLE_LEFT_FIRST; 871 872 /* disable start/stop signals of IEC 60958 blocks */ 873 audio_format.en_sig_blk_strt_end = HDMI_AUDIO_BLOCK_SIG_STARTEND_ON; 874 875 /* configure DMA and audio FIFO format*/ 876 hdmi_wp_audio_config_dma(wp, &audio_dma); 877 hdmi_wp_audio_config_format(wp, &audio_format); 878 879 /* configure the core */ 880 hdmi5_core_audio_config(core, &core_cfg); 881 882 /* configure CEA 861 audio infoframe */ 883 hdmi5_core_audio_infoframe_cfg(core, audio->cea); 884 885 return 0; 886 } 887 888 int hdmi5_core_init(struct platform_device *pdev, struct hdmi_core_data *core) 889 { 890 core->base = devm_platform_ioremap_resource_byname(pdev, "core"); 891 if (IS_ERR(core->base)) { 892 DSSERR("can't ioremap HDMI core\n"); 893 return PTR_ERR(core->base); 894 } 895 896 return 0; 897 } 898