1f7018c21STomi Valkeinen /***************************************************************************\
2f7018c21STomi Valkeinen |* *|
3f7018c21STomi Valkeinen |* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *|
4f7018c21STomi Valkeinen |* *|
5f7018c21STomi Valkeinen |* NOTICE TO USER: The source code is copyrighted under U.S. and *|
6f7018c21STomi Valkeinen |* international laws. Users and possessors of this source code are *|
7f7018c21STomi Valkeinen |* hereby granted a nonexclusive, royalty-free copyright license to *|
8f7018c21STomi Valkeinen |* use this code in individual and commercial software. *|
9f7018c21STomi Valkeinen |* *|
10f7018c21STomi Valkeinen |* Any use of this source code must include, in the user documenta- *|
11f7018c21STomi Valkeinen |* tion and internal comments to the code, notices to the end user *|
12f7018c21STomi Valkeinen |* as follows: *|
13f7018c21STomi Valkeinen |* *|
14f7018c21STomi Valkeinen |* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *|
15f7018c21STomi Valkeinen |* *|
16f7018c21STomi Valkeinen |* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *|
17f7018c21STomi Valkeinen |* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *|
18f7018c21STomi Valkeinen |* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
19f7018c21STomi Valkeinen |* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *|
20f7018c21STomi Valkeinen |* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
21f7018c21STomi Valkeinen |* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *|
22f7018c21STomi Valkeinen |* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
23f7018c21STomi Valkeinen |* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
24f7018c21STomi Valkeinen |* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *|
25f7018c21STomi Valkeinen |* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *|
26f7018c21STomi Valkeinen |* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *|
27f7018c21STomi Valkeinen |* *|
28f7018c21STomi Valkeinen |* U.S. Government End Users. This source code is a "commercial *|
29f7018c21STomi Valkeinen |* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *|
30f7018c21STomi Valkeinen |* consisting of "commercial computer software" and "commercial *|
31f7018c21STomi Valkeinen |* computer software documentation," as such terms are used in *|
32f7018c21STomi Valkeinen |* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
33f7018c21STomi Valkeinen |* ment only as a commercial end item. Consistent with 48 C.F.R. *|
34f7018c21STomi Valkeinen |* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
35f7018c21STomi Valkeinen |* all U.S. Government End Users acquire the source code with only *|
36f7018c21STomi Valkeinen |* those rights set forth herein. *|
37f7018c21STomi Valkeinen |* *|
38f7018c21STomi Valkeinen \***************************************************************************/
39f7018c21STomi Valkeinen
40f7018c21STomi Valkeinen /*
41f7018c21STomi Valkeinen * GPL licensing note -- nVidia is allowing a liberal interpretation of
42f7018c21STomi Valkeinen * the documentation restriction above, to merely say that this nVidia's
43f7018c21STomi Valkeinen * copyright and disclaimer should be included with all code derived
44f7018c21STomi Valkeinen * from this source. -- Jeff Garzik <jgarzik@pobox.com>, 01/Nov/99
45f7018c21STomi Valkeinen */
46f7018c21STomi Valkeinen
47f7018c21STomi Valkeinen /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/riva_hw.c,v 1.33 2002/08/05 20:47:06 mvojkovi Exp $ */
48f7018c21STomi Valkeinen
49f7018c21STomi Valkeinen #include <linux/kernel.h>
50f7018c21STomi Valkeinen #include <linux/pci.h>
51f7018c21STomi Valkeinen #include <linux/pci_ids.h>
52f7018c21STomi Valkeinen #include "riva_hw.h"
53f7018c21STomi Valkeinen #include "riva_tbl.h"
54f7018c21STomi Valkeinen #include "nv_type.h"
55f7018c21STomi Valkeinen
56f7018c21STomi Valkeinen /*
57f7018c21STomi Valkeinen * This file is an OS-agnostic file used to make RIVA 128 and RIVA TNT
58f7018c21STomi Valkeinen * operate identically (except TNT has more memory and better 3D quality.
59f7018c21STomi Valkeinen */
nv3Busy(RIVA_HW_INST * chip)60f7018c21STomi Valkeinen static int nv3Busy
61f7018c21STomi Valkeinen (
62f7018c21STomi Valkeinen RIVA_HW_INST *chip
63f7018c21STomi Valkeinen )
64f7018c21STomi Valkeinen {
65f7018c21STomi Valkeinen return ((NV_RD32(&chip->Rop->FifoFree, 0) < chip->FifoEmptyCount) ||
66f7018c21STomi Valkeinen NV_RD32(&chip->PGRAPH[0x000006B0/4], 0) & 0x01);
67f7018c21STomi Valkeinen }
nv4Busy(RIVA_HW_INST * chip)68f7018c21STomi Valkeinen static int nv4Busy
69f7018c21STomi Valkeinen (
70f7018c21STomi Valkeinen RIVA_HW_INST *chip
71f7018c21STomi Valkeinen )
72f7018c21STomi Valkeinen {
73f7018c21STomi Valkeinen return ((NV_RD32(&chip->Rop->FifoFree, 0) < chip->FifoEmptyCount) ||
74f7018c21STomi Valkeinen NV_RD32(&chip->PGRAPH[0x00000700/4], 0) & 0x01);
75f7018c21STomi Valkeinen }
nv10Busy(RIVA_HW_INST * chip)76f7018c21STomi Valkeinen static int nv10Busy
77f7018c21STomi Valkeinen (
78f7018c21STomi Valkeinen RIVA_HW_INST *chip
79f7018c21STomi Valkeinen )
80f7018c21STomi Valkeinen {
81f7018c21STomi Valkeinen return ((NV_RD32(&chip->Rop->FifoFree, 0) < chip->FifoEmptyCount) ||
82f7018c21STomi Valkeinen NV_RD32(&chip->PGRAPH[0x00000700/4], 0) & 0x01);
83f7018c21STomi Valkeinen }
84f7018c21STomi Valkeinen
vgaLockUnlock(RIVA_HW_INST * chip,int Lock)85f7018c21STomi Valkeinen static void vgaLockUnlock
86f7018c21STomi Valkeinen (
87f7018c21STomi Valkeinen RIVA_HW_INST *chip,
88f7018c21STomi Valkeinen int Lock
89f7018c21STomi Valkeinen )
90f7018c21STomi Valkeinen {
91f7018c21STomi Valkeinen U008 cr11;
92f7018c21STomi Valkeinen VGA_WR08(chip->PCIO, 0x3D4, 0x11);
93f7018c21STomi Valkeinen cr11 = VGA_RD08(chip->PCIO, 0x3D5);
94f7018c21STomi Valkeinen if(Lock) cr11 |= 0x80;
95f7018c21STomi Valkeinen else cr11 &= ~0x80;
96f7018c21STomi Valkeinen VGA_WR08(chip->PCIO, 0x3D5, cr11);
97f7018c21STomi Valkeinen }
nv3LockUnlock(RIVA_HW_INST * chip,int Lock)98f7018c21STomi Valkeinen static void nv3LockUnlock
99f7018c21STomi Valkeinen (
100f7018c21STomi Valkeinen RIVA_HW_INST *chip,
101f7018c21STomi Valkeinen int Lock
102f7018c21STomi Valkeinen )
103f7018c21STomi Valkeinen {
104f7018c21STomi Valkeinen VGA_WR08(chip->PVIO, 0x3C4, 0x06);
105f7018c21STomi Valkeinen VGA_WR08(chip->PVIO, 0x3C5, Lock ? 0x99 : 0x57);
106f7018c21STomi Valkeinen vgaLockUnlock(chip, Lock);
107f7018c21STomi Valkeinen }
nv4LockUnlock(RIVA_HW_INST * chip,int Lock)108f7018c21STomi Valkeinen static void nv4LockUnlock
109f7018c21STomi Valkeinen (
110f7018c21STomi Valkeinen RIVA_HW_INST *chip,
111f7018c21STomi Valkeinen int Lock
112f7018c21STomi Valkeinen )
113f7018c21STomi Valkeinen {
114f7018c21STomi Valkeinen VGA_WR08(chip->PCIO, 0x3D4, 0x1F);
115f7018c21STomi Valkeinen VGA_WR08(chip->PCIO, 0x3D5, Lock ? 0x99 : 0x57);
116f7018c21STomi Valkeinen vgaLockUnlock(chip, Lock);
117f7018c21STomi Valkeinen }
118f7018c21STomi Valkeinen
ShowHideCursor(RIVA_HW_INST * chip,int ShowHide)119f7018c21STomi Valkeinen static int ShowHideCursor
120f7018c21STomi Valkeinen (
121f7018c21STomi Valkeinen RIVA_HW_INST *chip,
122f7018c21STomi Valkeinen int ShowHide
123f7018c21STomi Valkeinen )
124f7018c21STomi Valkeinen {
125f7018c21STomi Valkeinen int cursor;
126f7018c21STomi Valkeinen cursor = chip->CurrentState->cursor1;
127f7018c21STomi Valkeinen chip->CurrentState->cursor1 = (chip->CurrentState->cursor1 & 0xFE) |
128f7018c21STomi Valkeinen (ShowHide & 0x01);
129f7018c21STomi Valkeinen VGA_WR08(chip->PCIO, 0x3D4, 0x31);
130f7018c21STomi Valkeinen VGA_WR08(chip->PCIO, 0x3D5, chip->CurrentState->cursor1);
131f7018c21STomi Valkeinen return (cursor & 0x01);
132f7018c21STomi Valkeinen }
133f7018c21STomi Valkeinen
134f7018c21STomi Valkeinen /****************************************************************************\
135f7018c21STomi Valkeinen * *
136f7018c21STomi Valkeinen * The video arbitration routines calculate some "magic" numbers. Fixes *
137f7018c21STomi Valkeinen * the snow seen when accessing the framebuffer without it. *
138f7018c21STomi Valkeinen * It just works (I hope). *
139f7018c21STomi Valkeinen * *
140f7018c21STomi Valkeinen \****************************************************************************/
141f7018c21STomi Valkeinen
142f7018c21STomi Valkeinen #define DEFAULT_GR_LWM 100
143f7018c21STomi Valkeinen #define DEFAULT_VID_LWM 100
144f7018c21STomi Valkeinen #define DEFAULT_GR_BURST_SIZE 256
145f7018c21STomi Valkeinen #define DEFAULT_VID_BURST_SIZE 128
146f7018c21STomi Valkeinen #define VIDEO 0
147f7018c21STomi Valkeinen #define GRAPHICS 1
148f7018c21STomi Valkeinen #define MPORT 2
149f7018c21STomi Valkeinen #define ENGINE 3
150f7018c21STomi Valkeinen #define GFIFO_SIZE 320
151f7018c21STomi Valkeinen #define GFIFO_SIZE_128 256
152f7018c21STomi Valkeinen #define MFIFO_SIZE 120
153f7018c21STomi Valkeinen #define VFIFO_SIZE 256
154f7018c21STomi Valkeinen
155f7018c21STomi Valkeinen typedef struct {
156f7018c21STomi Valkeinen int gdrain_rate;
157f7018c21STomi Valkeinen int vdrain_rate;
158f7018c21STomi Valkeinen int mdrain_rate;
159f7018c21STomi Valkeinen int gburst_size;
160f7018c21STomi Valkeinen int vburst_size;
161f7018c21STomi Valkeinen char vid_en;
162f7018c21STomi Valkeinen char gr_en;
163f7018c21STomi Valkeinen int wcmocc, wcgocc, wcvocc, wcvlwm, wcglwm;
164f7018c21STomi Valkeinen int by_gfacc;
165f7018c21STomi Valkeinen char vid_only_once;
166f7018c21STomi Valkeinen char gr_only_once;
167f7018c21STomi Valkeinen char first_vacc;
168f7018c21STomi Valkeinen char first_gacc;
169f7018c21STomi Valkeinen char first_macc;
170f7018c21STomi Valkeinen int vocc;
171f7018c21STomi Valkeinen int gocc;
172f7018c21STomi Valkeinen int mocc;
173f7018c21STomi Valkeinen char cur;
174f7018c21STomi Valkeinen char engine_en;
175f7018c21STomi Valkeinen char converged;
176f7018c21STomi Valkeinen int priority;
177f7018c21STomi Valkeinen } nv3_arb_info;
178f7018c21STomi Valkeinen typedef struct {
179f7018c21STomi Valkeinen int graphics_lwm;
180f7018c21STomi Valkeinen int video_lwm;
181f7018c21STomi Valkeinen int graphics_burst_size;
182f7018c21STomi Valkeinen int video_burst_size;
183f7018c21STomi Valkeinen int graphics_hi_priority;
184f7018c21STomi Valkeinen int media_hi_priority;
185f7018c21STomi Valkeinen int rtl_values;
186f7018c21STomi Valkeinen int valid;
187f7018c21STomi Valkeinen } nv3_fifo_info;
188f7018c21STomi Valkeinen typedef struct {
189f7018c21STomi Valkeinen char pix_bpp;
190f7018c21STomi Valkeinen char enable_video;
191f7018c21STomi Valkeinen char gr_during_vid;
192f7018c21STomi Valkeinen char enable_mp;
193f7018c21STomi Valkeinen int memory_width;
194f7018c21STomi Valkeinen int video_scale;
195f7018c21STomi Valkeinen int pclk_khz;
196f7018c21STomi Valkeinen int mclk_khz;
197f7018c21STomi Valkeinen int mem_page_miss;
198f7018c21STomi Valkeinen int mem_latency;
199f7018c21STomi Valkeinen char mem_aligned;
200f7018c21STomi Valkeinen } nv3_sim_state;
201f7018c21STomi Valkeinen typedef struct {
202f7018c21STomi Valkeinen int graphics_lwm;
203f7018c21STomi Valkeinen int video_lwm;
204f7018c21STomi Valkeinen int graphics_burst_size;
205f7018c21STomi Valkeinen int video_burst_size;
206f7018c21STomi Valkeinen int valid;
207f7018c21STomi Valkeinen } nv4_fifo_info;
208f7018c21STomi Valkeinen typedef struct {
209f7018c21STomi Valkeinen int pclk_khz;
210f7018c21STomi Valkeinen int mclk_khz;
211f7018c21STomi Valkeinen int nvclk_khz;
212f7018c21STomi Valkeinen char mem_page_miss;
213f7018c21STomi Valkeinen char mem_latency;
214f7018c21STomi Valkeinen int memory_width;
215f7018c21STomi Valkeinen char enable_video;
216f7018c21STomi Valkeinen char gr_during_vid;
217f7018c21STomi Valkeinen char pix_bpp;
218f7018c21STomi Valkeinen char mem_aligned;
219f7018c21STomi Valkeinen char enable_mp;
220f7018c21STomi Valkeinen } nv4_sim_state;
221f7018c21STomi Valkeinen typedef struct {
222f7018c21STomi Valkeinen int graphics_lwm;
223f7018c21STomi Valkeinen int video_lwm;
224f7018c21STomi Valkeinen int graphics_burst_size;
225f7018c21STomi Valkeinen int video_burst_size;
226f7018c21STomi Valkeinen int valid;
227f7018c21STomi Valkeinen } nv10_fifo_info;
228f7018c21STomi Valkeinen typedef struct {
229f7018c21STomi Valkeinen int pclk_khz;
230f7018c21STomi Valkeinen int mclk_khz;
231f7018c21STomi Valkeinen int nvclk_khz;
232f7018c21STomi Valkeinen char mem_page_miss;
233f7018c21STomi Valkeinen char mem_latency;
234f7018c21STomi Valkeinen u32 memory_type;
235f7018c21STomi Valkeinen int memory_width;
236f7018c21STomi Valkeinen char enable_video;
237f7018c21STomi Valkeinen char gr_during_vid;
238f7018c21STomi Valkeinen char pix_bpp;
239f7018c21STomi Valkeinen char mem_aligned;
240f7018c21STomi Valkeinen char enable_mp;
241f7018c21STomi Valkeinen } nv10_sim_state;
nv3_iterate(nv3_fifo_info * res_info,nv3_sim_state * state,nv3_arb_info * ainfo)242f7018c21STomi Valkeinen static int nv3_iterate(nv3_fifo_info *res_info, nv3_sim_state * state, nv3_arb_info *ainfo)
243f7018c21STomi Valkeinen {
244f7018c21STomi Valkeinen int iter = 0;
245f7018c21STomi Valkeinen int tmp;
246f7018c21STomi Valkeinen int vfsize, mfsize, gfsize;
247f7018c21STomi Valkeinen int mburst_size = 32;
248f7018c21STomi Valkeinen int mmisses, gmisses, vmisses;
249f7018c21STomi Valkeinen int misses;
250fa5226e5SAlex Shi int vlwm, glwm;
251f7018c21STomi Valkeinen int last, next, cur;
252f7018c21STomi Valkeinen int max_gfsize ;
253f7018c21STomi Valkeinen long ns;
254f7018c21STomi Valkeinen
255f7018c21STomi Valkeinen vlwm = 0;
256f7018c21STomi Valkeinen glwm = 0;
257f7018c21STomi Valkeinen vfsize = 0;
258f7018c21STomi Valkeinen gfsize = 0;
259f7018c21STomi Valkeinen cur = ainfo->cur;
260f7018c21STomi Valkeinen mmisses = 2;
261f7018c21STomi Valkeinen gmisses = 2;
262f7018c21STomi Valkeinen vmisses = 2;
263f7018c21STomi Valkeinen if (ainfo->gburst_size == 128) max_gfsize = GFIFO_SIZE_128;
264f7018c21STomi Valkeinen else max_gfsize = GFIFO_SIZE;
265f7018c21STomi Valkeinen max_gfsize = GFIFO_SIZE;
266f7018c21STomi Valkeinen while (1)
267f7018c21STomi Valkeinen {
268f7018c21STomi Valkeinen if (ainfo->vid_en)
269f7018c21STomi Valkeinen {
270f7018c21STomi Valkeinen if (ainfo->wcvocc > ainfo->vocc) ainfo->wcvocc = ainfo->vocc;
271f7018c21STomi Valkeinen if (ainfo->wcvlwm > vlwm) ainfo->wcvlwm = vlwm ;
272f7018c21STomi Valkeinen ns = 1000000 * ainfo->vburst_size/(state->memory_width/8)/state->mclk_khz;
273f7018c21STomi Valkeinen vfsize = ns * ainfo->vdrain_rate / 1000000;
274f7018c21STomi Valkeinen vfsize = ainfo->wcvlwm - ainfo->vburst_size + vfsize;
275f7018c21STomi Valkeinen }
276f7018c21STomi Valkeinen if (state->enable_mp)
277f7018c21STomi Valkeinen {
278f7018c21STomi Valkeinen if (ainfo->wcmocc > ainfo->mocc) ainfo->wcmocc = ainfo->mocc;
279f7018c21STomi Valkeinen }
280f7018c21STomi Valkeinen if (ainfo->gr_en)
281f7018c21STomi Valkeinen {
282f7018c21STomi Valkeinen if (ainfo->wcglwm > glwm) ainfo->wcglwm = glwm ;
283f7018c21STomi Valkeinen if (ainfo->wcgocc > ainfo->gocc) ainfo->wcgocc = ainfo->gocc;
284f7018c21STomi Valkeinen ns = 1000000 * (ainfo->gburst_size/(state->memory_width/8))/state->mclk_khz;
285f7018c21STomi Valkeinen gfsize = (ns * (long) ainfo->gdrain_rate)/1000000;
286f7018c21STomi Valkeinen gfsize = ainfo->wcglwm - ainfo->gburst_size + gfsize;
287f7018c21STomi Valkeinen }
288f7018c21STomi Valkeinen mfsize = 0;
289f7018c21STomi Valkeinen if (!state->gr_during_vid && ainfo->vid_en)
290f7018c21STomi Valkeinen if (ainfo->vid_en && (ainfo->vocc < 0) && !ainfo->vid_only_once)
291f7018c21STomi Valkeinen next = VIDEO;
292f7018c21STomi Valkeinen else if (ainfo->mocc < 0)
293f7018c21STomi Valkeinen next = MPORT;
294f7018c21STomi Valkeinen else if (ainfo->gocc< ainfo->by_gfacc)
295f7018c21STomi Valkeinen next = GRAPHICS;
296f7018c21STomi Valkeinen else return (0);
297f7018c21STomi Valkeinen else switch (ainfo->priority)
298f7018c21STomi Valkeinen {
299f7018c21STomi Valkeinen case VIDEO:
300f7018c21STomi Valkeinen if (ainfo->vid_en && ainfo->vocc<0 && !ainfo->vid_only_once)
301f7018c21STomi Valkeinen next = VIDEO;
302f7018c21STomi Valkeinen else if (ainfo->gr_en && ainfo->gocc<0 && !ainfo->gr_only_once)
303f7018c21STomi Valkeinen next = GRAPHICS;
304f7018c21STomi Valkeinen else if (ainfo->mocc<0)
305f7018c21STomi Valkeinen next = MPORT;
306f7018c21STomi Valkeinen else return (0);
307f7018c21STomi Valkeinen break;
308f7018c21STomi Valkeinen case GRAPHICS:
309f7018c21STomi Valkeinen if (ainfo->gr_en && ainfo->gocc<0 && !ainfo->gr_only_once)
310f7018c21STomi Valkeinen next = GRAPHICS;
311f7018c21STomi Valkeinen else if (ainfo->vid_en && ainfo->vocc<0 && !ainfo->vid_only_once)
312f7018c21STomi Valkeinen next = VIDEO;
313f7018c21STomi Valkeinen else if (ainfo->mocc<0)
314f7018c21STomi Valkeinen next = MPORT;
315f7018c21STomi Valkeinen else return (0);
316f7018c21STomi Valkeinen break;
317f7018c21STomi Valkeinen default:
318f7018c21STomi Valkeinen if (ainfo->mocc<0)
319f7018c21STomi Valkeinen next = MPORT;
320f7018c21STomi Valkeinen else if (ainfo->gr_en && ainfo->gocc<0 && !ainfo->gr_only_once)
321f7018c21STomi Valkeinen next = GRAPHICS;
322f7018c21STomi Valkeinen else if (ainfo->vid_en && ainfo->vocc<0 && !ainfo->vid_only_once)
323f7018c21STomi Valkeinen next = VIDEO;
324f7018c21STomi Valkeinen else return (0);
325f7018c21STomi Valkeinen break;
326f7018c21STomi Valkeinen }
327f7018c21STomi Valkeinen last = cur;
328f7018c21STomi Valkeinen cur = next;
329f7018c21STomi Valkeinen iter++;
330f7018c21STomi Valkeinen switch (cur)
331f7018c21STomi Valkeinen {
332f7018c21STomi Valkeinen case VIDEO:
333f7018c21STomi Valkeinen if (last==cur) misses = 0;
334f7018c21STomi Valkeinen else if (ainfo->first_vacc) misses = vmisses;
335f7018c21STomi Valkeinen else misses = 1;
336f7018c21STomi Valkeinen ainfo->first_vacc = 0;
337f7018c21STomi Valkeinen if (last!=cur)
338f7018c21STomi Valkeinen {
339f7018c21STomi Valkeinen ns = 1000000 * (vmisses*state->mem_page_miss + state->mem_latency)/state->mclk_khz;
340f7018c21STomi Valkeinen vlwm = ns * ainfo->vdrain_rate/ 1000000;
341f7018c21STomi Valkeinen vlwm = ainfo->vocc - vlwm;
342f7018c21STomi Valkeinen }
343f7018c21STomi Valkeinen ns = 1000000*(misses*state->mem_page_miss + ainfo->vburst_size)/(state->memory_width/8)/state->mclk_khz;
344f7018c21STomi Valkeinen ainfo->vocc = ainfo->vocc + ainfo->vburst_size - ns*ainfo->vdrain_rate/1000000;
345f7018c21STomi Valkeinen ainfo->gocc = ainfo->gocc - ns*ainfo->gdrain_rate/1000000;
346f7018c21STomi Valkeinen ainfo->mocc = ainfo->mocc - ns*ainfo->mdrain_rate/1000000;
347f7018c21STomi Valkeinen break;
348f7018c21STomi Valkeinen case GRAPHICS:
349f7018c21STomi Valkeinen if (last==cur) misses = 0;
350f7018c21STomi Valkeinen else if (ainfo->first_gacc) misses = gmisses;
351f7018c21STomi Valkeinen else misses = 1;
352f7018c21STomi Valkeinen ainfo->first_gacc = 0;
353f7018c21STomi Valkeinen if (last!=cur)
354f7018c21STomi Valkeinen {
355f7018c21STomi Valkeinen ns = 1000000*(gmisses*state->mem_page_miss + state->mem_latency)/state->mclk_khz ;
356f7018c21STomi Valkeinen glwm = ns * ainfo->gdrain_rate/1000000;
357f7018c21STomi Valkeinen glwm = ainfo->gocc - glwm;
358f7018c21STomi Valkeinen }
359f7018c21STomi Valkeinen ns = 1000000*(misses*state->mem_page_miss + ainfo->gburst_size/(state->memory_width/8))/state->mclk_khz;
360f7018c21STomi Valkeinen ainfo->vocc = ainfo->vocc + 0 - ns*ainfo->vdrain_rate/1000000;
361f7018c21STomi Valkeinen ainfo->gocc = ainfo->gocc + ainfo->gburst_size - ns*ainfo->gdrain_rate/1000000;
362f7018c21STomi Valkeinen ainfo->mocc = ainfo->mocc + 0 - ns*ainfo->mdrain_rate/1000000;
363f7018c21STomi Valkeinen break;
364f7018c21STomi Valkeinen default:
365f7018c21STomi Valkeinen if (last==cur) misses = 0;
366f7018c21STomi Valkeinen else if (ainfo->first_macc) misses = mmisses;
367f7018c21STomi Valkeinen else misses = 1;
368f7018c21STomi Valkeinen ainfo->first_macc = 0;
369f7018c21STomi Valkeinen ns = 1000000*(misses*state->mem_page_miss + mburst_size/(state->memory_width/8))/state->mclk_khz;
370f7018c21STomi Valkeinen ainfo->vocc = ainfo->vocc + 0 - ns*ainfo->vdrain_rate/1000000;
371f7018c21STomi Valkeinen ainfo->gocc = ainfo->gocc + 0 - ns*ainfo->gdrain_rate/1000000;
372f7018c21STomi Valkeinen ainfo->mocc = ainfo->mocc + mburst_size - ns*ainfo->mdrain_rate/1000000;
373f7018c21STomi Valkeinen break;
374f7018c21STomi Valkeinen }
375f7018c21STomi Valkeinen if (iter>100)
376f7018c21STomi Valkeinen {
377f7018c21STomi Valkeinen ainfo->converged = 0;
378f7018c21STomi Valkeinen return (1);
379f7018c21STomi Valkeinen }
380f7018c21STomi Valkeinen ns = 1000000*ainfo->gburst_size/(state->memory_width/8)/state->mclk_khz;
381f7018c21STomi Valkeinen tmp = ns * ainfo->gdrain_rate/1000000;
382f7018c21STomi Valkeinen if (abs(ainfo->gburst_size) + ((abs(ainfo->wcglwm) + 16 ) & ~0x7) - tmp > max_gfsize)
383f7018c21STomi Valkeinen {
384f7018c21STomi Valkeinen ainfo->converged = 0;
385f7018c21STomi Valkeinen return (1);
386f7018c21STomi Valkeinen }
387f7018c21STomi Valkeinen ns = 1000000*ainfo->vburst_size/(state->memory_width/8)/state->mclk_khz;
388f7018c21STomi Valkeinen tmp = ns * ainfo->vdrain_rate/1000000;
389f7018c21STomi Valkeinen if (abs(ainfo->vburst_size) + (abs(ainfo->wcvlwm + 32) & ~0xf) - tmp> VFIFO_SIZE)
390f7018c21STomi Valkeinen {
391f7018c21STomi Valkeinen ainfo->converged = 0;
392f7018c21STomi Valkeinen return (1);
393f7018c21STomi Valkeinen }
394f7018c21STomi Valkeinen if (abs(ainfo->gocc) > max_gfsize)
395f7018c21STomi Valkeinen {
396f7018c21STomi Valkeinen ainfo->converged = 0;
397f7018c21STomi Valkeinen return (1);
398f7018c21STomi Valkeinen }
399f7018c21STomi Valkeinen if (abs(ainfo->vocc) > VFIFO_SIZE)
400f7018c21STomi Valkeinen {
401f7018c21STomi Valkeinen ainfo->converged = 0;
402f7018c21STomi Valkeinen return (1);
403f7018c21STomi Valkeinen }
404f7018c21STomi Valkeinen if (abs(ainfo->mocc) > MFIFO_SIZE)
405f7018c21STomi Valkeinen {
406f7018c21STomi Valkeinen ainfo->converged = 0;
407f7018c21STomi Valkeinen return (1);
408f7018c21STomi Valkeinen }
409f7018c21STomi Valkeinen if (abs(vfsize) > VFIFO_SIZE)
410f7018c21STomi Valkeinen {
411f7018c21STomi Valkeinen ainfo->converged = 0;
412f7018c21STomi Valkeinen return (1);
413f7018c21STomi Valkeinen }
414f7018c21STomi Valkeinen if (abs(gfsize) > max_gfsize)
415f7018c21STomi Valkeinen {
416f7018c21STomi Valkeinen ainfo->converged = 0;
417f7018c21STomi Valkeinen return (1);
418f7018c21STomi Valkeinen }
419f7018c21STomi Valkeinen if (abs(mfsize) > MFIFO_SIZE)
420f7018c21STomi Valkeinen {
421f7018c21STomi Valkeinen ainfo->converged = 0;
422f7018c21STomi Valkeinen return (1);
423f7018c21STomi Valkeinen }
424f7018c21STomi Valkeinen }
425f7018c21STomi Valkeinen }
nv3_arb(nv3_fifo_info * res_info,nv3_sim_state * state,nv3_arb_info * ainfo)426f7018c21STomi Valkeinen static char nv3_arb(nv3_fifo_info * res_info, nv3_sim_state * state, nv3_arb_info *ainfo)
427f7018c21STomi Valkeinen {
428f7018c21STomi Valkeinen long ens, vns, mns, gns;
429f7018c21STomi Valkeinen int mmisses, gmisses, vmisses, eburst_size, mburst_size;
430f7018c21STomi Valkeinen int refresh_cycle;
431f7018c21STomi Valkeinen
432f7018c21STomi Valkeinen refresh_cycle = 2*(state->mclk_khz/state->pclk_khz) + 5;
433f7018c21STomi Valkeinen mmisses = 2;
434f7018c21STomi Valkeinen if (state->mem_aligned) gmisses = 2;
435f7018c21STomi Valkeinen else gmisses = 3;
436f7018c21STomi Valkeinen vmisses = 2;
437f7018c21STomi Valkeinen eburst_size = state->memory_width * 1;
438f7018c21STomi Valkeinen mburst_size = 32;
439f7018c21STomi Valkeinen gns = 1000000 * (gmisses*state->mem_page_miss + state->mem_latency)/state->mclk_khz;
440f7018c21STomi Valkeinen ainfo->by_gfacc = gns*ainfo->gdrain_rate/1000000;
441f7018c21STomi Valkeinen ainfo->wcmocc = 0;
442f7018c21STomi Valkeinen ainfo->wcgocc = 0;
443f7018c21STomi Valkeinen ainfo->wcvocc = 0;
444f7018c21STomi Valkeinen ainfo->wcvlwm = 0;
445f7018c21STomi Valkeinen ainfo->wcglwm = 0;
446f7018c21STomi Valkeinen ainfo->engine_en = 1;
447f7018c21STomi Valkeinen ainfo->converged = 1;
448f7018c21STomi Valkeinen if (ainfo->engine_en)
449f7018c21STomi Valkeinen {
450f7018c21STomi Valkeinen ens = 1000000*(state->mem_page_miss + eburst_size/(state->memory_width/8) +refresh_cycle)/state->mclk_khz;
451f7018c21STomi Valkeinen ainfo->mocc = state->enable_mp ? 0-ens*ainfo->mdrain_rate/1000000 : 0;
452f7018c21STomi Valkeinen ainfo->vocc = ainfo->vid_en ? 0-ens*ainfo->vdrain_rate/1000000 : 0;
453f7018c21STomi Valkeinen ainfo->gocc = ainfo->gr_en ? 0-ens*ainfo->gdrain_rate/1000000 : 0;
454f7018c21STomi Valkeinen ainfo->cur = ENGINE;
455f7018c21STomi Valkeinen ainfo->first_vacc = 1;
456f7018c21STomi Valkeinen ainfo->first_gacc = 1;
457f7018c21STomi Valkeinen ainfo->first_macc = 1;
458f7018c21STomi Valkeinen nv3_iterate(res_info, state,ainfo);
459f7018c21STomi Valkeinen }
460f7018c21STomi Valkeinen if (state->enable_mp)
461f7018c21STomi Valkeinen {
462f7018c21STomi Valkeinen mns = 1000000 * (mmisses*state->mem_page_miss + mburst_size/(state->memory_width/8) + refresh_cycle)/state->mclk_khz;
463f7018c21STomi Valkeinen ainfo->mocc = state->enable_mp ? 0 : mburst_size - mns*ainfo->mdrain_rate/1000000;
464f7018c21STomi Valkeinen ainfo->vocc = ainfo->vid_en ? 0 : 0- mns*ainfo->vdrain_rate/1000000;
465f7018c21STomi Valkeinen ainfo->gocc = ainfo->gr_en ? 0: 0- mns*ainfo->gdrain_rate/1000000;
466f7018c21STomi Valkeinen ainfo->cur = MPORT;
467f7018c21STomi Valkeinen ainfo->first_vacc = 1;
468f7018c21STomi Valkeinen ainfo->first_gacc = 1;
469f7018c21STomi Valkeinen ainfo->first_macc = 0;
470f7018c21STomi Valkeinen nv3_iterate(res_info, state,ainfo);
471f7018c21STomi Valkeinen }
472f7018c21STomi Valkeinen if (ainfo->gr_en)
473f7018c21STomi Valkeinen {
474f7018c21STomi Valkeinen ainfo->first_vacc = 1;
475f7018c21STomi Valkeinen ainfo->first_gacc = 0;
476f7018c21STomi Valkeinen ainfo->first_macc = 1;
477f7018c21STomi Valkeinen gns = 1000000*(gmisses*state->mem_page_miss + ainfo->gburst_size/(state->memory_width/8) + refresh_cycle)/state->mclk_khz;
478f7018c21STomi Valkeinen ainfo->gocc = ainfo->gburst_size - gns*ainfo->gdrain_rate/1000000;
479f7018c21STomi Valkeinen ainfo->vocc = ainfo->vid_en? 0-gns*ainfo->vdrain_rate/1000000 : 0;
480f7018c21STomi Valkeinen ainfo->mocc = state->enable_mp ? 0-gns*ainfo->mdrain_rate/1000000: 0;
481f7018c21STomi Valkeinen ainfo->cur = GRAPHICS;
482f7018c21STomi Valkeinen nv3_iterate(res_info, state,ainfo);
483f7018c21STomi Valkeinen }
484f7018c21STomi Valkeinen if (ainfo->vid_en)
485f7018c21STomi Valkeinen {
486f7018c21STomi Valkeinen ainfo->first_vacc = 0;
487f7018c21STomi Valkeinen ainfo->first_gacc = 1;
488f7018c21STomi Valkeinen ainfo->first_macc = 1;
489f7018c21STomi Valkeinen vns = 1000000*(vmisses*state->mem_page_miss + ainfo->vburst_size/(state->memory_width/8) + refresh_cycle)/state->mclk_khz;
490f7018c21STomi Valkeinen ainfo->vocc = ainfo->vburst_size - vns*ainfo->vdrain_rate/1000000;
491f7018c21STomi Valkeinen ainfo->gocc = ainfo->gr_en? (0-vns*ainfo->gdrain_rate/1000000) : 0;
492f7018c21STomi Valkeinen ainfo->mocc = state->enable_mp? 0-vns*ainfo->mdrain_rate/1000000 :0 ;
493f7018c21STomi Valkeinen ainfo->cur = VIDEO;
494f7018c21STomi Valkeinen nv3_iterate(res_info, state, ainfo);
495f7018c21STomi Valkeinen }
496f7018c21STomi Valkeinen if (ainfo->converged)
497f7018c21STomi Valkeinen {
498f7018c21STomi Valkeinen res_info->graphics_lwm = (int)abs(ainfo->wcglwm) + 16;
499f7018c21STomi Valkeinen res_info->video_lwm = (int)abs(ainfo->wcvlwm) + 32;
500f7018c21STomi Valkeinen res_info->graphics_burst_size = ainfo->gburst_size;
501f7018c21STomi Valkeinen res_info->video_burst_size = ainfo->vburst_size;
502f7018c21STomi Valkeinen res_info->graphics_hi_priority = (ainfo->priority == GRAPHICS);
503f7018c21STomi Valkeinen res_info->media_hi_priority = (ainfo->priority == MPORT);
504f7018c21STomi Valkeinen if (res_info->video_lwm > 160)
505f7018c21STomi Valkeinen {
506f7018c21STomi Valkeinen res_info->graphics_lwm = 256;
507f7018c21STomi Valkeinen res_info->video_lwm = 128;
508f7018c21STomi Valkeinen res_info->graphics_burst_size = 64;
509f7018c21STomi Valkeinen res_info->video_burst_size = 64;
510f7018c21STomi Valkeinen res_info->graphics_hi_priority = 0;
511f7018c21STomi Valkeinen res_info->media_hi_priority = 0;
512f7018c21STomi Valkeinen ainfo->converged = 0;
513f7018c21STomi Valkeinen return (0);
514f7018c21STomi Valkeinen }
515f7018c21STomi Valkeinen if (res_info->video_lwm > 128)
516f7018c21STomi Valkeinen {
517f7018c21STomi Valkeinen res_info->video_lwm = 128;
518f7018c21STomi Valkeinen }
519f7018c21STomi Valkeinen return (1);
520f7018c21STomi Valkeinen }
521f7018c21STomi Valkeinen else
522f7018c21STomi Valkeinen {
523f7018c21STomi Valkeinen res_info->graphics_lwm = 256;
524f7018c21STomi Valkeinen res_info->video_lwm = 128;
525f7018c21STomi Valkeinen res_info->graphics_burst_size = 64;
526f7018c21STomi Valkeinen res_info->video_burst_size = 64;
527f7018c21STomi Valkeinen res_info->graphics_hi_priority = 0;
528f7018c21STomi Valkeinen res_info->media_hi_priority = 0;
529f7018c21STomi Valkeinen return (0);
530f7018c21STomi Valkeinen }
531f7018c21STomi Valkeinen }
nv3_get_param(nv3_fifo_info * res_info,nv3_sim_state * state,nv3_arb_info * ainfo)532f7018c21STomi Valkeinen static char nv3_get_param(nv3_fifo_info *res_info, nv3_sim_state * state, nv3_arb_info *ainfo)
533f7018c21STomi Valkeinen {
534f7018c21STomi Valkeinen int done, g,v, p;
535f7018c21STomi Valkeinen
536f7018c21STomi Valkeinen done = 0;
537f7018c21STomi Valkeinen for (p=0; p < 2; p++)
538f7018c21STomi Valkeinen {
539f7018c21STomi Valkeinen for (g=128 ; g > 32; g= g>> 1)
540f7018c21STomi Valkeinen {
541f7018c21STomi Valkeinen for (v=128; v >=32; v = v>> 1)
542f7018c21STomi Valkeinen {
543f7018c21STomi Valkeinen ainfo->priority = p;
544f7018c21STomi Valkeinen ainfo->gburst_size = g;
545f7018c21STomi Valkeinen ainfo->vburst_size = v;
546f7018c21STomi Valkeinen done = nv3_arb(res_info, state,ainfo);
547f7018c21STomi Valkeinen if (done && (g==128))
548f7018c21STomi Valkeinen if ((res_info->graphics_lwm + g) > 256)
549f7018c21STomi Valkeinen done = 0;
550f7018c21STomi Valkeinen if (done)
551f7018c21STomi Valkeinen goto Done;
552f7018c21STomi Valkeinen }
553f7018c21STomi Valkeinen }
554f7018c21STomi Valkeinen }
555f7018c21STomi Valkeinen
556f7018c21STomi Valkeinen Done:
557f7018c21STomi Valkeinen return done;
558f7018c21STomi Valkeinen }
nv3CalcArbitration(nv3_fifo_info * res_info,nv3_sim_state * state)559f7018c21STomi Valkeinen static void nv3CalcArbitration
560f7018c21STomi Valkeinen (
561f7018c21STomi Valkeinen nv3_fifo_info * res_info,
562f7018c21STomi Valkeinen nv3_sim_state * state
563f7018c21STomi Valkeinen )
564f7018c21STomi Valkeinen {
565f7018c21STomi Valkeinen nv3_fifo_info save_info;
566f7018c21STomi Valkeinen nv3_arb_info ainfo;
567f7018c21STomi Valkeinen char res_gr, res_vid;
568f7018c21STomi Valkeinen
569f7018c21STomi Valkeinen ainfo.gr_en = 1;
570f7018c21STomi Valkeinen ainfo.vid_en = state->enable_video;
571f7018c21STomi Valkeinen ainfo.vid_only_once = 0;
572f7018c21STomi Valkeinen ainfo.gr_only_once = 0;
573f7018c21STomi Valkeinen ainfo.gdrain_rate = (int) state->pclk_khz * (state->pix_bpp/8);
574f7018c21STomi Valkeinen ainfo.vdrain_rate = (int) state->pclk_khz * 2;
575f7018c21STomi Valkeinen if (state->video_scale != 0)
576f7018c21STomi Valkeinen ainfo.vdrain_rate = ainfo.vdrain_rate/state->video_scale;
577f7018c21STomi Valkeinen ainfo.mdrain_rate = 33000;
578f7018c21STomi Valkeinen res_info->rtl_values = 0;
579f7018c21STomi Valkeinen if (!state->gr_during_vid && state->enable_video)
580f7018c21STomi Valkeinen {
581f7018c21STomi Valkeinen ainfo.gr_only_once = 1;
582f7018c21STomi Valkeinen ainfo.gr_en = 1;
583f7018c21STomi Valkeinen ainfo.gdrain_rate = 0;
584f7018c21STomi Valkeinen res_vid = nv3_get_param(res_info, state, &ainfo);
585f7018c21STomi Valkeinen res_vid = ainfo.converged;
586f7018c21STomi Valkeinen save_info.video_lwm = res_info->video_lwm;
587f7018c21STomi Valkeinen save_info.video_burst_size = res_info->video_burst_size;
588f7018c21STomi Valkeinen ainfo.vid_en = 1;
589f7018c21STomi Valkeinen ainfo.vid_only_once = 1;
590f7018c21STomi Valkeinen ainfo.gr_en = 1;
591f7018c21STomi Valkeinen ainfo.gdrain_rate = (int) state->pclk_khz * (state->pix_bpp/8);
592f7018c21STomi Valkeinen ainfo.vdrain_rate = 0;
593f7018c21STomi Valkeinen res_gr = nv3_get_param(res_info, state, &ainfo);
594f7018c21STomi Valkeinen res_gr = ainfo.converged;
595f7018c21STomi Valkeinen res_info->video_lwm = save_info.video_lwm;
596f7018c21STomi Valkeinen res_info->video_burst_size = save_info.video_burst_size;
597f7018c21STomi Valkeinen res_info->valid = res_gr & res_vid;
598f7018c21STomi Valkeinen }
599f7018c21STomi Valkeinen else
600f7018c21STomi Valkeinen {
601f7018c21STomi Valkeinen if (!ainfo.gr_en) ainfo.gdrain_rate = 0;
602f7018c21STomi Valkeinen if (!ainfo.vid_en) ainfo.vdrain_rate = 0;
603f7018c21STomi Valkeinen res_gr = nv3_get_param(res_info, state, &ainfo);
604f7018c21STomi Valkeinen res_info->valid = ainfo.converged;
605f7018c21STomi Valkeinen }
606f7018c21STomi Valkeinen }
nv3UpdateArbitrationSettings(unsigned VClk,unsigned pixelDepth,unsigned * burst,unsigned * lwm,RIVA_HW_INST * chip)607f7018c21STomi Valkeinen static void nv3UpdateArbitrationSettings
608f7018c21STomi Valkeinen (
609f7018c21STomi Valkeinen unsigned VClk,
610f7018c21STomi Valkeinen unsigned pixelDepth,
611f7018c21STomi Valkeinen unsigned *burst,
612f7018c21STomi Valkeinen unsigned *lwm,
613f7018c21STomi Valkeinen RIVA_HW_INST *chip
614f7018c21STomi Valkeinen )
615f7018c21STomi Valkeinen {
616f7018c21STomi Valkeinen nv3_fifo_info fifo_data;
617f7018c21STomi Valkeinen nv3_sim_state sim_data;
618f7018c21STomi Valkeinen unsigned int M, N, P, pll, MClk;
619f7018c21STomi Valkeinen
620f7018c21STomi Valkeinen pll = NV_RD32(&chip->PRAMDAC0[0x00000504/4], 0);
621f7018c21STomi Valkeinen M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;
622f7018c21STomi Valkeinen MClk = (N * chip->CrystalFreqKHz / M) >> P;
623f7018c21STomi Valkeinen sim_data.pix_bpp = (char)pixelDepth;
624f7018c21STomi Valkeinen sim_data.enable_video = 0;
625f7018c21STomi Valkeinen sim_data.enable_mp = 0;
626f7018c21STomi Valkeinen sim_data.video_scale = 1;
627f7018c21STomi Valkeinen sim_data.memory_width = (NV_RD32(&chip->PEXTDEV[0x00000000/4], 0) & 0x10) ?
628f7018c21STomi Valkeinen 128 : 64;
629f7018c21STomi Valkeinen sim_data.memory_width = 128;
630f7018c21STomi Valkeinen
631f7018c21STomi Valkeinen sim_data.mem_latency = 9;
632f7018c21STomi Valkeinen sim_data.mem_aligned = 1;
633f7018c21STomi Valkeinen sim_data.mem_page_miss = 11;
634f7018c21STomi Valkeinen sim_data.gr_during_vid = 0;
635f7018c21STomi Valkeinen sim_data.pclk_khz = VClk;
636f7018c21STomi Valkeinen sim_data.mclk_khz = MClk;
637f7018c21STomi Valkeinen nv3CalcArbitration(&fifo_data, &sim_data);
638f7018c21STomi Valkeinen if (fifo_data.valid)
639f7018c21STomi Valkeinen {
640f7018c21STomi Valkeinen int b = fifo_data.graphics_burst_size >> 4;
641f7018c21STomi Valkeinen *burst = 0;
642f7018c21STomi Valkeinen while (b >>= 1)
643f7018c21STomi Valkeinen (*burst)++;
644f7018c21STomi Valkeinen *lwm = fifo_data.graphics_lwm >> 3;
645f7018c21STomi Valkeinen }
646f7018c21STomi Valkeinen else
647f7018c21STomi Valkeinen {
648f7018c21STomi Valkeinen *lwm = 0x24;
649f7018c21STomi Valkeinen *burst = 0x2;
650f7018c21STomi Valkeinen }
651f7018c21STomi Valkeinen }
nv4CalcArbitration(nv4_fifo_info * fifo,nv4_sim_state * arb)652f7018c21STomi Valkeinen static void nv4CalcArbitration
653f7018c21STomi Valkeinen (
654f7018c21STomi Valkeinen nv4_fifo_info *fifo,
655f7018c21STomi Valkeinen nv4_sim_state *arb
656f7018c21STomi Valkeinen )
657f7018c21STomi Valkeinen {
658fa5226e5SAlex Shi int data, pagemiss, cas,width, video_enable, bpp;
659f7018c21STomi Valkeinen int nvclks, mclks, pclks, vpagemiss, crtpagemiss, vbs;
660f7018c21STomi Valkeinen int found, mclk_extra, mclk_loop, cbs, m1, p1;
661f7018c21STomi Valkeinen int mclk_freq, pclk_freq, nvclk_freq, mp_enable;
662f7018c21STomi Valkeinen int us_m, us_n, us_p, video_drain_rate, crtc_drain_rate;
663f7018c21STomi Valkeinen int vpm_us, us_video, vlwm, video_fill_us, cpm_us, us_crt,clwm;
664f7018c21STomi Valkeinen
665f7018c21STomi Valkeinen fifo->valid = 1;
666f7018c21STomi Valkeinen pclk_freq = arb->pclk_khz;
667f7018c21STomi Valkeinen mclk_freq = arb->mclk_khz;
668f7018c21STomi Valkeinen nvclk_freq = arb->nvclk_khz;
669f7018c21STomi Valkeinen pagemiss = arb->mem_page_miss;
670f7018c21STomi Valkeinen cas = arb->mem_latency;
671f7018c21STomi Valkeinen width = arb->memory_width >> 6;
672f7018c21STomi Valkeinen video_enable = arb->enable_video;
673f7018c21STomi Valkeinen bpp = arb->pix_bpp;
674f7018c21STomi Valkeinen mp_enable = arb->enable_mp;
675f7018c21STomi Valkeinen clwm = 0;
676f7018c21STomi Valkeinen vlwm = 0;
677f7018c21STomi Valkeinen cbs = 128;
678f7018c21STomi Valkeinen pclks = 2;
679f7018c21STomi Valkeinen nvclks = 2;
680f7018c21STomi Valkeinen nvclks += 2;
681f7018c21STomi Valkeinen nvclks += 1;
682f7018c21STomi Valkeinen mclks = 5;
683f7018c21STomi Valkeinen mclks += 3;
684f7018c21STomi Valkeinen mclks += 1;
685f7018c21STomi Valkeinen mclks += cas;
686f7018c21STomi Valkeinen mclks += 1;
687f7018c21STomi Valkeinen mclks += 1;
688f7018c21STomi Valkeinen mclks += 1;
689f7018c21STomi Valkeinen mclks += 1;
690f7018c21STomi Valkeinen mclk_extra = 3;
691f7018c21STomi Valkeinen nvclks += 2;
692f7018c21STomi Valkeinen nvclks += 1;
693f7018c21STomi Valkeinen nvclks += 1;
694f7018c21STomi Valkeinen nvclks += 1;
695f7018c21STomi Valkeinen if (mp_enable)
696f7018c21STomi Valkeinen mclks+=4;
697f7018c21STomi Valkeinen nvclks += 0;
698f7018c21STomi Valkeinen pclks += 0;
699f7018c21STomi Valkeinen found = 0;
700f7018c21STomi Valkeinen vbs = 0;
701f7018c21STomi Valkeinen while (found != 1)
702f7018c21STomi Valkeinen {
703f7018c21STomi Valkeinen fifo->valid = 1;
704f7018c21STomi Valkeinen found = 1;
705f7018c21STomi Valkeinen mclk_loop = mclks+mclk_extra;
706f7018c21STomi Valkeinen us_m = mclk_loop *1000*1000 / mclk_freq;
707f7018c21STomi Valkeinen us_n = nvclks*1000*1000 / nvclk_freq;
708f7018c21STomi Valkeinen us_p = nvclks*1000*1000 / pclk_freq;
709f7018c21STomi Valkeinen if (video_enable)
710f7018c21STomi Valkeinen {
711f7018c21STomi Valkeinen video_drain_rate = pclk_freq * 2;
712f7018c21STomi Valkeinen crtc_drain_rate = pclk_freq * bpp/8;
713f7018c21STomi Valkeinen vpagemiss = 2;
714f7018c21STomi Valkeinen vpagemiss += 1;
715f7018c21STomi Valkeinen crtpagemiss = 2;
716f7018c21STomi Valkeinen vpm_us = (vpagemiss * pagemiss)*1000*1000/mclk_freq;
717f7018c21STomi Valkeinen if (nvclk_freq * 2 > mclk_freq * width)
718f7018c21STomi Valkeinen video_fill_us = cbs*1000*1000 / 16 / nvclk_freq ;
719f7018c21STomi Valkeinen else
720f7018c21STomi Valkeinen video_fill_us = cbs*1000*1000 / (8 * width) / mclk_freq;
721f7018c21STomi Valkeinen us_video = vpm_us + us_m + us_n + us_p + video_fill_us;
722f7018c21STomi Valkeinen vlwm = us_video * video_drain_rate/(1000*1000);
723f7018c21STomi Valkeinen vlwm++;
724f7018c21STomi Valkeinen vbs = 128;
725f7018c21STomi Valkeinen if (vlwm > 128) vbs = 64;
726f7018c21STomi Valkeinen if (vlwm > (256-64)) vbs = 32;
727f7018c21STomi Valkeinen if (nvclk_freq * 2 > mclk_freq * width)
728f7018c21STomi Valkeinen video_fill_us = vbs *1000*1000/ 16 / nvclk_freq ;
729f7018c21STomi Valkeinen else
730f7018c21STomi Valkeinen video_fill_us = vbs*1000*1000 / (8 * width) / mclk_freq;
731f7018c21STomi Valkeinen cpm_us = crtpagemiss * pagemiss *1000*1000/ mclk_freq;
732f7018c21STomi Valkeinen us_crt =
733f7018c21STomi Valkeinen us_video
734f7018c21STomi Valkeinen +video_fill_us
735f7018c21STomi Valkeinen +cpm_us
736f7018c21STomi Valkeinen +us_m + us_n +us_p
737f7018c21STomi Valkeinen ;
738f7018c21STomi Valkeinen clwm = us_crt * crtc_drain_rate/(1000*1000);
739f7018c21STomi Valkeinen clwm++;
740f7018c21STomi Valkeinen }
741f7018c21STomi Valkeinen else
742f7018c21STomi Valkeinen {
743f7018c21STomi Valkeinen crtc_drain_rate = pclk_freq * bpp/8;
744f7018c21STomi Valkeinen crtpagemiss = 2;
745f7018c21STomi Valkeinen crtpagemiss += 1;
746f7018c21STomi Valkeinen cpm_us = crtpagemiss * pagemiss *1000*1000/ mclk_freq;
747f7018c21STomi Valkeinen us_crt = cpm_us + us_m + us_n + us_p ;
748f7018c21STomi Valkeinen clwm = us_crt * crtc_drain_rate/(1000*1000);
749f7018c21STomi Valkeinen clwm++;
750f7018c21STomi Valkeinen }
751f7018c21STomi Valkeinen m1 = clwm + cbs - 512;
752f7018c21STomi Valkeinen p1 = m1 * pclk_freq / mclk_freq;
753f7018c21STomi Valkeinen p1 = p1 * bpp / 8;
754f7018c21STomi Valkeinen if ((p1 < m1) && (m1 > 0))
755f7018c21STomi Valkeinen {
756f7018c21STomi Valkeinen fifo->valid = 0;
757f7018c21STomi Valkeinen found = 0;
758f7018c21STomi Valkeinen if (mclk_extra ==0) found = 1;
759f7018c21STomi Valkeinen mclk_extra--;
760f7018c21STomi Valkeinen }
761f7018c21STomi Valkeinen else if (video_enable)
762f7018c21STomi Valkeinen {
763f7018c21STomi Valkeinen if ((clwm > 511) || (vlwm > 255))
764f7018c21STomi Valkeinen {
765f7018c21STomi Valkeinen fifo->valid = 0;
766f7018c21STomi Valkeinen found = 0;
767f7018c21STomi Valkeinen if (mclk_extra ==0) found = 1;
768f7018c21STomi Valkeinen mclk_extra--;
769f7018c21STomi Valkeinen }
770f7018c21STomi Valkeinen }
771f7018c21STomi Valkeinen else
772f7018c21STomi Valkeinen {
773f7018c21STomi Valkeinen if (clwm > 519)
774f7018c21STomi Valkeinen {
775f7018c21STomi Valkeinen fifo->valid = 0;
776f7018c21STomi Valkeinen found = 0;
777f7018c21STomi Valkeinen if (mclk_extra ==0) found = 1;
778f7018c21STomi Valkeinen mclk_extra--;
779f7018c21STomi Valkeinen }
780f7018c21STomi Valkeinen }
781f7018c21STomi Valkeinen if (clwm < 384) clwm = 384;
782f7018c21STomi Valkeinen if (vlwm < 128) vlwm = 128;
783f7018c21STomi Valkeinen data = (int)(clwm);
784f7018c21STomi Valkeinen fifo->graphics_lwm = data;
785f7018c21STomi Valkeinen fifo->graphics_burst_size = 128;
786f7018c21STomi Valkeinen data = (int)((vlwm+15));
787f7018c21STomi Valkeinen fifo->video_lwm = data;
788f7018c21STomi Valkeinen fifo->video_burst_size = vbs;
789f7018c21STomi Valkeinen }
790f7018c21STomi Valkeinen }
nv4UpdateArbitrationSettings(unsigned VClk,unsigned pixelDepth,unsigned * burst,unsigned * lwm,RIVA_HW_INST * chip)791f7018c21STomi Valkeinen static void nv4UpdateArbitrationSettings
792f7018c21STomi Valkeinen (
793f7018c21STomi Valkeinen unsigned VClk,
794f7018c21STomi Valkeinen unsigned pixelDepth,
795f7018c21STomi Valkeinen unsigned *burst,
796f7018c21STomi Valkeinen unsigned *lwm,
797f7018c21STomi Valkeinen RIVA_HW_INST *chip
798f7018c21STomi Valkeinen )
799f7018c21STomi Valkeinen {
800f7018c21STomi Valkeinen nv4_fifo_info fifo_data;
801f7018c21STomi Valkeinen nv4_sim_state sim_data;
802f7018c21STomi Valkeinen unsigned int M, N, P, pll, MClk, NVClk, cfg1;
803f7018c21STomi Valkeinen
804f7018c21STomi Valkeinen pll = NV_RD32(&chip->PRAMDAC0[0x00000504/4], 0);
805f7018c21STomi Valkeinen M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;
806f7018c21STomi Valkeinen MClk = (N * chip->CrystalFreqKHz / M) >> P;
807f7018c21STomi Valkeinen pll = NV_RD32(&chip->PRAMDAC0[0x00000500/4], 0);
808f7018c21STomi Valkeinen M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;
809f7018c21STomi Valkeinen NVClk = (N * chip->CrystalFreqKHz / M) >> P;
810f7018c21STomi Valkeinen cfg1 = NV_RD32(&chip->PFB[0x00000204/4], 0);
811f7018c21STomi Valkeinen sim_data.pix_bpp = (char)pixelDepth;
812f7018c21STomi Valkeinen sim_data.enable_video = 0;
813f7018c21STomi Valkeinen sim_data.enable_mp = 0;
814f7018c21STomi Valkeinen sim_data.memory_width = (NV_RD32(&chip->PEXTDEV[0x00000000/4], 0) & 0x10) ?
815f7018c21STomi Valkeinen 128 : 64;
816f7018c21STomi Valkeinen sim_data.mem_latency = (char)cfg1 & 0x0F;
817f7018c21STomi Valkeinen sim_data.mem_aligned = 1;
818f7018c21STomi Valkeinen sim_data.mem_page_miss = (char)(((cfg1 >> 4) &0x0F) + ((cfg1 >> 31) & 0x01));
819f7018c21STomi Valkeinen sim_data.gr_during_vid = 0;
820f7018c21STomi Valkeinen sim_data.pclk_khz = VClk;
821f7018c21STomi Valkeinen sim_data.mclk_khz = MClk;
822f7018c21STomi Valkeinen sim_data.nvclk_khz = NVClk;
823f7018c21STomi Valkeinen nv4CalcArbitration(&fifo_data, &sim_data);
824f7018c21STomi Valkeinen if (fifo_data.valid)
825f7018c21STomi Valkeinen {
826f7018c21STomi Valkeinen int b = fifo_data.graphics_burst_size >> 4;
827f7018c21STomi Valkeinen *burst = 0;
828f7018c21STomi Valkeinen while (b >>= 1)
829f7018c21STomi Valkeinen (*burst)++;
830f7018c21STomi Valkeinen *lwm = fifo_data.graphics_lwm >> 3;
831f7018c21STomi Valkeinen }
832f7018c21STomi Valkeinen }
nv10CalcArbitration(nv10_fifo_info * fifo,nv10_sim_state * arb)833f7018c21STomi Valkeinen static void nv10CalcArbitration
834f7018c21STomi Valkeinen (
835f7018c21STomi Valkeinen nv10_fifo_info *fifo,
836f7018c21STomi Valkeinen nv10_sim_state *arb
837f7018c21STomi Valkeinen )
838f7018c21STomi Valkeinen {
839*5c7ddcc8SSam Ravnborg int data, pagemiss, width, video_enable, bpp;
840*5c7ddcc8SSam Ravnborg int nvclks, mclks, pclks, vpagemiss, crtpagemiss;
841*5c7ddcc8SSam Ravnborg int nvclk_fill;
842f7018c21STomi Valkeinen int found, mclk_extra, mclk_loop, cbs, m1;
843f7018c21STomi Valkeinen int mclk_freq, pclk_freq, nvclk_freq, mp_enable;
844*5c7ddcc8SSam Ravnborg int us_m, us_m_min, us_n, us_p, crtc_drain_rate;
845*5c7ddcc8SSam Ravnborg int vus_m;
846*5c7ddcc8SSam Ravnborg int vpm_us, us_video, cpm_us, us_crt,clwm;
847f7018c21STomi Valkeinen int clwm_rnd_down;
848*5c7ddcc8SSam Ravnborg int m2us, us_pipe_min, p1clk, p2;
849*5c7ddcc8SSam Ravnborg int min_mclk_extra;
850f7018c21STomi Valkeinen int us_min_mclk_extra;
851f7018c21STomi Valkeinen
852f7018c21STomi Valkeinen fifo->valid = 1;
853f7018c21STomi Valkeinen pclk_freq = arb->pclk_khz; /* freq in KHz */
854f7018c21STomi Valkeinen mclk_freq = arb->mclk_khz;
855f7018c21STomi Valkeinen nvclk_freq = arb->nvclk_khz;
856f7018c21STomi Valkeinen pagemiss = arb->mem_page_miss;
857f7018c21STomi Valkeinen width = arb->memory_width/64;
858f7018c21STomi Valkeinen video_enable = arb->enable_video;
859f7018c21STomi Valkeinen bpp = arb->pix_bpp;
860f7018c21STomi Valkeinen mp_enable = arb->enable_mp;
861f7018c21STomi Valkeinen clwm = 0;
862f7018c21STomi Valkeinen
863f7018c21STomi Valkeinen cbs = 512;
864f7018c21STomi Valkeinen
865f7018c21STomi Valkeinen pclks = 4; /* lwm detect. */
866f7018c21STomi Valkeinen
867f7018c21STomi Valkeinen nvclks = 3; /* lwm -> sync. */
868f7018c21STomi Valkeinen nvclks += 2; /* fbi bus cycles (1 req + 1 busy) */
869f7018c21STomi Valkeinen
870f7018c21STomi Valkeinen mclks = 1; /* 2 edge sync. may be very close to edge so just put one. */
871f7018c21STomi Valkeinen
872f7018c21STomi Valkeinen mclks += 1; /* arb_hp_req */
873f7018c21STomi Valkeinen mclks += 5; /* ap_hp_req tiling pipeline */
874f7018c21STomi Valkeinen
875f7018c21STomi Valkeinen mclks += 2; /* tc_req latency fifo */
876f7018c21STomi Valkeinen mclks += 2; /* fb_cas_n_ memory request to fbio block */
877f7018c21STomi Valkeinen mclks += 7; /* sm_d_rdv data returned from fbio block */
878f7018c21STomi Valkeinen
879f7018c21STomi Valkeinen /* fb.rd.d.Put_gc need to accumulate 256 bits for read */
880f7018c21STomi Valkeinen if (arb->memory_type == 0)
881f7018c21STomi Valkeinen if (arb->memory_width == 64) /* 64 bit bus */
882f7018c21STomi Valkeinen mclks += 4;
883f7018c21STomi Valkeinen else
884f7018c21STomi Valkeinen mclks += 2;
885f7018c21STomi Valkeinen else
886f7018c21STomi Valkeinen if (arb->memory_width == 64) /* 64 bit bus */
887f7018c21STomi Valkeinen mclks += 2;
888f7018c21STomi Valkeinen else
889f7018c21STomi Valkeinen mclks += 1;
890f7018c21STomi Valkeinen
891f7018c21STomi Valkeinen if ((!video_enable) && (arb->memory_width == 128))
892f7018c21STomi Valkeinen {
893f7018c21STomi Valkeinen mclk_extra = (bpp == 32) ? 31 : 42; /* Margin of error */
894f7018c21STomi Valkeinen min_mclk_extra = 17;
895f7018c21STomi Valkeinen }
896f7018c21STomi Valkeinen else
897f7018c21STomi Valkeinen {
898f7018c21STomi Valkeinen mclk_extra = (bpp == 32) ? 8 : 4; /* Margin of error */
899f7018c21STomi Valkeinen /* mclk_extra = 4; */ /* Margin of error */
900f7018c21STomi Valkeinen min_mclk_extra = 18;
901f7018c21STomi Valkeinen }
902f7018c21STomi Valkeinen
903f7018c21STomi Valkeinen nvclks += 1; /* 2 edge sync. may be very close to edge so just put one. */
904f7018c21STomi Valkeinen nvclks += 1; /* fbi_d_rdv_n */
905f7018c21STomi Valkeinen nvclks += 1; /* Fbi_d_rdata */
906f7018c21STomi Valkeinen nvclks += 1; /* crtfifo load */
907f7018c21STomi Valkeinen
908f7018c21STomi Valkeinen if(mp_enable)
909f7018c21STomi Valkeinen mclks+=4; /* Mp can get in with a burst of 8. */
910f7018c21STomi Valkeinen /* Extra clocks determined by heuristics */
911f7018c21STomi Valkeinen
912f7018c21STomi Valkeinen nvclks += 0;
913f7018c21STomi Valkeinen pclks += 0;
914f7018c21STomi Valkeinen found = 0;
915f7018c21STomi Valkeinen while(found != 1) {
916f7018c21STomi Valkeinen fifo->valid = 1;
917f7018c21STomi Valkeinen found = 1;
918f7018c21STomi Valkeinen mclk_loop = mclks+mclk_extra;
919f7018c21STomi Valkeinen us_m = mclk_loop *1000*1000 / mclk_freq; /* Mclk latency in us */
920f7018c21STomi Valkeinen us_m_min = mclks * 1000*1000 / mclk_freq; /* Minimum Mclk latency in us */
921f7018c21STomi Valkeinen us_min_mclk_extra = min_mclk_extra *1000*1000 / mclk_freq;
922f7018c21STomi Valkeinen us_n = nvclks*1000*1000 / nvclk_freq;/* nvclk latency in us */
923f7018c21STomi Valkeinen us_p = pclks*1000*1000 / pclk_freq;/* nvclk latency in us */
924f7018c21STomi Valkeinen us_pipe_min = us_m_min + us_n + us_p;
925f7018c21STomi Valkeinen
926f7018c21STomi Valkeinen vus_m = mclk_loop *1000*1000 / mclk_freq; /* Mclk latency in us */
927f7018c21STomi Valkeinen
928f7018c21STomi Valkeinen if(video_enable) {
929f7018c21STomi Valkeinen crtc_drain_rate = pclk_freq * bpp/8; /* MB/s */
930f7018c21STomi Valkeinen
931f7018c21STomi Valkeinen vpagemiss = 1; /* self generating page miss */
932f7018c21STomi Valkeinen vpagemiss += 1; /* One higher priority before */
933f7018c21STomi Valkeinen
934f7018c21STomi Valkeinen crtpagemiss = 2; /* self generating page miss */
935f7018c21STomi Valkeinen if(mp_enable)
936f7018c21STomi Valkeinen crtpagemiss += 1; /* if MA0 conflict */
937f7018c21STomi Valkeinen
938f7018c21STomi Valkeinen vpm_us = (vpagemiss * pagemiss)*1000*1000/mclk_freq;
939f7018c21STomi Valkeinen
940f7018c21STomi Valkeinen us_video = vpm_us + vus_m; /* Video has separate read return path */
941f7018c21STomi Valkeinen
942f7018c21STomi Valkeinen cpm_us = crtpagemiss * pagemiss *1000*1000/ mclk_freq;
943f7018c21STomi Valkeinen us_crt =
944f7018c21STomi Valkeinen us_video /* Wait for video */
945f7018c21STomi Valkeinen +cpm_us /* CRT Page miss */
946f7018c21STomi Valkeinen +us_m + us_n +us_p /* other latency */
947f7018c21STomi Valkeinen ;
948f7018c21STomi Valkeinen
949f7018c21STomi Valkeinen clwm = us_crt * crtc_drain_rate/(1000*1000);
950f7018c21STomi Valkeinen clwm++; /* fixed point <= float_point - 1. Fixes that */
951f7018c21STomi Valkeinen } else {
952f7018c21STomi Valkeinen crtc_drain_rate = pclk_freq * bpp/8; /* bpp * pclk/8 */
953f7018c21STomi Valkeinen
954f7018c21STomi Valkeinen crtpagemiss = 1; /* self generating page miss */
955f7018c21STomi Valkeinen crtpagemiss += 1; /* MA0 page miss */
956f7018c21STomi Valkeinen if(mp_enable)
957f7018c21STomi Valkeinen crtpagemiss += 1; /* if MA0 conflict */
958f7018c21STomi Valkeinen cpm_us = crtpagemiss * pagemiss *1000*1000/ mclk_freq;
959f7018c21STomi Valkeinen us_crt = cpm_us + us_m + us_n + us_p ;
960f7018c21STomi Valkeinen clwm = us_crt * crtc_drain_rate/(1000*1000);
961f7018c21STomi Valkeinen clwm++; /* fixed point <= float_point - 1. Fixes that */
962f7018c21STomi Valkeinen
963f7018c21STomi Valkeinen /*
964f7018c21STomi Valkeinen //
965f7018c21STomi Valkeinen // Another concern, only for high pclks so don't do this
966f7018c21STomi Valkeinen // with video:
967f7018c21STomi Valkeinen // What happens if the latency to fetch the cbs is so large that
968f7018c21STomi Valkeinen // fifo empties. In that case we need to have an alternate clwm value
969f7018c21STomi Valkeinen // based off the total burst fetch
970f7018c21STomi Valkeinen //
971f7018c21STomi Valkeinen us_crt = (cbs * 1000 * 1000)/ (8*width)/mclk_freq ;
972f7018c21STomi Valkeinen us_crt = us_crt + us_m + us_n + us_p + (4 * 1000 * 1000)/mclk_freq;
973f7018c21STomi Valkeinen clwm_mt = us_crt * crtc_drain_rate/(1000*1000);
974f7018c21STomi Valkeinen clwm_mt ++;
975f7018c21STomi Valkeinen if(clwm_mt > clwm)
976f7018c21STomi Valkeinen clwm = clwm_mt;
977f7018c21STomi Valkeinen */
978f7018c21STomi Valkeinen /* Finally, a heuristic check when width == 64 bits */
979f7018c21STomi Valkeinen if(width == 1){
980f7018c21STomi Valkeinen nvclk_fill = nvclk_freq * 8;
981f7018c21STomi Valkeinen if(crtc_drain_rate * 100 >= nvclk_fill * 102)
982f7018c21STomi Valkeinen clwm = 0xfff; /*Large number to fail */
983f7018c21STomi Valkeinen
984f7018c21STomi Valkeinen else if(crtc_drain_rate * 100 >= nvclk_fill * 98) {
985f7018c21STomi Valkeinen clwm = 1024;
986f7018c21STomi Valkeinen cbs = 512;
987f7018c21STomi Valkeinen }
988f7018c21STomi Valkeinen }
989f7018c21STomi Valkeinen }
990f7018c21STomi Valkeinen
991f7018c21STomi Valkeinen
992f7018c21STomi Valkeinen /*
993f7018c21STomi Valkeinen Overfill check:
994f7018c21STomi Valkeinen
995f7018c21STomi Valkeinen */
996f7018c21STomi Valkeinen
997f7018c21STomi Valkeinen clwm_rnd_down = ((int)clwm/8)*8;
998f7018c21STomi Valkeinen if (clwm_rnd_down < clwm)
999f7018c21STomi Valkeinen clwm += 8;
1000f7018c21STomi Valkeinen
1001f7018c21STomi Valkeinen m1 = clwm + cbs - 1024; /* Amount of overfill */
1002f7018c21STomi Valkeinen m2us = us_pipe_min + us_min_mclk_extra;
1003f7018c21STomi Valkeinen
1004f7018c21STomi Valkeinen /* pclk cycles to drain */
1005f7018c21STomi Valkeinen p1clk = m2us * pclk_freq/(1000*1000);
1006f7018c21STomi Valkeinen p2 = p1clk * bpp / 8; /* bytes drained. */
1007f7018c21STomi Valkeinen
1008f7018c21STomi Valkeinen if((p2 < m1) && (m1 > 0)) {
1009f7018c21STomi Valkeinen fifo->valid = 0;
1010f7018c21STomi Valkeinen found = 0;
1011f7018c21STomi Valkeinen if(min_mclk_extra == 0) {
1012f7018c21STomi Valkeinen if(cbs <= 32) {
1013f7018c21STomi Valkeinen found = 1; /* Can't adjust anymore! */
1014f7018c21STomi Valkeinen } else {
1015f7018c21STomi Valkeinen cbs = cbs/2; /* reduce the burst size */
1016f7018c21STomi Valkeinen }
1017f7018c21STomi Valkeinen } else {
1018f7018c21STomi Valkeinen min_mclk_extra--;
1019f7018c21STomi Valkeinen }
1020f7018c21STomi Valkeinen } else {
1021f7018c21STomi Valkeinen if (clwm > 1023){ /* Have some margin */
1022f7018c21STomi Valkeinen fifo->valid = 0;
1023f7018c21STomi Valkeinen found = 0;
1024f7018c21STomi Valkeinen if(min_mclk_extra == 0)
1025f7018c21STomi Valkeinen found = 1; /* Can't adjust anymore! */
1026f7018c21STomi Valkeinen else
1027f7018c21STomi Valkeinen min_mclk_extra--;
1028f7018c21STomi Valkeinen }
1029f7018c21STomi Valkeinen }
1030f7018c21STomi Valkeinen
1031f7018c21STomi Valkeinen if(clwm < (1024-cbs+8)) clwm = 1024-cbs+8;
1032f7018c21STomi Valkeinen data = (int)(clwm);
1033f7018c21STomi Valkeinen /* printf("CRT LWM: %f bytes, prog: 0x%x, bs: 256\n", clwm, data ); */
1034f7018c21STomi Valkeinen fifo->graphics_lwm = data; fifo->graphics_burst_size = cbs;
1035f7018c21STomi Valkeinen
1036f7018c21STomi Valkeinen /* printf("VID LWM: %f bytes, prog: 0x%x, bs: %d\n, ", vlwm, data, vbs ); */
1037f7018c21STomi Valkeinen fifo->video_lwm = 1024; fifo->video_burst_size = 512;
1038f7018c21STomi Valkeinen }
1039f7018c21STomi Valkeinen }
nv10UpdateArbitrationSettings(unsigned VClk,unsigned pixelDepth,unsigned * burst,unsigned * lwm,RIVA_HW_INST * chip)1040f7018c21STomi Valkeinen static void nv10UpdateArbitrationSettings
1041f7018c21STomi Valkeinen (
1042f7018c21STomi Valkeinen unsigned VClk,
1043f7018c21STomi Valkeinen unsigned pixelDepth,
1044f7018c21STomi Valkeinen unsigned *burst,
1045f7018c21STomi Valkeinen unsigned *lwm,
1046f7018c21STomi Valkeinen RIVA_HW_INST *chip
1047f7018c21STomi Valkeinen )
1048f7018c21STomi Valkeinen {
1049f7018c21STomi Valkeinen nv10_fifo_info fifo_data;
1050f7018c21STomi Valkeinen nv10_sim_state sim_data;
1051f7018c21STomi Valkeinen unsigned int M, N, P, pll, MClk, NVClk, cfg1;
1052f7018c21STomi Valkeinen
1053f7018c21STomi Valkeinen pll = NV_RD32(&chip->PRAMDAC0[0x00000504/4], 0);
1054f7018c21STomi Valkeinen M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;
1055f7018c21STomi Valkeinen MClk = (N * chip->CrystalFreqKHz / M) >> P;
1056f7018c21STomi Valkeinen pll = NV_RD32(&chip->PRAMDAC0[0x00000500/4], 0);
1057f7018c21STomi Valkeinen M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;
1058f7018c21STomi Valkeinen NVClk = (N * chip->CrystalFreqKHz / M) >> P;
1059f7018c21STomi Valkeinen cfg1 = NV_RD32(&chip->PFB[0x00000204/4], 0);
1060f7018c21STomi Valkeinen sim_data.pix_bpp = (char)pixelDepth;
1061f7018c21STomi Valkeinen sim_data.enable_video = 0;
1062f7018c21STomi Valkeinen sim_data.enable_mp = 0;
1063f7018c21STomi Valkeinen sim_data.memory_type = (NV_RD32(&chip->PFB[0x00000200/4], 0) & 0x01) ?
1064f7018c21STomi Valkeinen 1 : 0;
1065f7018c21STomi Valkeinen sim_data.memory_width = (NV_RD32(&chip->PEXTDEV[0x00000000/4], 0) & 0x10) ?
1066f7018c21STomi Valkeinen 128 : 64;
1067f7018c21STomi Valkeinen sim_data.mem_latency = (char)cfg1 & 0x0F;
1068f7018c21STomi Valkeinen sim_data.mem_aligned = 1;
1069f7018c21STomi Valkeinen sim_data.mem_page_miss = (char)(((cfg1 >> 4) &0x0F) + ((cfg1 >> 31) & 0x01));
1070f7018c21STomi Valkeinen sim_data.gr_during_vid = 0;
1071f7018c21STomi Valkeinen sim_data.pclk_khz = VClk;
1072f7018c21STomi Valkeinen sim_data.mclk_khz = MClk;
1073f7018c21STomi Valkeinen sim_data.nvclk_khz = NVClk;
1074f7018c21STomi Valkeinen nv10CalcArbitration(&fifo_data, &sim_data);
1075f7018c21STomi Valkeinen if (fifo_data.valid)
1076f7018c21STomi Valkeinen {
1077f7018c21STomi Valkeinen int b = fifo_data.graphics_burst_size >> 4;
1078f7018c21STomi Valkeinen *burst = 0;
1079f7018c21STomi Valkeinen while (b >>= 1)
1080f7018c21STomi Valkeinen (*burst)++;
1081f7018c21STomi Valkeinen *lwm = fifo_data.graphics_lwm >> 3;
1082f7018c21STomi Valkeinen }
1083f7018c21STomi Valkeinen }
1084f7018c21STomi Valkeinen
nForceUpdateArbitrationSettings(unsigned VClk,unsigned pixelDepth,unsigned * burst,unsigned * lwm,RIVA_HW_INST * chip,struct pci_dev * pdev)1085f7018c21STomi Valkeinen static void nForceUpdateArbitrationSettings
1086f7018c21STomi Valkeinen (
1087f7018c21STomi Valkeinen unsigned VClk,
1088f7018c21STomi Valkeinen unsigned pixelDepth,
1089f7018c21STomi Valkeinen unsigned *burst,
1090f7018c21STomi Valkeinen unsigned *lwm,
1091e2281080SSinan Kaya RIVA_HW_INST *chip,
1092e2281080SSinan Kaya struct pci_dev *pdev
1093f7018c21STomi Valkeinen )
1094f7018c21STomi Valkeinen {
1095f7018c21STomi Valkeinen nv10_fifo_info fifo_data;
1096f7018c21STomi Valkeinen nv10_sim_state sim_data;
1097f7018c21STomi Valkeinen unsigned int M, N, P, pll, MClk, NVClk;
1098f7018c21STomi Valkeinen unsigned int uMClkPostDiv;
1099f7018c21STomi Valkeinen struct pci_dev *dev;
1100e2281080SSinan Kaya int domain = pci_domain_nr(pdev->bus);
1101f7018c21STomi Valkeinen
1102e2281080SSinan Kaya dev = pci_get_domain_bus_and_slot(domain, 0, 3);
1103f7018c21STomi Valkeinen pci_read_config_dword(dev, 0x6C, &uMClkPostDiv);
1104f7018c21STomi Valkeinen pci_dev_put(dev);
1105f7018c21STomi Valkeinen uMClkPostDiv = (uMClkPostDiv >> 8) & 0xf;
1106f7018c21STomi Valkeinen
1107f7018c21STomi Valkeinen if(!uMClkPostDiv) uMClkPostDiv = 4;
1108f7018c21STomi Valkeinen MClk = 400000 / uMClkPostDiv;
1109f7018c21STomi Valkeinen
1110f7018c21STomi Valkeinen pll = NV_RD32(&chip->PRAMDAC0[0x00000500/4], 0);
1111f7018c21STomi Valkeinen M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;
1112f7018c21STomi Valkeinen NVClk = (N * chip->CrystalFreqKHz / M) >> P;
1113f7018c21STomi Valkeinen sim_data.pix_bpp = (char)pixelDepth;
1114f7018c21STomi Valkeinen sim_data.enable_video = 0;
1115f7018c21STomi Valkeinen sim_data.enable_mp = 0;
1116f7018c21STomi Valkeinen
1117e2281080SSinan Kaya dev = pci_get_domain_bus_and_slot(domain, 0, 1);
1118f7018c21STomi Valkeinen pci_read_config_dword(dev, 0x7C, &sim_data.memory_type);
1119f7018c21STomi Valkeinen pci_dev_put(dev);
1120f7018c21STomi Valkeinen sim_data.memory_type = (sim_data.memory_type >> 12) & 1;
1121f7018c21STomi Valkeinen
1122f7018c21STomi Valkeinen sim_data.memory_width = 64;
1123f7018c21STomi Valkeinen sim_data.mem_latency = 3;
1124f7018c21STomi Valkeinen sim_data.mem_aligned = 1;
1125f7018c21STomi Valkeinen sim_data.mem_page_miss = 10;
1126f7018c21STomi Valkeinen sim_data.gr_during_vid = 0;
1127f7018c21STomi Valkeinen sim_data.pclk_khz = VClk;
1128f7018c21STomi Valkeinen sim_data.mclk_khz = MClk;
1129f7018c21STomi Valkeinen sim_data.nvclk_khz = NVClk;
1130f7018c21STomi Valkeinen nv10CalcArbitration(&fifo_data, &sim_data);
1131f7018c21STomi Valkeinen if (fifo_data.valid)
1132f7018c21STomi Valkeinen {
1133f7018c21STomi Valkeinen int b = fifo_data.graphics_burst_size >> 4;
1134f7018c21STomi Valkeinen *burst = 0;
1135f7018c21STomi Valkeinen while (b >>= 1)
1136f7018c21STomi Valkeinen (*burst)++;
1137f7018c21STomi Valkeinen *lwm = fifo_data.graphics_lwm >> 3;
1138f7018c21STomi Valkeinen }
1139f7018c21STomi Valkeinen }
1140f7018c21STomi Valkeinen
1141f7018c21STomi Valkeinen /****************************************************************************\
1142f7018c21STomi Valkeinen * *
1143f7018c21STomi Valkeinen * RIVA Mode State Routines *
1144f7018c21STomi Valkeinen * *
1145f7018c21STomi Valkeinen \****************************************************************************/
1146f7018c21STomi Valkeinen
1147f7018c21STomi Valkeinen /*
1148f7018c21STomi Valkeinen * Calculate the Video Clock parameters for the PLL.
1149f7018c21STomi Valkeinen */
CalcVClock(int clockIn,int * clockOut,int * mOut,int * nOut,int * pOut,RIVA_HW_INST * chip)1150f7018c21STomi Valkeinen static int CalcVClock
1151f7018c21STomi Valkeinen (
1152f7018c21STomi Valkeinen int clockIn,
1153f7018c21STomi Valkeinen int *clockOut,
1154f7018c21STomi Valkeinen int *mOut,
1155f7018c21STomi Valkeinen int *nOut,
1156f7018c21STomi Valkeinen int *pOut,
1157f7018c21STomi Valkeinen RIVA_HW_INST *chip
1158f7018c21STomi Valkeinen )
1159f7018c21STomi Valkeinen {
1160f7018c21STomi Valkeinen unsigned lowM, highM, highP;
1161f7018c21STomi Valkeinen unsigned DeltaNew, DeltaOld;
1162f7018c21STomi Valkeinen unsigned VClk, Freq;
1163f7018c21STomi Valkeinen unsigned M, N, P;
1164f7018c21STomi Valkeinen
1165f7018c21STomi Valkeinen DeltaOld = 0xFFFFFFFF;
1166f7018c21STomi Valkeinen
1167f7018c21STomi Valkeinen VClk = (unsigned)clockIn;
1168f7018c21STomi Valkeinen
1169f7018c21STomi Valkeinen if (chip->CrystalFreqKHz == 13500)
1170f7018c21STomi Valkeinen {
1171f7018c21STomi Valkeinen lowM = 7;
1172f7018c21STomi Valkeinen highM = 13 - (chip->Architecture == NV_ARCH_03);
1173f7018c21STomi Valkeinen }
1174f7018c21STomi Valkeinen else
1175f7018c21STomi Valkeinen {
1176f7018c21STomi Valkeinen lowM = 8;
1177f7018c21STomi Valkeinen highM = 14 - (chip->Architecture == NV_ARCH_03);
1178f7018c21STomi Valkeinen }
1179f7018c21STomi Valkeinen
1180f7018c21STomi Valkeinen highP = 4 - (chip->Architecture == NV_ARCH_03);
1181f7018c21STomi Valkeinen for (P = 0; P <= highP; P ++)
1182f7018c21STomi Valkeinen {
1183f7018c21STomi Valkeinen Freq = VClk << P;
1184f7018c21STomi Valkeinen if ((Freq >= 128000) && (Freq <= chip->MaxVClockFreqKHz))
1185f7018c21STomi Valkeinen {
1186f7018c21STomi Valkeinen for (M = lowM; M <= highM; M++)
1187f7018c21STomi Valkeinen {
1188f7018c21STomi Valkeinen N = (VClk << P) * M / chip->CrystalFreqKHz;
1189f7018c21STomi Valkeinen if(N <= 255) {
1190f7018c21STomi Valkeinen Freq = (chip->CrystalFreqKHz * N / M) >> P;
1191f7018c21STomi Valkeinen if (Freq > VClk)
1192f7018c21STomi Valkeinen DeltaNew = Freq - VClk;
1193f7018c21STomi Valkeinen else
1194f7018c21STomi Valkeinen DeltaNew = VClk - Freq;
1195f7018c21STomi Valkeinen if (DeltaNew < DeltaOld)
1196f7018c21STomi Valkeinen {
1197f7018c21STomi Valkeinen *mOut = M;
1198f7018c21STomi Valkeinen *nOut = N;
1199f7018c21STomi Valkeinen *pOut = P;
1200f7018c21STomi Valkeinen *clockOut = Freq;
1201f7018c21STomi Valkeinen DeltaOld = DeltaNew;
1202f7018c21STomi Valkeinen }
1203f7018c21STomi Valkeinen }
1204f7018c21STomi Valkeinen }
1205f7018c21STomi Valkeinen }
1206f7018c21STomi Valkeinen }
1207f7018c21STomi Valkeinen
1208f7018c21STomi Valkeinen /* non-zero: M/N/P/clock values assigned. zero: error (not set) */
1209f7018c21STomi Valkeinen return (DeltaOld != 0xFFFFFFFF);
1210f7018c21STomi Valkeinen }
1211f7018c21STomi Valkeinen /*
1212f7018c21STomi Valkeinen * Calculate extended mode parameters (SVGA) and save in a
1213f7018c21STomi Valkeinen * mode state structure.
1214f7018c21STomi Valkeinen */
CalcStateExt(RIVA_HW_INST * chip,RIVA_HW_STATE * state,struct pci_dev * pdev,int bpp,int width,int hDisplaySize,int height,int dotClock)1215f7018c21STomi Valkeinen int CalcStateExt
1216f7018c21STomi Valkeinen (
1217f7018c21STomi Valkeinen RIVA_HW_INST *chip,
1218f7018c21STomi Valkeinen RIVA_HW_STATE *state,
1219e2281080SSinan Kaya struct pci_dev *pdev,
1220f7018c21STomi Valkeinen int bpp,
1221f7018c21STomi Valkeinen int width,
1222f7018c21STomi Valkeinen int hDisplaySize,
1223f7018c21STomi Valkeinen int height,
1224f7018c21STomi Valkeinen int dotClock
1225f7018c21STomi Valkeinen )
1226f7018c21STomi Valkeinen {
1227f7018c21STomi Valkeinen int pixelDepth;
12283f649ab7SKees Cook int VClk, m, n, p;
1229f7018c21STomi Valkeinen
1230f7018c21STomi Valkeinen /*
1231f7018c21STomi Valkeinen * Save mode parameters.
1232f7018c21STomi Valkeinen */
1233f7018c21STomi Valkeinen state->bpp = bpp; /* this is not bitsPerPixel, it's 8,15,16,32 */
1234f7018c21STomi Valkeinen state->width = width;
1235f7018c21STomi Valkeinen state->height = height;
1236f7018c21STomi Valkeinen /*
1237f7018c21STomi Valkeinen * Extended RIVA registers.
1238f7018c21STomi Valkeinen */
1239f7018c21STomi Valkeinen pixelDepth = (bpp + 1)/8;
1240f7018c21STomi Valkeinen if (!CalcVClock(dotClock, &VClk, &m, &n, &p, chip))
1241f7018c21STomi Valkeinen return -EINVAL;
1242f7018c21STomi Valkeinen
1243f7018c21STomi Valkeinen switch (chip->Architecture)
1244f7018c21STomi Valkeinen {
1245f7018c21STomi Valkeinen case NV_ARCH_03:
1246f7018c21STomi Valkeinen nv3UpdateArbitrationSettings(VClk,
1247f7018c21STomi Valkeinen pixelDepth * 8,
1248f7018c21STomi Valkeinen &(state->arbitration0),
1249f7018c21STomi Valkeinen &(state->arbitration1),
1250f7018c21STomi Valkeinen chip);
1251f7018c21STomi Valkeinen state->cursor0 = 0x00;
1252f7018c21STomi Valkeinen state->cursor1 = 0x78;
1253f7018c21STomi Valkeinen state->cursor2 = 0x00000000;
1254f7018c21STomi Valkeinen state->pllsel = 0x10010100;
1255f7018c21STomi Valkeinen state->config = ((width + 31)/32)
1256f7018c21STomi Valkeinen | (((pixelDepth > 2) ? 3 : pixelDepth) << 8)
1257f7018c21STomi Valkeinen | 0x1000;
1258f7018c21STomi Valkeinen state->general = 0x00100100;
1259f7018c21STomi Valkeinen state->repaint1 = hDisplaySize < 1280 ? 0x06 : 0x02;
1260f7018c21STomi Valkeinen break;
1261f7018c21STomi Valkeinen case NV_ARCH_04:
1262f7018c21STomi Valkeinen nv4UpdateArbitrationSettings(VClk,
1263f7018c21STomi Valkeinen pixelDepth * 8,
1264f7018c21STomi Valkeinen &(state->arbitration0),
1265f7018c21STomi Valkeinen &(state->arbitration1),
1266f7018c21STomi Valkeinen chip);
1267f7018c21STomi Valkeinen state->cursor0 = 0x00;
1268f7018c21STomi Valkeinen state->cursor1 = 0xFC;
1269f7018c21STomi Valkeinen state->cursor2 = 0x00000000;
1270f7018c21STomi Valkeinen state->pllsel = 0x10000700;
1271f7018c21STomi Valkeinen state->config = 0x00001114;
1272f7018c21STomi Valkeinen state->general = bpp == 16 ? 0x00101100 : 0x00100100;
1273f7018c21STomi Valkeinen state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00;
1274f7018c21STomi Valkeinen break;
1275f7018c21STomi Valkeinen case NV_ARCH_10:
1276f7018c21STomi Valkeinen case NV_ARCH_20:
1277f7018c21STomi Valkeinen case NV_ARCH_30:
1278f7018c21STomi Valkeinen if((chip->Chipset == NV_CHIP_IGEFORCE2) ||
1279f7018c21STomi Valkeinen (chip->Chipset == NV_CHIP_0x01F0))
1280f7018c21STomi Valkeinen {
1281f7018c21STomi Valkeinen nForceUpdateArbitrationSettings(VClk,
1282f7018c21STomi Valkeinen pixelDepth * 8,
1283f7018c21STomi Valkeinen &(state->arbitration0),
1284f7018c21STomi Valkeinen &(state->arbitration1),
1285e2281080SSinan Kaya chip, pdev);
1286f7018c21STomi Valkeinen } else {
1287f7018c21STomi Valkeinen nv10UpdateArbitrationSettings(VClk,
1288f7018c21STomi Valkeinen pixelDepth * 8,
1289f7018c21STomi Valkeinen &(state->arbitration0),
1290f7018c21STomi Valkeinen &(state->arbitration1),
1291f7018c21STomi Valkeinen chip);
1292f7018c21STomi Valkeinen }
1293f7018c21STomi Valkeinen state->cursor0 = 0x80 | (chip->CursorStart >> 17);
1294f7018c21STomi Valkeinen state->cursor1 = (chip->CursorStart >> 11) << 2;
1295f7018c21STomi Valkeinen state->cursor2 = chip->CursorStart >> 24;
1296f7018c21STomi Valkeinen state->pllsel = 0x10000700;
1297f7018c21STomi Valkeinen state->config = NV_RD32(&chip->PFB[0x00000200/4], 0);
1298f7018c21STomi Valkeinen state->general = bpp == 16 ? 0x00101100 : 0x00100100;
1299f7018c21STomi Valkeinen state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00;
1300f7018c21STomi Valkeinen break;
1301f7018c21STomi Valkeinen }
1302f7018c21STomi Valkeinen
1303f7018c21STomi Valkeinen /* Paul Richards: below if block borks things in kernel for some reason */
1304f7018c21STomi Valkeinen /* Tony: Below is needed to set hardware in DirectColor */
1305f7018c21STomi Valkeinen if((bpp != 8) && (chip->Architecture != NV_ARCH_03))
1306f7018c21STomi Valkeinen state->general |= 0x00000030;
1307f7018c21STomi Valkeinen
1308f7018c21STomi Valkeinen state->vpll = (p << 16) | (n << 8) | m;
1309f7018c21STomi Valkeinen state->repaint0 = (((width/8)*pixelDepth) & 0x700) >> 3;
1310f7018c21STomi Valkeinen state->pixel = pixelDepth > 2 ? 3 : pixelDepth;
1311f7018c21STomi Valkeinen state->offset0 =
1312f7018c21STomi Valkeinen state->offset1 =
1313f7018c21STomi Valkeinen state->offset2 =
1314f7018c21STomi Valkeinen state->offset3 = 0;
1315f7018c21STomi Valkeinen state->pitch0 =
1316f7018c21STomi Valkeinen state->pitch1 =
1317f7018c21STomi Valkeinen state->pitch2 =
1318f7018c21STomi Valkeinen state->pitch3 = pixelDepth * width;
1319f7018c21STomi Valkeinen
1320f7018c21STomi Valkeinen return 0;
1321f7018c21STomi Valkeinen }
1322f7018c21STomi Valkeinen /*
1323f7018c21STomi Valkeinen * Load fixed function state and pre-calculated/stored state.
1324f7018c21STomi Valkeinen */
1325f7018c21STomi Valkeinen #define LOAD_FIXED_STATE(tbl,dev) \
1326f7018c21STomi Valkeinen for (i = 0; i < sizeof(tbl##Table##dev)/8; i++) \
1327f7018c21STomi Valkeinen NV_WR32(&chip->dev[tbl##Table##dev[i][0]], 0, tbl##Table##dev[i][1])
1328f7018c21STomi Valkeinen #define LOAD_FIXED_STATE_8BPP(tbl,dev) \
1329f7018c21STomi Valkeinen for (i = 0; i < sizeof(tbl##Table##dev##_8BPP)/8; i++) \
1330f7018c21STomi Valkeinen NV_WR32(&chip->dev[tbl##Table##dev##_8BPP[i][0]], 0, tbl##Table##dev##_8BPP[i][1])
1331f7018c21STomi Valkeinen #define LOAD_FIXED_STATE_15BPP(tbl,dev) \
1332f7018c21STomi Valkeinen for (i = 0; i < sizeof(tbl##Table##dev##_15BPP)/8; i++) \
1333f7018c21STomi Valkeinen NV_WR32(&chip->dev[tbl##Table##dev##_15BPP[i][0]], 0, tbl##Table##dev##_15BPP[i][1])
1334f7018c21STomi Valkeinen #define LOAD_FIXED_STATE_16BPP(tbl,dev) \
1335f7018c21STomi Valkeinen for (i = 0; i < sizeof(tbl##Table##dev##_16BPP)/8; i++) \
1336f7018c21STomi Valkeinen NV_WR32(&chip->dev[tbl##Table##dev##_16BPP[i][0]], 0, tbl##Table##dev##_16BPP[i][1])
1337f7018c21STomi Valkeinen #define LOAD_FIXED_STATE_32BPP(tbl,dev) \
1338f7018c21STomi Valkeinen for (i = 0; i < sizeof(tbl##Table##dev##_32BPP)/8; i++) \
1339f7018c21STomi Valkeinen NV_WR32(&chip->dev[tbl##Table##dev##_32BPP[i][0]], 0, tbl##Table##dev##_32BPP[i][1])
1340f7018c21STomi Valkeinen
UpdateFifoState(RIVA_HW_INST * chip)1341f7018c21STomi Valkeinen static void UpdateFifoState
1342f7018c21STomi Valkeinen (
1343f7018c21STomi Valkeinen RIVA_HW_INST *chip
1344f7018c21STomi Valkeinen )
1345f7018c21STomi Valkeinen {
1346f7018c21STomi Valkeinen int i;
1347f7018c21STomi Valkeinen
1348f7018c21STomi Valkeinen switch (chip->Architecture)
1349f7018c21STomi Valkeinen {
1350f7018c21STomi Valkeinen case NV_ARCH_04:
1351f7018c21STomi Valkeinen LOAD_FIXED_STATE(nv4,FIFO);
1352f7018c21STomi Valkeinen chip->Tri03 = NULL;
1353f7018c21STomi Valkeinen chip->Tri05 = (RivaTexturedTriangle05 __iomem *)&(chip->FIFO[0x0000E000/4]);
1354f7018c21STomi Valkeinen break;
1355f7018c21STomi Valkeinen case NV_ARCH_10:
1356f7018c21STomi Valkeinen case NV_ARCH_20:
1357f7018c21STomi Valkeinen case NV_ARCH_30:
1358f7018c21STomi Valkeinen /*
1359f7018c21STomi Valkeinen * Initialize state for the RivaTriangle3D05 routines.
1360f7018c21STomi Valkeinen */
1361f7018c21STomi Valkeinen LOAD_FIXED_STATE(nv10tri05,PGRAPH);
1362f7018c21STomi Valkeinen LOAD_FIXED_STATE(nv10,FIFO);
1363f7018c21STomi Valkeinen chip->Tri03 = NULL;
1364f7018c21STomi Valkeinen chip->Tri05 = (RivaTexturedTriangle05 __iomem *)&(chip->FIFO[0x0000E000/4]);
1365f7018c21STomi Valkeinen break;
1366f7018c21STomi Valkeinen }
1367f7018c21STomi Valkeinen }
LoadStateExt(RIVA_HW_INST * chip,RIVA_HW_STATE * state)1368f7018c21STomi Valkeinen static void LoadStateExt
1369f7018c21STomi Valkeinen (
1370f7018c21STomi Valkeinen RIVA_HW_INST *chip,
1371f7018c21STomi Valkeinen RIVA_HW_STATE *state
1372f7018c21STomi Valkeinen )
1373f7018c21STomi Valkeinen {
1374f7018c21STomi Valkeinen int i;
1375f7018c21STomi Valkeinen
1376f7018c21STomi Valkeinen /*
1377f7018c21STomi Valkeinen * Load HW fixed function state.
1378f7018c21STomi Valkeinen */
1379f7018c21STomi Valkeinen LOAD_FIXED_STATE(Riva,PMC);
1380f7018c21STomi Valkeinen LOAD_FIXED_STATE(Riva,PTIMER);
1381f7018c21STomi Valkeinen switch (chip->Architecture)
1382f7018c21STomi Valkeinen {
1383f7018c21STomi Valkeinen case NV_ARCH_03:
1384f7018c21STomi Valkeinen /*
1385f7018c21STomi Valkeinen * Make sure frame buffer config gets set before loading PRAMIN.
1386f7018c21STomi Valkeinen */
1387f7018c21STomi Valkeinen NV_WR32(chip->PFB, 0x00000200, state->config);
1388f7018c21STomi Valkeinen LOAD_FIXED_STATE(nv3,PFIFO);
1389f7018c21STomi Valkeinen LOAD_FIXED_STATE(nv3,PRAMIN);
1390f7018c21STomi Valkeinen LOAD_FIXED_STATE(nv3,PGRAPH);
1391f7018c21STomi Valkeinen switch (state->bpp)
1392f7018c21STomi Valkeinen {
1393f7018c21STomi Valkeinen case 15:
1394f7018c21STomi Valkeinen case 16:
1395f7018c21STomi Valkeinen LOAD_FIXED_STATE_15BPP(nv3,PRAMIN);
1396f7018c21STomi Valkeinen LOAD_FIXED_STATE_15BPP(nv3,PGRAPH);
1397f7018c21STomi Valkeinen chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]);
1398f7018c21STomi Valkeinen break;
1399f7018c21STomi Valkeinen case 24:
1400f7018c21STomi Valkeinen case 32:
1401f7018c21STomi Valkeinen LOAD_FIXED_STATE_32BPP(nv3,PRAMIN);
1402f7018c21STomi Valkeinen LOAD_FIXED_STATE_32BPP(nv3,PGRAPH);
1403f7018c21STomi Valkeinen chip->Tri03 = NULL;
1404f7018c21STomi Valkeinen break;
1405f7018c21STomi Valkeinen case 8:
1406f7018c21STomi Valkeinen default:
1407f7018c21STomi Valkeinen LOAD_FIXED_STATE_8BPP(nv3,PRAMIN);
1408f7018c21STomi Valkeinen LOAD_FIXED_STATE_8BPP(nv3,PGRAPH);
1409f7018c21STomi Valkeinen chip->Tri03 = NULL;
1410f7018c21STomi Valkeinen break;
1411f7018c21STomi Valkeinen }
1412f7018c21STomi Valkeinen for (i = 0x00000; i < 0x00800; i++)
1413f7018c21STomi Valkeinen NV_WR32(&chip->PRAMIN[0x00000502 + i], 0, (i << 12) | 0x03);
1414f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000630, state->offset0);
1415f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000634, state->offset1);
1416f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000638, state->offset2);
1417f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x0000063C, state->offset3);
1418f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000650, state->pitch0);
1419f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000654, state->pitch1);
1420f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000658, state->pitch2);
1421f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x0000065C, state->pitch3);
1422f7018c21STomi Valkeinen break;
1423f7018c21STomi Valkeinen case NV_ARCH_04:
1424f7018c21STomi Valkeinen /*
1425f7018c21STomi Valkeinen * Make sure frame buffer config gets set before loading PRAMIN.
1426f7018c21STomi Valkeinen */
1427f7018c21STomi Valkeinen NV_WR32(chip->PFB, 0x00000200, state->config);
1428f7018c21STomi Valkeinen LOAD_FIXED_STATE(nv4,PFIFO);
1429f7018c21STomi Valkeinen LOAD_FIXED_STATE(nv4,PRAMIN);
1430f7018c21STomi Valkeinen LOAD_FIXED_STATE(nv4,PGRAPH);
1431f7018c21STomi Valkeinen switch (state->bpp)
1432f7018c21STomi Valkeinen {
1433f7018c21STomi Valkeinen case 15:
1434f7018c21STomi Valkeinen LOAD_FIXED_STATE_15BPP(nv4,PRAMIN);
1435f7018c21STomi Valkeinen LOAD_FIXED_STATE_15BPP(nv4,PGRAPH);
1436f7018c21STomi Valkeinen chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]);
1437f7018c21STomi Valkeinen break;
1438f7018c21STomi Valkeinen case 16:
1439f7018c21STomi Valkeinen LOAD_FIXED_STATE_16BPP(nv4,PRAMIN);
1440f7018c21STomi Valkeinen LOAD_FIXED_STATE_16BPP(nv4,PGRAPH);
1441f7018c21STomi Valkeinen chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]);
1442f7018c21STomi Valkeinen break;
1443f7018c21STomi Valkeinen case 24:
1444f7018c21STomi Valkeinen case 32:
1445f7018c21STomi Valkeinen LOAD_FIXED_STATE_32BPP(nv4,PRAMIN);
1446f7018c21STomi Valkeinen LOAD_FIXED_STATE_32BPP(nv4,PGRAPH);
1447f7018c21STomi Valkeinen chip->Tri03 = NULL;
1448f7018c21STomi Valkeinen break;
1449f7018c21STomi Valkeinen case 8:
1450f7018c21STomi Valkeinen default:
1451f7018c21STomi Valkeinen LOAD_FIXED_STATE_8BPP(nv4,PRAMIN);
1452f7018c21STomi Valkeinen LOAD_FIXED_STATE_8BPP(nv4,PGRAPH);
1453f7018c21STomi Valkeinen chip->Tri03 = NULL;
1454f7018c21STomi Valkeinen break;
1455f7018c21STomi Valkeinen }
1456f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000640, state->offset0);
1457f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000644, state->offset1);
1458f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000648, state->offset2);
1459f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x0000064C, state->offset3);
1460f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000670, state->pitch0);
1461f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000674, state->pitch1);
1462f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000678, state->pitch2);
1463f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x0000067C, state->pitch3);
1464f7018c21STomi Valkeinen break;
1465f7018c21STomi Valkeinen case NV_ARCH_10:
1466f7018c21STomi Valkeinen case NV_ARCH_20:
1467f7018c21STomi Valkeinen case NV_ARCH_30:
1468f7018c21STomi Valkeinen if(chip->twoHeads) {
1469f7018c21STomi Valkeinen VGA_WR08(chip->PCIO, 0x03D4, 0x44);
1470f7018c21STomi Valkeinen VGA_WR08(chip->PCIO, 0x03D5, state->crtcOwner);
1471f7018c21STomi Valkeinen chip->LockUnlock(chip, 0);
1472f7018c21STomi Valkeinen }
1473f7018c21STomi Valkeinen
1474f7018c21STomi Valkeinen LOAD_FIXED_STATE(nv10,PFIFO);
1475f7018c21STomi Valkeinen LOAD_FIXED_STATE(nv10,PRAMIN);
1476f7018c21STomi Valkeinen LOAD_FIXED_STATE(nv10,PGRAPH);
1477f7018c21STomi Valkeinen switch (state->bpp)
1478f7018c21STomi Valkeinen {
1479f7018c21STomi Valkeinen case 15:
1480f7018c21STomi Valkeinen LOAD_FIXED_STATE_15BPP(nv10,PRAMIN);
1481f7018c21STomi Valkeinen LOAD_FIXED_STATE_15BPP(nv10,PGRAPH);
1482f7018c21STomi Valkeinen chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]);
1483f7018c21STomi Valkeinen break;
1484f7018c21STomi Valkeinen case 16:
1485f7018c21STomi Valkeinen LOAD_FIXED_STATE_16BPP(nv10,PRAMIN);
1486f7018c21STomi Valkeinen LOAD_FIXED_STATE_16BPP(nv10,PGRAPH);
1487f7018c21STomi Valkeinen chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]);
1488f7018c21STomi Valkeinen break;
1489f7018c21STomi Valkeinen case 24:
1490f7018c21STomi Valkeinen case 32:
1491f7018c21STomi Valkeinen LOAD_FIXED_STATE_32BPP(nv10,PRAMIN);
1492f7018c21STomi Valkeinen LOAD_FIXED_STATE_32BPP(nv10,PGRAPH);
1493f7018c21STomi Valkeinen chip->Tri03 = NULL;
1494f7018c21STomi Valkeinen break;
1495f7018c21STomi Valkeinen case 8:
1496f7018c21STomi Valkeinen default:
1497f7018c21STomi Valkeinen LOAD_FIXED_STATE_8BPP(nv10,PRAMIN);
1498f7018c21STomi Valkeinen LOAD_FIXED_STATE_8BPP(nv10,PGRAPH);
1499f7018c21STomi Valkeinen chip->Tri03 = NULL;
1500f7018c21STomi Valkeinen break;
1501f7018c21STomi Valkeinen }
1502f7018c21STomi Valkeinen
1503f7018c21STomi Valkeinen if(chip->Architecture == NV_ARCH_10) {
1504f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000640, state->offset0);
1505f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000644, state->offset1);
1506f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000648, state->offset2);
1507f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x0000064C, state->offset3);
1508f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000670, state->pitch0);
1509f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000674, state->pitch1);
1510f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000678, state->pitch2);
1511f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x0000067C, state->pitch3);
1512f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000680, state->pitch3);
1513f7018c21STomi Valkeinen } else {
1514f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000820, state->offset0);
1515f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000824, state->offset1);
1516f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000828, state->offset2);
1517f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x0000082C, state->offset3);
1518f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000850, state->pitch0);
1519f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000854, state->pitch1);
1520f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000858, state->pitch2);
1521f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x0000085C, state->pitch3);
1522f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000860, state->pitch3);
1523f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000864, state->pitch3);
1524f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x000009A4, NV_RD32(chip->PFB, 0x00000200));
1525f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x000009A8, NV_RD32(chip->PFB, 0x00000204));
1526f7018c21STomi Valkeinen }
1527f7018c21STomi Valkeinen if(chip->twoHeads) {
1528f7018c21STomi Valkeinen NV_WR32(chip->PCRTC0, 0x00000860, state->head);
1529f7018c21STomi Valkeinen NV_WR32(chip->PCRTC0, 0x00002860, state->head2);
1530f7018c21STomi Valkeinen }
1531f7018c21STomi Valkeinen NV_WR32(chip->PRAMDAC, 0x00000404, NV_RD32(chip->PRAMDAC, 0x00000404) | (1 << 25));
1532f7018c21STomi Valkeinen
1533f7018c21STomi Valkeinen NV_WR32(chip->PMC, 0x00008704, 1);
1534f7018c21STomi Valkeinen NV_WR32(chip->PMC, 0x00008140, 0);
1535f7018c21STomi Valkeinen NV_WR32(chip->PMC, 0x00008920, 0);
1536f7018c21STomi Valkeinen NV_WR32(chip->PMC, 0x00008924, 0);
1537f7018c21STomi Valkeinen NV_WR32(chip->PMC, 0x00008908, 0x01ffffff);
1538f7018c21STomi Valkeinen NV_WR32(chip->PMC, 0x0000890C, 0x01ffffff);
1539f7018c21STomi Valkeinen NV_WR32(chip->PMC, 0x00001588, 0);
1540f7018c21STomi Valkeinen
1541f7018c21STomi Valkeinen NV_WR32(chip->PFB, 0x00000240, 0);
1542f7018c21STomi Valkeinen NV_WR32(chip->PFB, 0x00000250, 0);
1543f7018c21STomi Valkeinen NV_WR32(chip->PFB, 0x00000260, 0);
1544f7018c21STomi Valkeinen NV_WR32(chip->PFB, 0x00000270, 0);
1545f7018c21STomi Valkeinen NV_WR32(chip->PFB, 0x00000280, 0);
1546f7018c21STomi Valkeinen NV_WR32(chip->PFB, 0x00000290, 0);
1547f7018c21STomi Valkeinen NV_WR32(chip->PFB, 0x000002A0, 0);
1548f7018c21STomi Valkeinen NV_WR32(chip->PFB, 0x000002B0, 0);
1549f7018c21STomi Valkeinen
1550f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000B00, NV_RD32(chip->PFB, 0x00000240));
1551f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000B04, NV_RD32(chip->PFB, 0x00000244));
1552f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000B08, NV_RD32(chip->PFB, 0x00000248));
1553f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000B0C, NV_RD32(chip->PFB, 0x0000024C));
1554f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000B10, NV_RD32(chip->PFB, 0x00000250));
1555f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000B14, NV_RD32(chip->PFB, 0x00000254));
1556f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000B18, NV_RD32(chip->PFB, 0x00000258));
1557f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000B1C, NV_RD32(chip->PFB, 0x0000025C));
1558f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000B20, NV_RD32(chip->PFB, 0x00000260));
1559f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000B24, NV_RD32(chip->PFB, 0x00000264));
1560f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000B28, NV_RD32(chip->PFB, 0x00000268));
1561f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000B2C, NV_RD32(chip->PFB, 0x0000026C));
1562f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000B30, NV_RD32(chip->PFB, 0x00000270));
1563f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000B34, NV_RD32(chip->PFB, 0x00000274));
1564f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000B38, NV_RD32(chip->PFB, 0x00000278));
1565f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000B3C, NV_RD32(chip->PFB, 0x0000027C));
1566f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000B40, NV_RD32(chip->PFB, 0x00000280));
1567f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000B44, NV_RD32(chip->PFB, 0x00000284));
1568f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000B48, NV_RD32(chip->PFB, 0x00000288));
1569f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000B4C, NV_RD32(chip->PFB, 0x0000028C));
1570f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000B50, NV_RD32(chip->PFB, 0x00000290));
1571f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000B54, NV_RD32(chip->PFB, 0x00000294));
1572f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000B58, NV_RD32(chip->PFB, 0x00000298));
1573f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000B5C, NV_RD32(chip->PFB, 0x0000029C));
1574f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000B60, NV_RD32(chip->PFB, 0x000002A0));
1575f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000B64, NV_RD32(chip->PFB, 0x000002A4));
1576f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000B68, NV_RD32(chip->PFB, 0x000002A8));
1577f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000B6C, NV_RD32(chip->PFB, 0x000002AC));
1578f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000B70, NV_RD32(chip->PFB, 0x000002B0));
1579f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000B74, NV_RD32(chip->PFB, 0x000002B4));
1580f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000B78, NV_RD32(chip->PFB, 0x000002B8));
1581f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000B7C, NV_RD32(chip->PFB, 0x000002BC));
1582f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000F40, 0x10000000);
1583f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000F44, 0x00000000);
1584f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000040);
1585f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000008);
1586f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000200);
1587f7018c21STomi Valkeinen for (i = 0; i < (3*16); i++)
1588f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
1589f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000040);
1590f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
1591f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000800);
1592f7018c21STomi Valkeinen for (i = 0; i < (16*16); i++)
1593f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
1594f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000F40, 0x30000000);
1595f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000F44, 0x00000004);
1596f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000F50, 0x00006400);
1597f7018c21STomi Valkeinen for (i = 0; i < (59*4); i++)
1598f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
1599f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000F50, 0x00006800);
1600f7018c21STomi Valkeinen for (i = 0; i < (47*4); i++)
1601f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
1602f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000F50, 0x00006C00);
1603f7018c21STomi Valkeinen for (i = 0; i < (3*4); i++)
1604f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
1605f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000F50, 0x00007000);
1606f7018c21STomi Valkeinen for (i = 0; i < (19*4); i++)
1607f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
1608f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000F50, 0x00007400);
1609f7018c21STomi Valkeinen for (i = 0; i < (12*4); i++)
1610f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
1611f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000F50, 0x00007800);
1612f7018c21STomi Valkeinen for (i = 0; i < (12*4); i++)
1613f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
1614f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000F50, 0x00004400);
1615f7018c21STomi Valkeinen for (i = 0; i < (8*4); i++)
1616f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
1617f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000000);
1618f7018c21STomi Valkeinen for (i = 0; i < 16; i++)
1619f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
1620f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000040);
1621f7018c21STomi Valkeinen for (i = 0; i < 4; i++)
1622f7018c21STomi Valkeinen NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
1623f7018c21STomi Valkeinen
1624f7018c21STomi Valkeinen NV_WR32(chip->PCRTC, 0x00000810, state->cursorConfig);
1625f7018c21STomi Valkeinen
1626f7018c21STomi Valkeinen if(chip->flatPanel) {
1627f7018c21STomi Valkeinen if((chip->Chipset & 0x0ff0) == 0x0110) {
1628f7018c21STomi Valkeinen NV_WR32(chip->PRAMDAC, 0x0528, state->dither);
1629f7018c21STomi Valkeinen } else
1630f7018c21STomi Valkeinen if((chip->Chipset & 0x0ff0) >= 0x0170) {
1631f7018c21STomi Valkeinen NV_WR32(chip->PRAMDAC, 0x083C, state->dither);
1632f7018c21STomi Valkeinen }
1633f7018c21STomi Valkeinen
1634f7018c21STomi Valkeinen VGA_WR08(chip->PCIO, 0x03D4, 0x53);
1635f7018c21STomi Valkeinen VGA_WR08(chip->PCIO, 0x03D5, 0);
1636f7018c21STomi Valkeinen VGA_WR08(chip->PCIO, 0x03D4, 0x54);
1637f7018c21STomi Valkeinen VGA_WR08(chip->PCIO, 0x03D5, 0);
1638f7018c21STomi Valkeinen VGA_WR08(chip->PCIO, 0x03D4, 0x21);
1639f7018c21STomi Valkeinen VGA_WR08(chip->PCIO, 0x03D5, 0xfa);
1640f7018c21STomi Valkeinen }
1641f7018c21STomi Valkeinen
1642f7018c21STomi Valkeinen VGA_WR08(chip->PCIO, 0x03D4, 0x41);
1643f7018c21STomi Valkeinen VGA_WR08(chip->PCIO, 0x03D5, state->extra);
1644f7018c21STomi Valkeinen }
1645f7018c21STomi Valkeinen LOAD_FIXED_STATE(Riva,FIFO);
1646f7018c21STomi Valkeinen UpdateFifoState(chip);
1647f7018c21STomi Valkeinen /*
1648f7018c21STomi Valkeinen * Load HW mode state.
1649f7018c21STomi Valkeinen */
1650f7018c21STomi Valkeinen VGA_WR08(chip->PCIO, 0x03D4, 0x19);
1651f7018c21STomi Valkeinen VGA_WR08(chip->PCIO, 0x03D5, state->repaint0);
1652f7018c21STomi Valkeinen VGA_WR08(chip->PCIO, 0x03D4, 0x1A);
1653f7018c21STomi Valkeinen VGA_WR08(chip->PCIO, 0x03D5, state->repaint1);
1654f7018c21STomi Valkeinen VGA_WR08(chip->PCIO, 0x03D4, 0x25);
1655f7018c21STomi Valkeinen VGA_WR08(chip->PCIO, 0x03D5, state->screen);
1656f7018c21STomi Valkeinen VGA_WR08(chip->PCIO, 0x03D4, 0x28);
1657f7018c21STomi Valkeinen VGA_WR08(chip->PCIO, 0x03D5, state->pixel);
1658f7018c21STomi Valkeinen VGA_WR08(chip->PCIO, 0x03D4, 0x2D);
1659f7018c21STomi Valkeinen VGA_WR08(chip->PCIO, 0x03D5, state->horiz);
1660f7018c21STomi Valkeinen VGA_WR08(chip->PCIO, 0x03D4, 0x1B);
1661f7018c21STomi Valkeinen VGA_WR08(chip->PCIO, 0x03D5, state->arbitration0);
1662f7018c21STomi Valkeinen VGA_WR08(chip->PCIO, 0x03D4, 0x20);
1663f7018c21STomi Valkeinen VGA_WR08(chip->PCIO, 0x03D5, state->arbitration1);
1664f7018c21STomi Valkeinen VGA_WR08(chip->PCIO, 0x03D4, 0x30);
1665f7018c21STomi Valkeinen VGA_WR08(chip->PCIO, 0x03D5, state->cursor0);
1666f7018c21STomi Valkeinen VGA_WR08(chip->PCIO, 0x03D4, 0x31);
1667f7018c21STomi Valkeinen VGA_WR08(chip->PCIO, 0x03D5, state->cursor1);
1668f7018c21STomi Valkeinen VGA_WR08(chip->PCIO, 0x03D4, 0x2F);
1669f7018c21STomi Valkeinen VGA_WR08(chip->PCIO, 0x03D5, state->cursor2);
1670f7018c21STomi Valkeinen VGA_WR08(chip->PCIO, 0x03D4, 0x39);
1671f7018c21STomi Valkeinen VGA_WR08(chip->PCIO, 0x03D5, state->interlace);
1672f7018c21STomi Valkeinen
1673f7018c21STomi Valkeinen if(!chip->flatPanel) {
1674f7018c21STomi Valkeinen NV_WR32(chip->PRAMDAC0, 0x00000508, state->vpll);
1675f7018c21STomi Valkeinen NV_WR32(chip->PRAMDAC0, 0x0000050C, state->pllsel);
1676f7018c21STomi Valkeinen if(chip->twoHeads)
1677f7018c21STomi Valkeinen NV_WR32(chip->PRAMDAC0, 0x00000520, state->vpll2);
1678f7018c21STomi Valkeinen } else {
1679f7018c21STomi Valkeinen NV_WR32(chip->PRAMDAC, 0x00000848 , state->scale);
1680f7018c21STomi Valkeinen }
1681f7018c21STomi Valkeinen NV_WR32(chip->PRAMDAC, 0x00000600 , state->general);
1682f7018c21STomi Valkeinen
1683f7018c21STomi Valkeinen /*
1684f7018c21STomi Valkeinen * Turn off VBlank enable and reset.
1685f7018c21STomi Valkeinen */
1686f7018c21STomi Valkeinen NV_WR32(chip->PCRTC, 0x00000140, 0);
1687f7018c21STomi Valkeinen NV_WR32(chip->PCRTC, 0x00000100, chip->VBlankBit);
1688f7018c21STomi Valkeinen /*
1689f7018c21STomi Valkeinen * Set interrupt enable.
1690f7018c21STomi Valkeinen */
1691f7018c21STomi Valkeinen NV_WR32(chip->PMC, 0x00000140, chip->EnableIRQ & 0x01);
1692f7018c21STomi Valkeinen /*
1693f7018c21STomi Valkeinen * Set current state pointer.
1694f7018c21STomi Valkeinen */
1695f7018c21STomi Valkeinen chip->CurrentState = state;
1696f7018c21STomi Valkeinen /*
1697f7018c21STomi Valkeinen * Reset FIFO free and empty counts.
1698f7018c21STomi Valkeinen */
1699f7018c21STomi Valkeinen chip->FifoFreeCount = 0;
1700f7018c21STomi Valkeinen /* Free count from first subchannel */
1701f7018c21STomi Valkeinen chip->FifoEmptyCount = NV_RD32(&chip->Rop->FifoFree, 0);
1702f7018c21STomi Valkeinen }
UnloadStateExt(RIVA_HW_INST * chip,RIVA_HW_STATE * state)1703f7018c21STomi Valkeinen static void UnloadStateExt
1704f7018c21STomi Valkeinen (
1705f7018c21STomi Valkeinen RIVA_HW_INST *chip,
1706f7018c21STomi Valkeinen RIVA_HW_STATE *state
1707f7018c21STomi Valkeinen )
1708f7018c21STomi Valkeinen {
1709f7018c21STomi Valkeinen /*
1710f7018c21STomi Valkeinen * Save current HW state.
1711f7018c21STomi Valkeinen */
1712f7018c21STomi Valkeinen VGA_WR08(chip->PCIO, 0x03D4, 0x19);
1713f7018c21STomi Valkeinen state->repaint0 = VGA_RD08(chip->PCIO, 0x03D5);
1714f7018c21STomi Valkeinen VGA_WR08(chip->PCIO, 0x03D4, 0x1A);
1715f7018c21STomi Valkeinen state->repaint1 = VGA_RD08(chip->PCIO, 0x03D5);
1716f7018c21STomi Valkeinen VGA_WR08(chip->PCIO, 0x03D4, 0x25);
1717f7018c21STomi Valkeinen state->screen = VGA_RD08(chip->PCIO, 0x03D5);
1718f7018c21STomi Valkeinen VGA_WR08(chip->PCIO, 0x03D4, 0x28);
1719f7018c21STomi Valkeinen state->pixel = VGA_RD08(chip->PCIO, 0x03D5);
1720f7018c21STomi Valkeinen VGA_WR08(chip->PCIO, 0x03D4, 0x2D);
1721f7018c21STomi Valkeinen state->horiz = VGA_RD08(chip->PCIO, 0x03D5);
1722f7018c21STomi Valkeinen VGA_WR08(chip->PCIO, 0x03D4, 0x1B);
1723f7018c21STomi Valkeinen state->arbitration0 = VGA_RD08(chip->PCIO, 0x03D5);
1724f7018c21STomi Valkeinen VGA_WR08(chip->PCIO, 0x03D4, 0x20);
1725f7018c21STomi Valkeinen state->arbitration1 = VGA_RD08(chip->PCIO, 0x03D5);
1726f7018c21STomi Valkeinen VGA_WR08(chip->PCIO, 0x03D4, 0x30);
1727f7018c21STomi Valkeinen state->cursor0 = VGA_RD08(chip->PCIO, 0x03D5);
1728f7018c21STomi Valkeinen VGA_WR08(chip->PCIO, 0x03D4, 0x31);
1729f7018c21STomi Valkeinen state->cursor1 = VGA_RD08(chip->PCIO, 0x03D5);
1730f7018c21STomi Valkeinen VGA_WR08(chip->PCIO, 0x03D4, 0x2F);
1731f7018c21STomi Valkeinen state->cursor2 = VGA_RD08(chip->PCIO, 0x03D5);
1732f7018c21STomi Valkeinen VGA_WR08(chip->PCIO, 0x03D4, 0x39);
1733f7018c21STomi Valkeinen state->interlace = VGA_RD08(chip->PCIO, 0x03D5);
1734f7018c21STomi Valkeinen state->vpll = NV_RD32(chip->PRAMDAC0, 0x00000508);
1735f7018c21STomi Valkeinen state->vpll2 = NV_RD32(chip->PRAMDAC0, 0x00000520);
1736f7018c21STomi Valkeinen state->pllsel = NV_RD32(chip->PRAMDAC0, 0x0000050C);
1737f7018c21STomi Valkeinen state->general = NV_RD32(chip->PRAMDAC, 0x00000600);
1738f7018c21STomi Valkeinen state->scale = NV_RD32(chip->PRAMDAC, 0x00000848);
1739f7018c21STomi Valkeinen state->config = NV_RD32(chip->PFB, 0x00000200);
1740f7018c21STomi Valkeinen switch (chip->Architecture)
1741f7018c21STomi Valkeinen {
1742f7018c21STomi Valkeinen case NV_ARCH_03:
1743f7018c21STomi Valkeinen state->offset0 = NV_RD32(chip->PGRAPH, 0x00000630);
1744f7018c21STomi Valkeinen state->offset1 = NV_RD32(chip->PGRAPH, 0x00000634);
1745f7018c21STomi Valkeinen state->offset2 = NV_RD32(chip->PGRAPH, 0x00000638);
1746f7018c21STomi Valkeinen state->offset3 = NV_RD32(chip->PGRAPH, 0x0000063C);
1747f7018c21STomi Valkeinen state->pitch0 = NV_RD32(chip->PGRAPH, 0x00000650);
1748f7018c21STomi Valkeinen state->pitch1 = NV_RD32(chip->PGRAPH, 0x00000654);
1749f7018c21STomi Valkeinen state->pitch2 = NV_RD32(chip->PGRAPH, 0x00000658);
1750f7018c21STomi Valkeinen state->pitch3 = NV_RD32(chip->PGRAPH, 0x0000065C);
1751f7018c21STomi Valkeinen break;
1752f7018c21STomi Valkeinen case NV_ARCH_04:
1753f7018c21STomi Valkeinen state->offset0 = NV_RD32(chip->PGRAPH, 0x00000640);
1754f7018c21STomi Valkeinen state->offset1 = NV_RD32(chip->PGRAPH, 0x00000644);
1755f7018c21STomi Valkeinen state->offset2 = NV_RD32(chip->PGRAPH, 0x00000648);
1756f7018c21STomi Valkeinen state->offset3 = NV_RD32(chip->PGRAPH, 0x0000064C);
1757f7018c21STomi Valkeinen state->pitch0 = NV_RD32(chip->PGRAPH, 0x00000670);
1758f7018c21STomi Valkeinen state->pitch1 = NV_RD32(chip->PGRAPH, 0x00000674);
1759f7018c21STomi Valkeinen state->pitch2 = NV_RD32(chip->PGRAPH, 0x00000678);
1760f7018c21STomi Valkeinen state->pitch3 = NV_RD32(chip->PGRAPH, 0x0000067C);
1761f7018c21STomi Valkeinen break;
1762f7018c21STomi Valkeinen case NV_ARCH_10:
1763f7018c21STomi Valkeinen case NV_ARCH_20:
1764f7018c21STomi Valkeinen case NV_ARCH_30:
1765f7018c21STomi Valkeinen state->offset0 = NV_RD32(chip->PGRAPH, 0x00000640);
1766f7018c21STomi Valkeinen state->offset1 = NV_RD32(chip->PGRAPH, 0x00000644);
1767f7018c21STomi Valkeinen state->offset2 = NV_RD32(chip->PGRAPH, 0x00000648);
1768f7018c21STomi Valkeinen state->offset3 = NV_RD32(chip->PGRAPH, 0x0000064C);
1769f7018c21STomi Valkeinen state->pitch0 = NV_RD32(chip->PGRAPH, 0x00000670);
1770f7018c21STomi Valkeinen state->pitch1 = NV_RD32(chip->PGRAPH, 0x00000674);
1771f7018c21STomi Valkeinen state->pitch2 = NV_RD32(chip->PGRAPH, 0x00000678);
1772f7018c21STomi Valkeinen state->pitch3 = NV_RD32(chip->PGRAPH, 0x0000067C);
1773f7018c21STomi Valkeinen if(chip->twoHeads) {
1774f7018c21STomi Valkeinen state->head = NV_RD32(chip->PCRTC0, 0x00000860);
1775f7018c21STomi Valkeinen state->head2 = NV_RD32(chip->PCRTC0, 0x00002860);
1776f7018c21STomi Valkeinen VGA_WR08(chip->PCIO, 0x03D4, 0x44);
1777f7018c21STomi Valkeinen state->crtcOwner = VGA_RD08(chip->PCIO, 0x03D5);
1778f7018c21STomi Valkeinen }
1779f7018c21STomi Valkeinen VGA_WR08(chip->PCIO, 0x03D4, 0x41);
1780f7018c21STomi Valkeinen state->extra = VGA_RD08(chip->PCIO, 0x03D5);
1781f7018c21STomi Valkeinen state->cursorConfig = NV_RD32(chip->PCRTC, 0x00000810);
1782f7018c21STomi Valkeinen
1783f7018c21STomi Valkeinen if((chip->Chipset & 0x0ff0) == 0x0110) {
1784f7018c21STomi Valkeinen state->dither = NV_RD32(chip->PRAMDAC, 0x0528);
1785f7018c21STomi Valkeinen } else
1786f7018c21STomi Valkeinen if((chip->Chipset & 0x0ff0) >= 0x0170) {
1787f7018c21STomi Valkeinen state->dither = NV_RD32(chip->PRAMDAC, 0x083C);
1788f7018c21STomi Valkeinen }
1789f7018c21STomi Valkeinen break;
1790f7018c21STomi Valkeinen }
1791f7018c21STomi Valkeinen }
SetStartAddress(RIVA_HW_INST * chip,unsigned start)1792f7018c21STomi Valkeinen static void SetStartAddress
1793f7018c21STomi Valkeinen (
1794f7018c21STomi Valkeinen RIVA_HW_INST *chip,
1795f7018c21STomi Valkeinen unsigned start
1796f7018c21STomi Valkeinen )
1797f7018c21STomi Valkeinen {
1798f7018c21STomi Valkeinen NV_WR32(chip->PCRTC, 0x800, start);
1799f7018c21STomi Valkeinen }
1800f7018c21STomi Valkeinen
SetStartAddress3(RIVA_HW_INST * chip,unsigned start)1801f7018c21STomi Valkeinen static void SetStartAddress3
1802f7018c21STomi Valkeinen (
1803f7018c21STomi Valkeinen RIVA_HW_INST *chip,
1804f7018c21STomi Valkeinen unsigned start
1805f7018c21STomi Valkeinen )
1806f7018c21STomi Valkeinen {
1807f7018c21STomi Valkeinen int offset = start >> 2;
1808f7018c21STomi Valkeinen int pan = (start & 3) << 1;
1809f7018c21STomi Valkeinen unsigned char tmp;
1810f7018c21STomi Valkeinen
1811f7018c21STomi Valkeinen /*
1812f7018c21STomi Valkeinen * Unlock extended registers.
1813f7018c21STomi Valkeinen */
1814f7018c21STomi Valkeinen chip->LockUnlock(chip, 0);
1815f7018c21STomi Valkeinen /*
1816f7018c21STomi Valkeinen * Set start address.
1817f7018c21STomi Valkeinen */
1818f7018c21STomi Valkeinen VGA_WR08(chip->PCIO, 0x3D4, 0x0D); VGA_WR08(chip->PCIO, 0x3D5, offset);
1819f7018c21STomi Valkeinen offset >>= 8;
1820f7018c21STomi Valkeinen VGA_WR08(chip->PCIO, 0x3D4, 0x0C); VGA_WR08(chip->PCIO, 0x3D5, offset);
1821f7018c21STomi Valkeinen offset >>= 8;
1822f7018c21STomi Valkeinen VGA_WR08(chip->PCIO, 0x3D4, 0x19); tmp = VGA_RD08(chip->PCIO, 0x3D5);
1823f7018c21STomi Valkeinen VGA_WR08(chip->PCIO, 0x3D5, (offset & 0x01F) | (tmp & ~0x1F));
1824f7018c21STomi Valkeinen VGA_WR08(chip->PCIO, 0x3D4, 0x2D); tmp = VGA_RD08(chip->PCIO, 0x3D5);
1825f7018c21STomi Valkeinen VGA_WR08(chip->PCIO, 0x3D5, (offset & 0x60) | (tmp & ~0x60));
1826f7018c21STomi Valkeinen /*
1827f7018c21STomi Valkeinen * 4 pixel pan register.
1828f7018c21STomi Valkeinen */
1829f7018c21STomi Valkeinen offset = VGA_RD08(chip->PCIO, chip->IO + 0x0A);
1830f7018c21STomi Valkeinen VGA_WR08(chip->PCIO, 0x3C0, 0x13);
1831f7018c21STomi Valkeinen VGA_WR08(chip->PCIO, 0x3C0, pan);
1832f7018c21STomi Valkeinen }
nv3SetSurfaces2D(RIVA_HW_INST * chip,unsigned surf0,unsigned surf1)1833f7018c21STomi Valkeinen static void nv3SetSurfaces2D
1834f7018c21STomi Valkeinen (
1835f7018c21STomi Valkeinen RIVA_HW_INST *chip,
1836f7018c21STomi Valkeinen unsigned surf0,
1837f7018c21STomi Valkeinen unsigned surf1
1838f7018c21STomi Valkeinen )
1839f7018c21STomi Valkeinen {
1840f7018c21STomi Valkeinen RivaSurface __iomem *Surface =
1841f7018c21STomi Valkeinen (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]);
1842f7018c21STomi Valkeinen
1843f7018c21STomi Valkeinen RIVA_FIFO_FREE(*chip,Tri03,5);
1844f7018c21STomi Valkeinen NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000003);
1845f7018c21STomi Valkeinen NV_WR32(&Surface->Offset, 0, surf0);
1846f7018c21STomi Valkeinen NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000004);
1847f7018c21STomi Valkeinen NV_WR32(&Surface->Offset, 0, surf1);
1848f7018c21STomi Valkeinen NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000013);
1849f7018c21STomi Valkeinen }
nv4SetSurfaces2D(RIVA_HW_INST * chip,unsigned surf0,unsigned surf1)1850f7018c21STomi Valkeinen static void nv4SetSurfaces2D
1851f7018c21STomi Valkeinen (
1852f7018c21STomi Valkeinen RIVA_HW_INST *chip,
1853f7018c21STomi Valkeinen unsigned surf0,
1854f7018c21STomi Valkeinen unsigned surf1
1855f7018c21STomi Valkeinen )
1856f7018c21STomi Valkeinen {
1857f7018c21STomi Valkeinen RivaSurface __iomem *Surface =
1858f7018c21STomi Valkeinen (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]);
1859f7018c21STomi Valkeinen
1860f7018c21STomi Valkeinen NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000003);
1861f7018c21STomi Valkeinen NV_WR32(&Surface->Offset, 0, surf0);
1862f7018c21STomi Valkeinen NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000004);
1863f7018c21STomi Valkeinen NV_WR32(&Surface->Offset, 0, surf1);
1864f7018c21STomi Valkeinen NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000014);
1865f7018c21STomi Valkeinen }
nv10SetSurfaces2D(RIVA_HW_INST * chip,unsigned surf0,unsigned surf1)1866f7018c21STomi Valkeinen static void nv10SetSurfaces2D
1867f7018c21STomi Valkeinen (
1868f7018c21STomi Valkeinen RIVA_HW_INST *chip,
1869f7018c21STomi Valkeinen unsigned surf0,
1870f7018c21STomi Valkeinen unsigned surf1
1871f7018c21STomi Valkeinen )
1872f7018c21STomi Valkeinen {
1873f7018c21STomi Valkeinen RivaSurface __iomem *Surface =
1874f7018c21STomi Valkeinen (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]);
1875f7018c21STomi Valkeinen
1876f7018c21STomi Valkeinen NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000003);
1877f7018c21STomi Valkeinen NV_WR32(&Surface->Offset, 0, surf0);
1878f7018c21STomi Valkeinen NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000004);
1879f7018c21STomi Valkeinen NV_WR32(&Surface->Offset, 0, surf1);
1880f7018c21STomi Valkeinen NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000014);
1881f7018c21STomi Valkeinen }
nv3SetSurfaces3D(RIVA_HW_INST * chip,unsigned surf0,unsigned surf1)1882f7018c21STomi Valkeinen static void nv3SetSurfaces3D
1883f7018c21STomi Valkeinen (
1884f7018c21STomi Valkeinen RIVA_HW_INST *chip,
1885f7018c21STomi Valkeinen unsigned surf0,
1886f7018c21STomi Valkeinen unsigned surf1
1887f7018c21STomi Valkeinen )
1888f7018c21STomi Valkeinen {
1889f7018c21STomi Valkeinen RivaSurface __iomem *Surface =
1890f7018c21STomi Valkeinen (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]);
1891f7018c21STomi Valkeinen
1892f7018c21STomi Valkeinen RIVA_FIFO_FREE(*chip,Tri03,5);
1893f7018c21STomi Valkeinen NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000005);
1894f7018c21STomi Valkeinen NV_WR32(&Surface->Offset, 0, surf0);
1895f7018c21STomi Valkeinen NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000006);
1896f7018c21STomi Valkeinen NV_WR32(&Surface->Offset, 0, surf1);
1897f7018c21STomi Valkeinen NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000013);
1898f7018c21STomi Valkeinen }
nv4SetSurfaces3D(RIVA_HW_INST * chip,unsigned surf0,unsigned surf1)1899f7018c21STomi Valkeinen static void nv4SetSurfaces3D
1900f7018c21STomi Valkeinen (
1901f7018c21STomi Valkeinen RIVA_HW_INST *chip,
1902f7018c21STomi Valkeinen unsigned surf0,
1903f7018c21STomi Valkeinen unsigned surf1
1904f7018c21STomi Valkeinen )
1905f7018c21STomi Valkeinen {
1906f7018c21STomi Valkeinen RivaSurface __iomem *Surface =
1907f7018c21STomi Valkeinen (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]);
1908f7018c21STomi Valkeinen
1909f7018c21STomi Valkeinen NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000005);
1910f7018c21STomi Valkeinen NV_WR32(&Surface->Offset, 0, surf0);
1911f7018c21STomi Valkeinen NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000006);
1912f7018c21STomi Valkeinen NV_WR32(&Surface->Offset, 0, surf1);
1913f7018c21STomi Valkeinen NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000014);
1914f7018c21STomi Valkeinen }
nv10SetSurfaces3D(RIVA_HW_INST * chip,unsigned surf0,unsigned surf1)1915f7018c21STomi Valkeinen static void nv10SetSurfaces3D
1916f7018c21STomi Valkeinen (
1917f7018c21STomi Valkeinen RIVA_HW_INST *chip,
1918f7018c21STomi Valkeinen unsigned surf0,
1919f7018c21STomi Valkeinen unsigned surf1
1920f7018c21STomi Valkeinen )
1921f7018c21STomi Valkeinen {
1922f7018c21STomi Valkeinen RivaSurface3D __iomem *Surfaces3D =
1923f7018c21STomi Valkeinen (RivaSurface3D __iomem *)&(chip->FIFO[0x0000E000/4]);
1924f7018c21STomi Valkeinen
1925f7018c21STomi Valkeinen RIVA_FIFO_FREE(*chip,Tri03,4);
1926f7018c21STomi Valkeinen NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000007);
1927f7018c21STomi Valkeinen NV_WR32(&Surfaces3D->RenderBufferOffset, 0, surf0);
1928f7018c21STomi Valkeinen NV_WR32(&Surfaces3D->ZBufferOffset, 0, surf1);
1929f7018c21STomi Valkeinen NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000014);
1930f7018c21STomi Valkeinen }
1931f7018c21STomi Valkeinen
1932f7018c21STomi Valkeinen /****************************************************************************\
1933f7018c21STomi Valkeinen * *
1934f7018c21STomi Valkeinen * Probe RIVA Chip Configuration *
1935f7018c21STomi Valkeinen * *
1936f7018c21STomi Valkeinen \****************************************************************************/
1937f7018c21STomi Valkeinen
nv3GetConfig(RIVA_HW_INST * chip)1938f7018c21STomi Valkeinen static void nv3GetConfig
1939f7018c21STomi Valkeinen (
1940f7018c21STomi Valkeinen RIVA_HW_INST *chip
1941f7018c21STomi Valkeinen )
1942f7018c21STomi Valkeinen {
1943f7018c21STomi Valkeinen /*
1944f7018c21STomi Valkeinen * Fill in chip configuration.
1945f7018c21STomi Valkeinen */
1946f7018c21STomi Valkeinen if (NV_RD32(&chip->PFB[0x00000000/4], 0) & 0x00000020)
1947f7018c21STomi Valkeinen {
1948f7018c21STomi Valkeinen if (((NV_RD32(chip->PMC, 0x00000000) & 0xF0) == 0x20)
1949f7018c21STomi Valkeinen && ((NV_RD32(chip->PMC, 0x00000000) & 0x0F) >= 0x02))
1950f7018c21STomi Valkeinen {
1951f7018c21STomi Valkeinen /*
1952f7018c21STomi Valkeinen * SDRAM 128 ZX.
1953f7018c21STomi Valkeinen */
1954f7018c21STomi Valkeinen chip->RamBandwidthKBytesPerSec = 800000;
1955f7018c21STomi Valkeinen switch (NV_RD32(chip->PFB, 0x00000000) & 0x03)
1956f7018c21STomi Valkeinen {
1957f7018c21STomi Valkeinen case 2:
1958f7018c21STomi Valkeinen chip->RamAmountKBytes = 1024 * 4;
1959f7018c21STomi Valkeinen break;
1960f7018c21STomi Valkeinen case 1:
1961f7018c21STomi Valkeinen chip->RamAmountKBytes = 1024 * 2;
1962f7018c21STomi Valkeinen break;
1963f7018c21STomi Valkeinen default:
1964f7018c21STomi Valkeinen chip->RamAmountKBytes = 1024 * 8;
1965f7018c21STomi Valkeinen break;
1966f7018c21STomi Valkeinen }
1967f7018c21STomi Valkeinen }
1968f7018c21STomi Valkeinen else
1969f7018c21STomi Valkeinen {
1970f7018c21STomi Valkeinen chip->RamBandwidthKBytesPerSec = 1000000;
1971f7018c21STomi Valkeinen chip->RamAmountKBytes = 1024 * 8;
1972f7018c21STomi Valkeinen }
1973f7018c21STomi Valkeinen }
1974f7018c21STomi Valkeinen else
1975f7018c21STomi Valkeinen {
1976f7018c21STomi Valkeinen /*
1977f7018c21STomi Valkeinen * SGRAM 128.
1978f7018c21STomi Valkeinen */
1979f7018c21STomi Valkeinen chip->RamBandwidthKBytesPerSec = 1000000;
1980f7018c21STomi Valkeinen switch (NV_RD32(chip->PFB, 0x00000000) & 0x00000003)
1981f7018c21STomi Valkeinen {
1982f7018c21STomi Valkeinen case 0:
1983f7018c21STomi Valkeinen chip->RamAmountKBytes = 1024 * 8;
1984f7018c21STomi Valkeinen break;
1985f7018c21STomi Valkeinen case 2:
1986f7018c21STomi Valkeinen chip->RamAmountKBytes = 1024 * 4;
1987f7018c21STomi Valkeinen break;
1988f7018c21STomi Valkeinen default:
1989f7018c21STomi Valkeinen chip->RamAmountKBytes = 1024 * 2;
1990f7018c21STomi Valkeinen break;
1991f7018c21STomi Valkeinen }
1992f7018c21STomi Valkeinen }
1993f7018c21STomi Valkeinen chip->CrystalFreqKHz = (NV_RD32(chip->PEXTDEV, 0x00000000) & 0x00000040) ? 14318 : 13500;
1994f7018c21STomi Valkeinen chip->CURSOR = &(chip->PRAMIN[0x00008000/4 - 0x0800/4]);
1995f7018c21STomi Valkeinen chip->VBlankBit = 0x00000100;
1996f7018c21STomi Valkeinen chip->MaxVClockFreqKHz = 256000;
1997f7018c21STomi Valkeinen /*
1998f7018c21STomi Valkeinen * Set chip functions.
1999f7018c21STomi Valkeinen */
2000f7018c21STomi Valkeinen chip->Busy = nv3Busy;
2001f7018c21STomi Valkeinen chip->ShowHideCursor = ShowHideCursor;
2002f7018c21STomi Valkeinen chip->LoadStateExt = LoadStateExt;
2003f7018c21STomi Valkeinen chip->UnloadStateExt = UnloadStateExt;
2004f7018c21STomi Valkeinen chip->SetStartAddress = SetStartAddress3;
2005f7018c21STomi Valkeinen chip->SetSurfaces2D = nv3SetSurfaces2D;
2006f7018c21STomi Valkeinen chip->SetSurfaces3D = nv3SetSurfaces3D;
2007f7018c21STomi Valkeinen chip->LockUnlock = nv3LockUnlock;
2008f7018c21STomi Valkeinen }
nv4GetConfig(RIVA_HW_INST * chip)2009f7018c21STomi Valkeinen static void nv4GetConfig
2010f7018c21STomi Valkeinen (
2011f7018c21STomi Valkeinen RIVA_HW_INST *chip
2012f7018c21STomi Valkeinen )
2013f7018c21STomi Valkeinen {
2014f7018c21STomi Valkeinen /*
2015f7018c21STomi Valkeinen * Fill in chip configuration.
2016f7018c21STomi Valkeinen */
2017f7018c21STomi Valkeinen if (NV_RD32(chip->PFB, 0x00000000) & 0x00000100)
2018f7018c21STomi Valkeinen {
2019f7018c21STomi Valkeinen chip->RamAmountKBytes = ((NV_RD32(chip->PFB, 0x00000000) >> 12) & 0x0F) * 1024 * 2
2020f7018c21STomi Valkeinen + 1024 * 2;
2021f7018c21STomi Valkeinen }
2022f7018c21STomi Valkeinen else
2023f7018c21STomi Valkeinen {
2024f7018c21STomi Valkeinen switch (NV_RD32(chip->PFB, 0x00000000) & 0x00000003)
2025f7018c21STomi Valkeinen {
2026f7018c21STomi Valkeinen case 0:
2027f7018c21STomi Valkeinen chip->RamAmountKBytes = 1024 * 32;
2028f7018c21STomi Valkeinen break;
2029f7018c21STomi Valkeinen case 1:
2030f7018c21STomi Valkeinen chip->RamAmountKBytes = 1024 * 4;
2031f7018c21STomi Valkeinen break;
2032f7018c21STomi Valkeinen case 2:
2033f7018c21STomi Valkeinen chip->RamAmountKBytes = 1024 * 8;
2034f7018c21STomi Valkeinen break;
2035f7018c21STomi Valkeinen case 3:
2036f7018c21STomi Valkeinen default:
2037f7018c21STomi Valkeinen chip->RamAmountKBytes = 1024 * 16;
2038f7018c21STomi Valkeinen break;
2039f7018c21STomi Valkeinen }
2040f7018c21STomi Valkeinen }
2041f7018c21STomi Valkeinen switch ((NV_RD32(chip->PFB, 0x00000000) >> 3) & 0x00000003)
2042f7018c21STomi Valkeinen {
2043f7018c21STomi Valkeinen case 3:
2044f7018c21STomi Valkeinen chip->RamBandwidthKBytesPerSec = 800000;
2045f7018c21STomi Valkeinen break;
2046f7018c21STomi Valkeinen default:
2047f7018c21STomi Valkeinen chip->RamBandwidthKBytesPerSec = 1000000;
2048f7018c21STomi Valkeinen break;
2049f7018c21STomi Valkeinen }
2050f7018c21STomi Valkeinen chip->CrystalFreqKHz = (NV_RD32(chip->PEXTDEV, 0x00000000) & 0x00000040) ? 14318 : 13500;
2051f7018c21STomi Valkeinen chip->CURSOR = &(chip->PRAMIN[0x00010000/4 - 0x0800/4]);
2052f7018c21STomi Valkeinen chip->VBlankBit = 0x00000001;
2053f7018c21STomi Valkeinen chip->MaxVClockFreqKHz = 350000;
2054f7018c21STomi Valkeinen /*
2055f7018c21STomi Valkeinen * Set chip functions.
2056f7018c21STomi Valkeinen */
2057f7018c21STomi Valkeinen chip->Busy = nv4Busy;
2058f7018c21STomi Valkeinen chip->ShowHideCursor = ShowHideCursor;
2059f7018c21STomi Valkeinen chip->LoadStateExt = LoadStateExt;
2060f7018c21STomi Valkeinen chip->UnloadStateExt = UnloadStateExt;
2061f7018c21STomi Valkeinen chip->SetStartAddress = SetStartAddress;
2062f7018c21STomi Valkeinen chip->SetSurfaces2D = nv4SetSurfaces2D;
2063f7018c21STomi Valkeinen chip->SetSurfaces3D = nv4SetSurfaces3D;
2064f7018c21STomi Valkeinen chip->LockUnlock = nv4LockUnlock;
2065f7018c21STomi Valkeinen }
nv10GetConfig(RIVA_HW_INST * chip,struct pci_dev * pdev,unsigned int chipset)2066f7018c21STomi Valkeinen static void nv10GetConfig
2067f7018c21STomi Valkeinen (
2068f7018c21STomi Valkeinen RIVA_HW_INST *chip,
2069e2281080SSinan Kaya struct pci_dev *pdev,
2070f7018c21STomi Valkeinen unsigned int chipset
2071f7018c21STomi Valkeinen )
2072f7018c21STomi Valkeinen {
2073f7018c21STomi Valkeinen struct pci_dev* dev;
2074e2281080SSinan Kaya int domain = pci_domain_nr(pdev->bus);
2075f7018c21STomi Valkeinen u32 amt;
2076f7018c21STomi Valkeinen
2077f7018c21STomi Valkeinen #ifdef __BIG_ENDIAN
2078f7018c21STomi Valkeinen /* turn on big endian register access */
2079f7018c21STomi Valkeinen if(!(NV_RD32(chip->PMC, 0x00000004) & 0x01000001))
2080f7018c21STomi Valkeinen NV_WR32(chip->PMC, 0x00000004, 0x01000001);
2081f7018c21STomi Valkeinen #endif
2082f7018c21STomi Valkeinen
2083f7018c21STomi Valkeinen /*
2084f7018c21STomi Valkeinen * Fill in chip configuration.
2085f7018c21STomi Valkeinen */
2086f7018c21STomi Valkeinen if(chipset == NV_CHIP_IGEFORCE2) {
2087e2281080SSinan Kaya dev = pci_get_domain_bus_and_slot(domain, 0, 1);
2088f7018c21STomi Valkeinen pci_read_config_dword(dev, 0x7C, &amt);
2089f7018c21STomi Valkeinen pci_dev_put(dev);
2090f7018c21STomi Valkeinen chip->RamAmountKBytes = (((amt >> 6) & 31) + 1) * 1024;
2091f7018c21STomi Valkeinen } else if(chipset == NV_CHIP_0x01F0) {
2092e2281080SSinan Kaya dev = pci_get_domain_bus_and_slot(domain, 0, 1);
2093f7018c21STomi Valkeinen pci_read_config_dword(dev, 0x84, &amt);
2094f7018c21STomi Valkeinen pci_dev_put(dev);
2095f7018c21STomi Valkeinen chip->RamAmountKBytes = (((amt >> 4) & 127) + 1) * 1024;
2096f7018c21STomi Valkeinen } else {
2097f7018c21STomi Valkeinen switch ((NV_RD32(chip->PFB, 0x0000020C) >> 20) & 0x000000FF)
2098f7018c21STomi Valkeinen {
2099f7018c21STomi Valkeinen case 0x02:
2100f7018c21STomi Valkeinen chip->RamAmountKBytes = 1024 * 2;
2101f7018c21STomi Valkeinen break;
2102f7018c21STomi Valkeinen case 0x04:
2103f7018c21STomi Valkeinen chip->RamAmountKBytes = 1024 * 4;
2104f7018c21STomi Valkeinen break;
2105f7018c21STomi Valkeinen case 0x08:
2106f7018c21STomi Valkeinen chip->RamAmountKBytes = 1024 * 8;
2107f7018c21STomi Valkeinen break;
2108f7018c21STomi Valkeinen case 0x10:
2109f7018c21STomi Valkeinen chip->RamAmountKBytes = 1024 * 16;
2110f7018c21STomi Valkeinen break;
2111f7018c21STomi Valkeinen case 0x20:
2112f7018c21STomi Valkeinen chip->RamAmountKBytes = 1024 * 32;
2113f7018c21STomi Valkeinen break;
2114f7018c21STomi Valkeinen case 0x40:
2115f7018c21STomi Valkeinen chip->RamAmountKBytes = 1024 * 64;
2116f7018c21STomi Valkeinen break;
2117f7018c21STomi Valkeinen case 0x80:
2118f7018c21STomi Valkeinen chip->RamAmountKBytes = 1024 * 128;
2119f7018c21STomi Valkeinen break;
2120f7018c21STomi Valkeinen default:
2121f7018c21STomi Valkeinen chip->RamAmountKBytes = 1024 * 16;
2122f7018c21STomi Valkeinen break;
2123f7018c21STomi Valkeinen }
2124f7018c21STomi Valkeinen }
2125f7018c21STomi Valkeinen switch ((NV_RD32(chip->PFB, 0x00000000) >> 3) & 0x00000003)
2126f7018c21STomi Valkeinen {
2127f7018c21STomi Valkeinen case 3:
2128f7018c21STomi Valkeinen chip->RamBandwidthKBytesPerSec = 800000;
2129f7018c21STomi Valkeinen break;
2130f7018c21STomi Valkeinen default:
2131f7018c21STomi Valkeinen chip->RamBandwidthKBytesPerSec = 1000000;
2132f7018c21STomi Valkeinen break;
2133f7018c21STomi Valkeinen }
2134f7018c21STomi Valkeinen chip->CrystalFreqKHz = (NV_RD32(chip->PEXTDEV, 0x0000) & (1 << 6)) ?
2135f7018c21STomi Valkeinen 14318 : 13500;
2136f7018c21STomi Valkeinen
2137f7018c21STomi Valkeinen switch (chipset & 0x0ff0) {
2138f7018c21STomi Valkeinen case 0x0170:
2139f7018c21STomi Valkeinen case 0x0180:
2140f7018c21STomi Valkeinen case 0x01F0:
2141f7018c21STomi Valkeinen case 0x0250:
2142f7018c21STomi Valkeinen case 0x0280:
2143f7018c21STomi Valkeinen case 0x0300:
2144f7018c21STomi Valkeinen case 0x0310:
2145f7018c21STomi Valkeinen case 0x0320:
2146f7018c21STomi Valkeinen case 0x0330:
2147f7018c21STomi Valkeinen case 0x0340:
2148f7018c21STomi Valkeinen if(NV_RD32(chip->PEXTDEV, 0x0000) & (1 << 22))
2149f7018c21STomi Valkeinen chip->CrystalFreqKHz = 27000;
2150f7018c21STomi Valkeinen break;
2151f7018c21STomi Valkeinen default:
2152f7018c21STomi Valkeinen break;
2153f7018c21STomi Valkeinen }
2154f7018c21STomi Valkeinen
2155f7018c21STomi Valkeinen chip->CursorStart = (chip->RamAmountKBytes - 128) * 1024;
2156f7018c21STomi Valkeinen chip->CURSOR = NULL; /* can't set this here */
2157f7018c21STomi Valkeinen chip->VBlankBit = 0x00000001;
2158f7018c21STomi Valkeinen chip->MaxVClockFreqKHz = 350000;
2159f7018c21STomi Valkeinen /*
2160f7018c21STomi Valkeinen * Set chip functions.
2161f7018c21STomi Valkeinen */
2162f7018c21STomi Valkeinen chip->Busy = nv10Busy;
2163f7018c21STomi Valkeinen chip->ShowHideCursor = ShowHideCursor;
2164f7018c21STomi Valkeinen chip->LoadStateExt = LoadStateExt;
2165f7018c21STomi Valkeinen chip->UnloadStateExt = UnloadStateExt;
2166f7018c21STomi Valkeinen chip->SetStartAddress = SetStartAddress;
2167f7018c21STomi Valkeinen chip->SetSurfaces2D = nv10SetSurfaces2D;
2168f7018c21STomi Valkeinen chip->SetSurfaces3D = nv10SetSurfaces3D;
2169f7018c21STomi Valkeinen chip->LockUnlock = nv4LockUnlock;
2170f7018c21STomi Valkeinen
2171f7018c21STomi Valkeinen switch(chipset & 0x0ff0) {
2172f7018c21STomi Valkeinen case 0x0110:
2173f7018c21STomi Valkeinen case 0x0170:
2174f7018c21STomi Valkeinen case 0x0180:
2175f7018c21STomi Valkeinen case 0x01F0:
2176f7018c21STomi Valkeinen case 0x0250:
2177f7018c21STomi Valkeinen case 0x0280:
2178f7018c21STomi Valkeinen case 0x0300:
2179f7018c21STomi Valkeinen case 0x0310:
2180f7018c21STomi Valkeinen case 0x0320:
2181f7018c21STomi Valkeinen case 0x0330:
2182f7018c21STomi Valkeinen case 0x0340:
2183f7018c21STomi Valkeinen chip->twoHeads = TRUE;
2184f7018c21STomi Valkeinen break;
2185f7018c21STomi Valkeinen default:
2186f7018c21STomi Valkeinen chip->twoHeads = FALSE;
2187f7018c21STomi Valkeinen break;
2188f7018c21STomi Valkeinen }
2189f7018c21STomi Valkeinen }
RivaGetConfig(RIVA_HW_INST * chip,struct pci_dev * pdev,unsigned int chipset)2190f7018c21STomi Valkeinen int RivaGetConfig
2191f7018c21STomi Valkeinen (
2192f7018c21STomi Valkeinen RIVA_HW_INST *chip,
2193e2281080SSinan Kaya struct pci_dev *pdev,
2194f7018c21STomi Valkeinen unsigned int chipset
2195f7018c21STomi Valkeinen )
2196f7018c21STomi Valkeinen {
2197f7018c21STomi Valkeinen /*
2198f7018c21STomi Valkeinen * Save this so future SW know whats it's dealing with.
2199f7018c21STomi Valkeinen */
2200f7018c21STomi Valkeinen chip->Version = RIVA_SW_VERSION;
2201f7018c21STomi Valkeinen /*
2202f7018c21STomi Valkeinen * Chip specific configuration.
2203f7018c21STomi Valkeinen */
2204f7018c21STomi Valkeinen switch (chip->Architecture)
2205f7018c21STomi Valkeinen {
2206f7018c21STomi Valkeinen case NV_ARCH_03:
2207f7018c21STomi Valkeinen nv3GetConfig(chip);
2208f7018c21STomi Valkeinen break;
2209f7018c21STomi Valkeinen case NV_ARCH_04:
2210f7018c21STomi Valkeinen nv4GetConfig(chip);
2211f7018c21STomi Valkeinen break;
2212f7018c21STomi Valkeinen case NV_ARCH_10:
2213f7018c21STomi Valkeinen case NV_ARCH_20:
2214f7018c21STomi Valkeinen case NV_ARCH_30:
2215e2281080SSinan Kaya nv10GetConfig(chip, pdev, chipset);
2216f7018c21STomi Valkeinen break;
2217f7018c21STomi Valkeinen default:
2218f7018c21STomi Valkeinen return (-1);
2219f7018c21STomi Valkeinen }
2220f7018c21STomi Valkeinen chip->Chipset = chipset;
2221f7018c21STomi Valkeinen /*
2222f7018c21STomi Valkeinen * Fill in FIFO pointers.
2223f7018c21STomi Valkeinen */
2224f7018c21STomi Valkeinen chip->Rop = (RivaRop __iomem *)&(chip->FIFO[0x00000000/4]);
2225f7018c21STomi Valkeinen chip->Clip = (RivaClip __iomem *)&(chip->FIFO[0x00002000/4]);
2226f7018c21STomi Valkeinen chip->Patt = (RivaPattern __iomem *)&(chip->FIFO[0x00004000/4]);
2227f7018c21STomi Valkeinen chip->Pixmap = (RivaPixmap __iomem *)&(chip->FIFO[0x00006000/4]);
2228f7018c21STomi Valkeinen chip->Blt = (RivaScreenBlt __iomem *)&(chip->FIFO[0x00008000/4]);
2229f7018c21STomi Valkeinen chip->Bitmap = (RivaBitmap __iomem *)&(chip->FIFO[0x0000A000/4]);
2230f7018c21STomi Valkeinen chip->Line = (RivaLine __iomem *)&(chip->FIFO[0x0000C000/4]);
2231f7018c21STomi Valkeinen chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]);
2232f7018c21STomi Valkeinen return (0);
2233f7018c21STomi Valkeinen }
2234f7018c21STomi Valkeinen
2235