1 /* 2 * Copyright © 2007-2008 Intel Corporation 3 * Jesse Barnes <jesse.barnes@intel.com> 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 #ifndef __DRM_EDID_H__ 24 #define __DRM_EDID_H__ 25 26 #include <linux/types.h> 27 #include <linux/hdmi.h> 28 #include <drm/drm_mode.h> 29 30 struct drm_device; 31 struct drm_edid; 32 struct i2c_adapter; 33 34 #define EDID_LENGTH 128 35 #define DDC_ADDR 0x50 36 #define DDC_ADDR2 0x52 /* E-DDC 1.2 - where DisplayID can hide */ 37 38 #define CEA_EXT 0x02 39 #define VTB_EXT 0x10 40 #define DI_EXT 0x40 41 #define LS_EXT 0x50 42 #define MI_EXT 0x60 43 #define DISPLAYID_EXT 0x70 44 45 struct est_timings { 46 u8 t1; 47 u8 t2; 48 u8 mfg_rsvd; 49 } __attribute__((packed)); 50 51 /* 00=16:10, 01=4:3, 10=5:4, 11=16:9 */ 52 #define EDID_TIMING_ASPECT_SHIFT 6 53 #define EDID_TIMING_ASPECT_MASK (0x3 << EDID_TIMING_ASPECT_SHIFT) 54 55 /* need to add 60 */ 56 #define EDID_TIMING_VFREQ_SHIFT 0 57 #define EDID_TIMING_VFREQ_MASK (0x3f << EDID_TIMING_VFREQ_SHIFT) 58 59 struct std_timing { 60 u8 hsize; /* need to multiply by 8 then add 248 */ 61 u8 vfreq_aspect; 62 } __attribute__((packed)); 63 64 #define DRM_EDID_PT_HSYNC_POSITIVE (1 << 1) 65 #define DRM_EDID_PT_VSYNC_POSITIVE (1 << 2) 66 #define DRM_EDID_PT_SEPARATE_SYNC (3 << 3) 67 #define DRM_EDID_PT_STEREO (1 << 5) 68 #define DRM_EDID_PT_INTERLACED (1 << 7) 69 70 /* If detailed data is pixel timing */ 71 struct detailed_pixel_timing { 72 u8 hactive_lo; 73 u8 hblank_lo; 74 u8 hactive_hblank_hi; 75 u8 vactive_lo; 76 u8 vblank_lo; 77 u8 vactive_vblank_hi; 78 u8 hsync_offset_lo; 79 u8 hsync_pulse_width_lo; 80 u8 vsync_offset_pulse_width_lo; 81 u8 hsync_vsync_offset_pulse_width_hi; 82 u8 width_mm_lo; 83 u8 height_mm_lo; 84 u8 width_height_mm_hi; 85 u8 hborder; 86 u8 vborder; 87 u8 misc; 88 } __attribute__((packed)); 89 90 /* If it's not pixel timing, it'll be one of the below */ 91 struct detailed_data_string { 92 u8 str[13]; 93 } __attribute__((packed)); 94 95 #define DRM_EDID_RANGE_OFFSET_MIN_VFREQ (1 << 0) /* 1.4 */ 96 #define DRM_EDID_RANGE_OFFSET_MAX_VFREQ (1 << 1) /* 1.4 */ 97 #define DRM_EDID_RANGE_OFFSET_MIN_HFREQ (1 << 2) /* 1.4 */ 98 #define DRM_EDID_RANGE_OFFSET_MAX_HFREQ (1 << 3) /* 1.4 */ 99 100 #define DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG 0x00 /* 1.3 */ 101 #define DRM_EDID_RANGE_LIMITS_ONLY_FLAG 0x01 /* 1.4 */ 102 #define DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG 0x02 /* 1.3 */ 103 #define DRM_EDID_CVT_SUPPORT_FLAG 0x04 /* 1.4 */ 104 105 #define DRM_EDID_CVT_FLAGS_STANDARD_BLANKING (1 << 3) 106 #define DRM_EDID_CVT_FLAGS_REDUCED_BLANKING (1 << 4) 107 108 struct detailed_data_monitor_range { 109 u8 min_vfreq; 110 u8 max_vfreq; 111 u8 min_hfreq_khz; 112 u8 max_hfreq_khz; 113 u8 pixel_clock_mhz; /* need to multiply by 10 */ 114 u8 flags; 115 union { 116 struct { 117 u8 reserved; 118 u8 hfreq_start_khz; /* need to multiply by 2 */ 119 u8 c; /* need to divide by 2 */ 120 __le16 m; 121 u8 k; 122 u8 j; /* need to divide by 2 */ 123 } __attribute__((packed)) gtf2; 124 struct { 125 u8 version; 126 u8 data1; /* high 6 bits: extra clock resolution */ 127 u8 data2; /* plus low 2 of above: max hactive */ 128 u8 supported_aspects; 129 u8 flags; /* preferred aspect and blanking support */ 130 u8 supported_scalings; 131 u8 preferred_refresh; 132 } __attribute__((packed)) cvt; 133 } __attribute__((packed)) formula; 134 } __attribute__((packed)); 135 136 struct detailed_data_wpindex { 137 u8 white_yx_lo; /* Lower 2 bits each */ 138 u8 white_x_hi; 139 u8 white_y_hi; 140 u8 gamma; /* need to divide by 100 then add 1 */ 141 } __attribute__((packed)); 142 143 struct detailed_data_color_point { 144 u8 windex1; 145 u8 wpindex1[3]; 146 u8 windex2; 147 u8 wpindex2[3]; 148 } __attribute__((packed)); 149 150 struct cvt_timing { 151 u8 code[3]; 152 } __attribute__((packed)); 153 154 struct detailed_non_pixel { 155 u8 pad1; 156 u8 type; /* ff=serial, fe=string, fd=monitor range, fc=monitor name 157 fb=color point data, fa=standard timing data, 158 f9=undefined, f8=mfg. reserved */ 159 u8 pad2; 160 union { 161 struct detailed_data_string str; 162 struct detailed_data_monitor_range range; 163 struct detailed_data_wpindex color; 164 struct std_timing timings[6]; 165 struct cvt_timing cvt[4]; 166 } __attribute__((packed)) data; 167 } __attribute__((packed)); 168 169 #define EDID_DETAIL_EST_TIMINGS 0xf7 170 #define EDID_DETAIL_CVT_3BYTE 0xf8 171 #define EDID_DETAIL_COLOR_MGMT_DATA 0xf9 172 #define EDID_DETAIL_STD_MODES 0xfa 173 #define EDID_DETAIL_MONITOR_CPDATA 0xfb 174 #define EDID_DETAIL_MONITOR_NAME 0xfc 175 #define EDID_DETAIL_MONITOR_RANGE 0xfd 176 #define EDID_DETAIL_MONITOR_STRING 0xfe 177 #define EDID_DETAIL_MONITOR_SERIAL 0xff 178 179 struct detailed_timing { 180 __le16 pixel_clock; /* need to multiply by 10 KHz */ 181 union { 182 struct detailed_pixel_timing pixel_data; 183 struct detailed_non_pixel other_data; 184 } __attribute__((packed)) data; 185 } __attribute__((packed)); 186 187 #define DRM_EDID_INPUT_SERRATION_VSYNC (1 << 0) 188 #define DRM_EDID_INPUT_SYNC_ON_GREEN (1 << 1) 189 #define DRM_EDID_INPUT_COMPOSITE_SYNC (1 << 2) 190 #define DRM_EDID_INPUT_SEPARATE_SYNCS (1 << 3) 191 #define DRM_EDID_INPUT_BLANK_TO_BLACK (1 << 4) 192 #define DRM_EDID_INPUT_VIDEO_LEVEL (3 << 5) 193 #define DRM_EDID_INPUT_DIGITAL (1 << 7) 194 #define DRM_EDID_DIGITAL_DEPTH_MASK (7 << 4) /* 1.4 */ 195 #define DRM_EDID_DIGITAL_DEPTH_UNDEF (0 << 4) /* 1.4 */ 196 #define DRM_EDID_DIGITAL_DEPTH_6 (1 << 4) /* 1.4 */ 197 #define DRM_EDID_DIGITAL_DEPTH_8 (2 << 4) /* 1.4 */ 198 #define DRM_EDID_DIGITAL_DEPTH_10 (3 << 4) /* 1.4 */ 199 #define DRM_EDID_DIGITAL_DEPTH_12 (4 << 4) /* 1.4 */ 200 #define DRM_EDID_DIGITAL_DEPTH_14 (5 << 4) /* 1.4 */ 201 #define DRM_EDID_DIGITAL_DEPTH_16 (6 << 4) /* 1.4 */ 202 #define DRM_EDID_DIGITAL_DEPTH_RSVD (7 << 4) /* 1.4 */ 203 #define DRM_EDID_DIGITAL_TYPE_MASK (7 << 0) /* 1.4 */ 204 #define DRM_EDID_DIGITAL_TYPE_UNDEF (0 << 0) /* 1.4 */ 205 #define DRM_EDID_DIGITAL_TYPE_DVI (1 << 0) /* 1.4 */ 206 #define DRM_EDID_DIGITAL_TYPE_HDMI_A (2 << 0) /* 1.4 */ 207 #define DRM_EDID_DIGITAL_TYPE_HDMI_B (3 << 0) /* 1.4 */ 208 #define DRM_EDID_DIGITAL_TYPE_MDDI (4 << 0) /* 1.4 */ 209 #define DRM_EDID_DIGITAL_TYPE_DP (5 << 0) /* 1.4 */ 210 #define DRM_EDID_DIGITAL_DFP_1_X (1 << 0) /* 1.3 */ 211 212 #define DRM_EDID_FEATURE_DEFAULT_GTF (1 << 0) /* 1.2 */ 213 #define DRM_EDID_FEATURE_CONTINUOUS_FREQ (1 << 0) /* 1.4 */ 214 #define DRM_EDID_FEATURE_PREFERRED_TIMING (1 << 1) 215 #define DRM_EDID_FEATURE_STANDARD_COLOR (1 << 2) 216 /* If analog */ 217 #define DRM_EDID_FEATURE_DISPLAY_TYPE (3 << 3) /* 00=mono, 01=rgb, 10=non-rgb, 11=unknown */ 218 /* If digital */ 219 #define DRM_EDID_FEATURE_COLOR_MASK (3 << 3) 220 #define DRM_EDID_FEATURE_RGB (0 << 3) 221 #define DRM_EDID_FEATURE_RGB_YCRCB444 (1 << 3) 222 #define DRM_EDID_FEATURE_RGB_YCRCB422 (2 << 3) 223 #define DRM_EDID_FEATURE_RGB_YCRCB (3 << 3) /* both 4:4:4 and 4:2:2 */ 224 225 #define DRM_EDID_FEATURE_PM_ACTIVE_OFF (1 << 5) 226 #define DRM_EDID_FEATURE_PM_SUSPEND (1 << 6) 227 #define DRM_EDID_FEATURE_PM_STANDBY (1 << 7) 228 229 #define DRM_EDID_HDMI_DC_48 (1 << 6) 230 #define DRM_EDID_HDMI_DC_36 (1 << 5) 231 #define DRM_EDID_HDMI_DC_30 (1 << 4) 232 #define DRM_EDID_HDMI_DC_Y444 (1 << 3) 233 234 /* YCBCR 420 deep color modes */ 235 #define DRM_EDID_YCBCR420_DC_48 (1 << 2) 236 #define DRM_EDID_YCBCR420_DC_36 (1 << 1) 237 #define DRM_EDID_YCBCR420_DC_30 (1 << 0) 238 #define DRM_EDID_YCBCR420_DC_MASK (DRM_EDID_YCBCR420_DC_48 | \ 239 DRM_EDID_YCBCR420_DC_36 | \ 240 DRM_EDID_YCBCR420_DC_30) 241 242 /* HDMI 2.1 additional fields */ 243 #define DRM_EDID_MAX_FRL_RATE_MASK 0xf0 244 #define DRM_EDID_FAPA_START_LOCATION (1 << 0) 245 #define DRM_EDID_ALLM (1 << 1) 246 #define DRM_EDID_FVA (1 << 2) 247 248 /* Deep Color specific */ 249 #define DRM_EDID_DC_30BIT_420 (1 << 0) 250 #define DRM_EDID_DC_36BIT_420 (1 << 1) 251 #define DRM_EDID_DC_48BIT_420 (1 << 2) 252 253 /* VRR specific */ 254 #define DRM_EDID_CNMVRR (1 << 3) 255 #define DRM_EDID_CINEMA_VRR (1 << 4) 256 #define DRM_EDID_MDELTA (1 << 5) 257 #define DRM_EDID_VRR_MAX_UPPER_MASK 0xc0 258 #define DRM_EDID_VRR_MAX_LOWER_MASK 0xff 259 #define DRM_EDID_VRR_MIN_MASK 0x3f 260 261 /* DSC specific */ 262 #define DRM_EDID_DSC_10BPC (1 << 0) 263 #define DRM_EDID_DSC_12BPC (1 << 1) 264 #define DRM_EDID_DSC_16BPC (1 << 2) 265 #define DRM_EDID_DSC_ALL_BPP (1 << 3) 266 #define DRM_EDID_DSC_NATIVE_420 (1 << 6) 267 #define DRM_EDID_DSC_1P2 (1 << 7) 268 #define DRM_EDID_DSC_MAX_FRL_RATE_MASK 0xf0 269 #define DRM_EDID_DSC_MAX_SLICES 0xf 270 #define DRM_EDID_DSC_TOTAL_CHUNK_KBYTES 0x3f 271 272 /* ELD Header Block */ 273 #define DRM_ELD_HEADER_BLOCK_SIZE 4 274 275 #define DRM_ELD_VER 0 276 # define DRM_ELD_VER_SHIFT 3 277 # define DRM_ELD_VER_MASK (0x1f << 3) 278 # define DRM_ELD_VER_CEA861D (2 << 3) /* supports 861D or below */ 279 # define DRM_ELD_VER_CANNED (0x1f << 3) 280 281 #define DRM_ELD_BASELINE_ELD_LEN 2 /* in dwords! */ 282 283 /* ELD Baseline Block for ELD_Ver == 2 */ 284 #define DRM_ELD_CEA_EDID_VER_MNL 4 285 # define DRM_ELD_CEA_EDID_VER_SHIFT 5 286 # define DRM_ELD_CEA_EDID_VER_MASK (7 << 5) 287 # define DRM_ELD_CEA_EDID_VER_NONE (0 << 5) 288 # define DRM_ELD_CEA_EDID_VER_CEA861 (1 << 5) 289 # define DRM_ELD_CEA_EDID_VER_CEA861A (2 << 5) 290 # define DRM_ELD_CEA_EDID_VER_CEA861BCD (3 << 5) 291 # define DRM_ELD_MNL_SHIFT 0 292 # define DRM_ELD_MNL_MASK (0x1f << 0) 293 294 #define DRM_ELD_SAD_COUNT_CONN_TYPE 5 295 # define DRM_ELD_SAD_COUNT_SHIFT 4 296 # define DRM_ELD_SAD_COUNT_MASK (0xf << 4) 297 # define DRM_ELD_CONN_TYPE_SHIFT 2 298 # define DRM_ELD_CONN_TYPE_MASK (3 << 2) 299 # define DRM_ELD_CONN_TYPE_HDMI (0 << 2) 300 # define DRM_ELD_CONN_TYPE_DP (1 << 2) 301 # define DRM_ELD_SUPPORTS_AI (1 << 1) 302 # define DRM_ELD_SUPPORTS_HDCP (1 << 0) 303 304 #define DRM_ELD_AUD_SYNCH_DELAY 6 /* in units of 2 ms */ 305 # define DRM_ELD_AUD_SYNCH_DELAY_MAX 0xfa /* 500 ms */ 306 307 #define DRM_ELD_SPEAKER 7 308 # define DRM_ELD_SPEAKER_MASK 0x7f 309 # define DRM_ELD_SPEAKER_RLRC (1 << 6) 310 # define DRM_ELD_SPEAKER_FLRC (1 << 5) 311 # define DRM_ELD_SPEAKER_RC (1 << 4) 312 # define DRM_ELD_SPEAKER_RLR (1 << 3) 313 # define DRM_ELD_SPEAKER_FC (1 << 2) 314 # define DRM_ELD_SPEAKER_LFE (1 << 1) 315 # define DRM_ELD_SPEAKER_FLR (1 << 0) 316 317 #define DRM_ELD_PORT_ID 8 /* offsets 8..15 inclusive */ 318 # define DRM_ELD_PORT_ID_LEN 8 319 320 #define DRM_ELD_MANUFACTURER_NAME0 16 321 #define DRM_ELD_MANUFACTURER_NAME1 17 322 323 #define DRM_ELD_PRODUCT_CODE0 18 324 #define DRM_ELD_PRODUCT_CODE1 19 325 326 #define DRM_ELD_MONITOR_NAME_STRING 20 /* offsets 20..(20+mnl-1) inclusive */ 327 328 #define DRM_ELD_CEA_SAD(mnl, sad) (20 + (mnl) + 3 * (sad)) 329 330 struct edid { 331 u8 header[8]; 332 /* Vendor & product info */ 333 u8 mfg_id[2]; 334 u8 prod_code[2]; 335 u32 serial; /* FIXME: byte order */ 336 u8 mfg_week; 337 u8 mfg_year; 338 /* EDID version */ 339 u8 version; 340 u8 revision; 341 /* Display info: */ 342 u8 input; 343 u8 width_cm; 344 u8 height_cm; 345 u8 gamma; 346 u8 features; 347 /* Color characteristics */ 348 u8 red_green_lo; 349 u8 blue_white_lo; 350 u8 red_x; 351 u8 red_y; 352 u8 green_x; 353 u8 green_y; 354 u8 blue_x; 355 u8 blue_y; 356 u8 white_x; 357 u8 white_y; 358 /* Est. timings and mfg rsvd timings*/ 359 struct est_timings established_timings; 360 /* Standard timings 1-8*/ 361 struct std_timing standard_timings[8]; 362 /* Detailing timings 1-4 */ 363 struct detailed_timing detailed_timings[4]; 364 /* Number of 128 byte ext. blocks */ 365 u8 extensions; 366 /* Checksum */ 367 u8 checksum; 368 } __attribute__((packed)); 369 370 #define EDID_PRODUCT_ID(e) ((e)->prod_code[0] | ((e)->prod_code[1] << 8)) 371 372 /* Short Audio Descriptor */ 373 struct cea_sad { 374 u8 format; 375 u8 channels; /* max number of channels - 1 */ 376 u8 freq; 377 u8 byte2; /* meaning depends on format */ 378 }; 379 380 struct drm_encoder; 381 struct drm_connector; 382 struct drm_connector_state; 383 struct drm_display_mode; 384 385 int drm_edid_to_sad(const struct edid *edid, struct cea_sad **sads); 386 int drm_edid_to_speaker_allocation(const struct edid *edid, u8 **sadb); 387 int drm_av_sync_delay(struct drm_connector *connector, 388 const struct drm_display_mode *mode); 389 390 #ifdef CONFIG_DRM_LOAD_EDID_FIRMWARE 391 int __drm_set_edid_firmware_path(const char *path); 392 int __drm_get_edid_firmware_path(char *buf, size_t bufsize); 393 #endif 394 395 bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2); 396 397 int 398 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 399 const struct drm_connector *connector, 400 const struct drm_display_mode *mode); 401 int 402 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 403 const struct drm_connector *connector, 404 const struct drm_display_mode *mode); 405 406 void 407 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame, 408 const struct drm_connector *connector, 409 const struct drm_display_mode *mode, 410 enum hdmi_quantization_range rgb_quant_range); 411 412 /** 413 * drm_eld_mnl - Get ELD monitor name length in bytes. 414 * @eld: pointer to an eld memory structure with mnl set 415 */ 416 static inline int drm_eld_mnl(const uint8_t *eld) 417 { 418 return (eld[DRM_ELD_CEA_EDID_VER_MNL] & DRM_ELD_MNL_MASK) >> DRM_ELD_MNL_SHIFT; 419 } 420 421 /** 422 * drm_eld_sad - Get ELD SAD structures. 423 * @eld: pointer to an eld memory structure with sad_count set 424 */ 425 static inline const uint8_t *drm_eld_sad(const uint8_t *eld) 426 { 427 unsigned int ver, mnl; 428 429 ver = (eld[DRM_ELD_VER] & DRM_ELD_VER_MASK) >> DRM_ELD_VER_SHIFT; 430 if (ver != 2 && ver != 31) 431 return NULL; 432 433 mnl = drm_eld_mnl(eld); 434 if (mnl > 16) 435 return NULL; 436 437 return eld + DRM_ELD_CEA_SAD(mnl, 0); 438 } 439 440 /** 441 * drm_eld_sad_count - Get ELD SAD count. 442 * @eld: pointer to an eld memory structure with sad_count set 443 */ 444 static inline int drm_eld_sad_count(const uint8_t *eld) 445 { 446 return (eld[DRM_ELD_SAD_COUNT_CONN_TYPE] & DRM_ELD_SAD_COUNT_MASK) >> 447 DRM_ELD_SAD_COUNT_SHIFT; 448 } 449 450 /** 451 * drm_eld_calc_baseline_block_size - Calculate baseline block size in bytes 452 * @eld: pointer to an eld memory structure with mnl and sad_count set 453 * 454 * This is a helper for determining the payload size of the baseline block, in 455 * bytes, for e.g. setting the Baseline_ELD_Len field in the ELD header block. 456 */ 457 static inline int drm_eld_calc_baseline_block_size(const uint8_t *eld) 458 { 459 return DRM_ELD_MONITOR_NAME_STRING - DRM_ELD_HEADER_BLOCK_SIZE + 460 drm_eld_mnl(eld) + drm_eld_sad_count(eld) * 3; 461 } 462 463 /** 464 * drm_eld_size - Get ELD size in bytes 465 * @eld: pointer to a complete eld memory structure 466 * 467 * The returned value does not include the vendor block. It's vendor specific, 468 * and comprises of the remaining bytes in the ELD memory buffer after 469 * drm_eld_size() bytes of header and baseline block. 470 * 471 * The returned value is guaranteed to be a multiple of 4. 472 */ 473 static inline int drm_eld_size(const uint8_t *eld) 474 { 475 return DRM_ELD_HEADER_BLOCK_SIZE + eld[DRM_ELD_BASELINE_ELD_LEN] * 4; 476 } 477 478 /** 479 * drm_eld_get_spk_alloc - Get speaker allocation 480 * @eld: pointer to an ELD memory structure 481 * 482 * The returned value is the speakers mask. User has to use %DRM_ELD_SPEAKER 483 * field definitions to identify speakers. 484 */ 485 static inline u8 drm_eld_get_spk_alloc(const uint8_t *eld) 486 { 487 return eld[DRM_ELD_SPEAKER] & DRM_ELD_SPEAKER_MASK; 488 } 489 490 /** 491 * drm_eld_get_conn_type - Get device type hdmi/dp connected 492 * @eld: pointer to an ELD memory structure 493 * 494 * The caller need to use %DRM_ELD_CONN_TYPE_HDMI or %DRM_ELD_CONN_TYPE_DP to 495 * identify the display type connected. 496 */ 497 static inline u8 drm_eld_get_conn_type(const uint8_t *eld) 498 { 499 return eld[DRM_ELD_SAD_COUNT_CONN_TYPE] & DRM_ELD_CONN_TYPE_MASK; 500 } 501 502 /** 503 * drm_edid_decode_mfg_id - Decode the manufacturer ID 504 * @mfg_id: The manufacturer ID 505 * @vend: A 4-byte buffer to store the 3-letter vendor string plus a '\0' 506 * termination 507 */ 508 static inline const char *drm_edid_decode_mfg_id(u16 mfg_id, char vend[4]) 509 { 510 vend[0] = '@' + ((mfg_id >> 10) & 0x1f); 511 vend[1] = '@' + ((mfg_id >> 5) & 0x1f); 512 vend[2] = '@' + ((mfg_id >> 0) & 0x1f); 513 vend[3] = '\0'; 514 515 return vend; 516 } 517 518 /** 519 * drm_edid_encode_panel_id - Encode an ID for matching against drm_edid_get_panel_id() 520 * @vend_chr_0: First character of the vendor string. 521 * @vend_chr_1: Second character of the vendor string. 522 * @vend_chr_2: Third character of the vendor string. 523 * @product_id: The 16-bit product ID. 524 * 525 * This is a macro so that it can be calculated at compile time and used 526 * as an initializer. 527 * 528 * For instance: 529 * drm_edid_encode_panel_id('B', 'O', 'E', 0x2d08) => 0x09e52d08 530 * 531 * Return: a 32-bit ID per panel. 532 */ 533 #define drm_edid_encode_panel_id(vend_chr_0, vend_chr_1, vend_chr_2, product_id) \ 534 ((((u32)(vend_chr_0) - '@') & 0x1f) << 26 | \ 535 (((u32)(vend_chr_1) - '@') & 0x1f) << 21 | \ 536 (((u32)(vend_chr_2) - '@') & 0x1f) << 16 | \ 537 ((product_id) & 0xffff)) 538 539 /** 540 * drm_edid_decode_panel_id - Decode a panel ID from drm_edid_encode_panel_id() 541 * @panel_id: The panel ID to decode. 542 * @vend: A 4-byte buffer to store the 3-letter vendor string plus a '\0' 543 * termination 544 * @product_id: The product ID will be returned here. 545 * 546 * For instance, after: 547 * drm_edid_decode_panel_id(0x09e52d08, vend, &product_id) 548 * These will be true: 549 * vend[0] = 'B' 550 * vend[1] = 'O' 551 * vend[2] = 'E' 552 * vend[3] = '\0' 553 * product_id = 0x2d08 554 */ 555 static inline void drm_edid_decode_panel_id(u32 panel_id, char vend[4], u16 *product_id) 556 { 557 *product_id = (u16)(panel_id & 0xffff); 558 drm_edid_decode_mfg_id(panel_id >> 16, vend); 559 } 560 561 bool drm_probe_ddc(struct i2c_adapter *adapter); 562 struct edid *drm_do_get_edid(struct drm_connector *connector, 563 int (*get_edid_block)(void *data, u8 *buf, unsigned int block, 564 size_t len), 565 void *data); 566 struct edid *drm_get_edid(struct drm_connector *connector, 567 struct i2c_adapter *adapter); 568 u32 drm_edid_get_panel_id(struct i2c_adapter *adapter); 569 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector, 570 struct i2c_adapter *adapter); 571 struct edid *drm_edid_duplicate(const struct edid *edid); 572 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid); 573 int drm_edid_override_connector_update(struct drm_connector *connector); 574 575 u8 drm_match_cea_mode(const struct drm_display_mode *to_match); 576 bool drm_detect_hdmi_monitor(const struct edid *edid); 577 bool drm_detect_monitor_audio(const struct edid *edid); 578 enum hdmi_quantization_range 579 drm_default_rgb_quant_range(const struct drm_display_mode *mode); 580 int drm_add_modes_noedid(struct drm_connector *connector, 581 int hdisplay, int vdisplay); 582 void drm_set_preferred_mode(struct drm_connector *connector, 583 int hpref, int vpref); 584 585 int drm_edid_header_is_valid(const void *edid); 586 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid, 587 bool *edid_corrupt); 588 bool drm_edid_is_valid(struct edid *edid); 589 void drm_edid_get_monitor_name(const struct edid *edid, char *name, 590 int buflen); 591 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, 592 int hsize, int vsize, int fresh, 593 bool rb); 594 struct drm_display_mode * 595 drm_display_mode_from_cea_vic(struct drm_device *dev, 596 u8 video_code); 597 598 /* Interface based on struct drm_edid */ 599 const struct drm_edid *drm_edid_alloc(const void *edid, size_t size); 600 const struct drm_edid *drm_edid_dup(const struct drm_edid *drm_edid); 601 void drm_edid_free(const struct drm_edid *drm_edid); 602 bool drm_edid_valid(const struct drm_edid *drm_edid); 603 const struct edid *drm_edid_raw(const struct drm_edid *drm_edid); 604 const struct drm_edid *drm_edid_read(struct drm_connector *connector); 605 const struct drm_edid *drm_edid_read_ddc(struct drm_connector *connector, 606 struct i2c_adapter *adapter); 607 const struct drm_edid *drm_edid_read_custom(struct drm_connector *connector, 608 int (*read_block)(void *context, u8 *buf, unsigned int block, size_t len), 609 void *context); 610 const struct drm_edid *drm_edid_read_switcheroo(struct drm_connector *connector, 611 struct i2c_adapter *adapter); 612 int drm_edid_connector_update(struct drm_connector *connector, 613 const struct drm_edid *edid); 614 int drm_edid_connector_add_modes(struct drm_connector *connector); 615 bool drm_edid_is_digital(const struct drm_edid *drm_edid); 616 617 const u8 *drm_find_edid_extension(const struct drm_edid *drm_edid, 618 int ext_id, int *ext_index); 619 620 #endif /* __DRM_EDID_H__ */ 621