1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Copyright (c) 2014 Samsung Electronics Co., Ltd.
4  * 	Author: Tomasz Figa <t.figa@samsung.com>
5  *
6  * Device Tree binding constants for Samsung Exynos3250 clock controllers.
7  */
8 
9 #ifndef _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H
10 #define _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H
11 
12 /*
13  * Let each exported clock get a unique index, which is used on DT-enabled
14  * platforms to lookup the clock from a clock specifier. These indices are
15  * therefore considered an ABI and so must not be changed. This implies
16  * that new clocks should be added either in free spaces between clock groups
17  * or at the end.
18  */
19 
20 
21 /*
22  * Main CMU
23  */
24 
25 #define CLK_OSCSEL			1
26 #define CLK_FIN_PLL			2
27 #define CLK_FOUT_APLL			3
28 #define CLK_FOUT_VPLL			4
29 #define CLK_FOUT_UPLL			5
30 #define CLK_FOUT_MPLL			6
31 #define CLK_ARM_CLK			7
32 
33 /* Muxes */
34 #define CLK_MOUT_MPLL_USER_L		16
35 #define CLK_MOUT_GDL			17
36 #define CLK_MOUT_MPLL_USER_R		18
37 #define CLK_MOUT_GDR			19
38 #define CLK_MOUT_EBI			20
39 #define CLK_MOUT_ACLK_200		21
40 #define CLK_MOUT_ACLK_160		22
41 #define CLK_MOUT_ACLK_100		23
42 #define CLK_MOUT_ACLK_266_1		24
43 #define CLK_MOUT_ACLK_266_0		25
44 #define CLK_MOUT_ACLK_266		26
45 #define CLK_MOUT_VPLL			27
46 #define CLK_MOUT_EPLL_USER		28
47 #define CLK_MOUT_EBI_1			29
48 #define CLK_MOUT_UPLL			30
49 #define CLK_MOUT_ACLK_400_MCUISP_SUB	31
50 #define CLK_MOUT_MPLL			32
51 #define CLK_MOUT_ACLK_400_MCUISP	33
52 #define CLK_MOUT_VPLLSRC		34
53 #define CLK_MOUT_CAM1			35
54 #define CLK_MOUT_CAM_BLK		36
55 #define CLK_MOUT_MFC			37
56 #define CLK_MOUT_MFC_1			38
57 #define CLK_MOUT_MFC_0			39
58 #define CLK_MOUT_G3D			40
59 #define CLK_MOUT_G3D_1			41
60 #define CLK_MOUT_G3D_0			42
61 #define CLK_MOUT_MIPI0			43
62 #define CLK_MOUT_FIMD0			44
63 #define CLK_MOUT_UART_ISP		45
64 #define CLK_MOUT_SPI1_ISP		46
65 #define CLK_MOUT_SPI0_ISP		47
66 #define CLK_MOUT_TSADC			48
67 #define CLK_MOUT_MMC1			49
68 #define CLK_MOUT_MMC0			50
69 #define CLK_MOUT_UART1			51
70 #define CLK_MOUT_UART0			52
71 #define CLK_MOUT_SPI1			53
72 #define CLK_MOUT_SPI0			54
73 #define CLK_MOUT_AUDIO			55
74 #define CLK_MOUT_MPLL_USER_C		56
75 #define CLK_MOUT_HPM			57
76 #define CLK_MOUT_CORE			58
77 #define CLK_MOUT_APLL			59
78 #define CLK_MOUT_ACLK_266_SUB		60
79 #define CLK_MOUT_UART2			61
80 #define CLK_MOUT_MMC2			62
81 
82 /* Dividers */
83 #define CLK_DIV_GPL			64
84 #define CLK_DIV_GDL			65
85 #define CLK_DIV_GPR			66
86 #define CLK_DIV_GDR			67
87 #define CLK_DIV_MPLL_PRE		68
88 #define CLK_DIV_ACLK_400_MCUISP		69
89 #define CLK_DIV_EBI			70
90 #define CLK_DIV_ACLK_200		71
91 #define CLK_DIV_ACLK_160		72
92 #define CLK_DIV_ACLK_100		73
93 #define CLK_DIV_ACLK_266		74
94 #define CLK_DIV_CAM1			75
95 #define CLK_DIV_CAM_BLK			76
96 #define CLK_DIV_MFC			77
97 #define CLK_DIV_G3D			78
98 #define CLK_DIV_MIPI0_PRE		79
99 #define CLK_DIV_MIPI0			80
100 #define CLK_DIV_FIMD0			81
101 #define CLK_DIV_UART_ISP		82
102 #define CLK_DIV_SPI1_ISP_PRE		83
103 #define CLK_DIV_SPI1_ISP		84
104 #define CLK_DIV_SPI0_ISP_PRE		85
105 #define CLK_DIV_SPI0_ISP		86
106 #define CLK_DIV_TSADC_PRE		87
107 #define CLK_DIV_TSADC			88
108 #define CLK_DIV_MMC1_PRE		89
109 #define CLK_DIV_MMC1			90
110 #define CLK_DIV_MMC0_PRE		91
111 #define CLK_DIV_MMC0			92
112 #define CLK_DIV_UART1			93
113 #define CLK_DIV_UART0			94
114 #define CLK_DIV_SPI1_PRE		95
115 #define CLK_DIV_SPI1			96
116 #define CLK_DIV_SPI0_PRE		97
117 #define CLK_DIV_SPI0			98
118 #define CLK_DIV_PCM			99
119 #define CLK_DIV_AUDIO			100
120 #define CLK_DIV_I2S			101
121 #define CLK_DIV_CORE2			102
122 #define CLK_DIV_APLL			103
123 #define CLK_DIV_PCLK_DBG		104
124 #define CLK_DIV_ATB			105
125 #define CLK_DIV_COREM			106
126 #define CLK_DIV_CORE			107
127 #define CLK_DIV_HPM			108
128 #define CLK_DIV_COPY			109
129 #define CLK_DIV_UART2			110
130 #define CLK_DIV_MMC2_PRE		111
131 #define CLK_DIV_MMC2			112
132 
133 /* Gates */
134 #define CLK_ASYNC_G3D			128
135 #define CLK_ASYNC_MFCL			129
136 #define CLK_PPMULEFT			130
137 #define CLK_GPIO_LEFT			131
138 #define CLK_ASYNC_ISPMX			132
139 #define CLK_ASYNC_FSYSD			133
140 #define CLK_ASYNC_LCD0X			134
141 #define CLK_ASYNC_CAMX			135
142 #define CLK_PPMURIGHT			136
143 #define CLK_GPIO_RIGHT			137
144 #define CLK_MONOCNT			138
145 #define CLK_TZPC6			139
146 #define CLK_PROVISIONKEY1		140
147 #define CLK_PROVISIONKEY0		141
148 #define CLK_CMU_ISPPART			142
149 #define CLK_TMU_APBIF			143
150 #define CLK_KEYIF			144
151 #define CLK_RTC				145
152 #define CLK_WDT				146
153 #define CLK_MCT				147
154 #define CLK_SECKEY			148
155 #define CLK_TZPC5			149
156 #define CLK_TZPC4			150
157 #define CLK_TZPC3			151
158 #define CLK_TZPC2			152
159 #define CLK_TZPC1			153
160 #define CLK_TZPC0			154
161 #define CLK_CMU_COREPART		155
162 #define CLK_CMU_TOPPART			156
163 #define CLK_PMU_APBIF			157
164 #define CLK_SYSREG			158
165 #define CLK_CHIP_ID			159
166 #define CLK_QEJPEG			160
167 #define CLK_PIXELASYNCM1		161
168 #define CLK_PIXELASYNCM0		162
169 #define CLK_PPMUCAMIF			163
170 #define CLK_QEM2MSCALER			164
171 #define CLK_QEGSCALER1			165
172 #define CLK_QEGSCALER0			166
173 #define CLK_SMMUJPEG			167
174 #define CLK_SMMUM2M2SCALER		168
175 #define CLK_SMMUGSCALER1		169
176 #define CLK_SMMUGSCALER0		170
177 #define CLK_JPEG			171
178 #define CLK_M2MSCALER			172
179 #define CLK_GSCALER1			173
180 #define CLK_GSCALER0			174
181 #define CLK_QEMFC			175
182 #define CLK_PPMUMFC_L			176
183 #define CLK_SMMUMFC_L			177
184 #define CLK_MFC				178
185 #define CLK_SMMUG3D			179
186 #define CLK_QEG3D			180
187 #define CLK_PPMUG3D			181
188 #define CLK_G3D				182
189 #define CLK_QE_CH1_LCD			183
190 #define CLK_QE_CH0_LCD			184
191 #define CLK_PPMULCD0			185
192 #define CLK_SMMUFIMD0			186
193 #define CLK_DSIM0			187
194 #define CLK_FIMD0			188
195 #define CLK_CAM1			189
196 #define CLK_UART_ISP_TOP		190
197 #define CLK_SPI1_ISP_TOP		191
198 #define CLK_SPI0_ISP_TOP		192
199 #define CLK_TSADC			193
200 #define CLK_PPMUFILE			194
201 #define CLK_USBOTG			195
202 #define CLK_USBHOST			196
203 #define CLK_SROMC			197
204 #define CLK_SDMMC1			198
205 #define CLK_SDMMC0			199
206 #define CLK_PDMA1			200
207 #define CLK_PDMA0			201
208 #define CLK_PWM				202
209 #define CLK_PCM				203
210 #define CLK_I2S				204
211 #define CLK_SPI1			205
212 #define CLK_SPI0			206
213 #define CLK_I2C7			207
214 #define CLK_I2C6			208
215 #define CLK_I2C5			209
216 #define CLK_I2C4			210
217 #define CLK_I2C3			211
218 #define CLK_I2C2			212
219 #define CLK_I2C1			213
220 #define CLK_I2C0			214
221 #define CLK_UART1			215
222 #define CLK_UART0			216
223 #define CLK_BLOCK_LCD			217
224 #define CLK_BLOCK_G3D			218
225 #define CLK_BLOCK_MFC			219
226 #define CLK_BLOCK_CAM			220
227 #define CLK_SMIES			221
228 #define CLK_UART2			222
229 #define CLK_SDMMC2			223
230 
231 /* Special clocks */
232 #define CLK_SCLK_JPEG			224
233 #define CLK_SCLK_M2MSCALER		225
234 #define CLK_SCLK_GSCALER1		226
235 #define CLK_SCLK_GSCALER0		227
236 #define CLK_SCLK_MFC			228
237 #define CLK_SCLK_G3D			229
238 #define CLK_SCLK_MIPIDPHY2L		230
239 #define CLK_SCLK_MIPI0			231
240 #define CLK_SCLK_FIMD0			232
241 #define CLK_SCLK_CAM1			233
242 #define CLK_SCLK_UART_ISP		234
243 #define CLK_SCLK_SPI1_ISP		235
244 #define CLK_SCLK_SPI0_ISP		236
245 #define CLK_SCLK_UPLL			237
246 #define CLK_SCLK_TSADC			238
247 #define CLK_SCLK_EBI			239
248 #define CLK_SCLK_MMC1			240
249 #define CLK_SCLK_MMC0			241
250 #define CLK_SCLK_I2S			242
251 #define CLK_SCLK_PCM			243
252 #define CLK_SCLK_SPI1			244
253 #define CLK_SCLK_SPI0			245
254 #define CLK_SCLK_UART1			246
255 #define CLK_SCLK_UART0			247
256 #define CLK_SCLK_UART2			248
257 #define CLK_SCLK_MMC2			249
258 
259 /*
260  * Total number of clocks of main CMU.
261  * NOTE: Must be equal to last clock ID increased by one.
262  */
263 #define CLK_NR_CLKS			250
264 
265 /*
266  * CMU DMC
267  */
268 
269 #define CLK_FOUT_BPLL			1
270 #define CLK_FOUT_EPLL			2
271 
272 /* Muxes */
273 #define CLK_MOUT_MPLL_MIF		8
274 #define CLK_MOUT_BPLL			9
275 #define CLK_MOUT_DPHY			10
276 #define CLK_MOUT_DMC_BUS		11
277 #define CLK_MOUT_EPLL			12
278 
279 /* Dividers */
280 #define CLK_DIV_DMC			16
281 #define CLK_DIV_DPHY			17
282 #define CLK_DIV_DMC_PRE			18
283 #define CLK_DIV_DMCP			19
284 #define CLK_DIV_DMCD			20
285 
286 /*
287  * Total number of clocks of main CMU.
288  * NOTE: Must be equal to last clock ID increased by one.
289  */
290 #define NR_CLKS_DMC			21
291 
292 /*
293  * CMU ISP
294  */
295 
296 /* Dividers */
297 
298 #define CLK_DIV_ISP1			1
299 #define CLK_DIV_ISP0			2
300 #define CLK_DIV_MCUISP1			3
301 #define CLK_DIV_MCUISP0			4
302 #define CLK_DIV_MPWM			5
303 
304 /* Gates */
305 
306 #define CLK_UART_ISP			8
307 #define CLK_WDT_ISP			9
308 #define CLK_PWM_ISP			10
309 #define CLK_I2C1_ISP			11
310 #define CLK_I2C0_ISP			12
311 #define CLK_MPWM_ISP			13
312 #define CLK_MCUCTL_ISP			14
313 #define CLK_PPMUISPX			15
314 #define CLK_PPMUISPMX			16
315 #define CLK_QE_LITE1			17
316 #define CLK_QE_LITE0			18
317 #define CLK_QE_FD			19
318 #define CLK_QE_DRC			20
319 #define CLK_QE_ISP			21
320 #define CLK_CSIS1			22
321 #define CLK_SMMU_LITE1			23
322 #define CLK_SMMU_LITE0			24
323 #define CLK_SMMU_FD			25
324 #define CLK_SMMU_DRC			26
325 #define CLK_SMMU_ISP			27
326 #define CLK_GICISP			28
327 #define CLK_CSIS0			29
328 #define CLK_MCUISP			30
329 #define CLK_LITE1			31
330 #define CLK_LITE0			32
331 #define CLK_FD				33
332 #define CLK_DRC				34
333 #define CLK_ISP				35
334 #define CLK_QE_ISPCX			36
335 #define CLK_QE_SCALERP			37
336 #define CLK_QE_SCALERC			38
337 #define CLK_SMMU_SCALERP		39
338 #define CLK_SMMU_SCALERC		40
339 #define CLK_SCALERP			41
340 #define CLK_SCALERC			42
341 #define CLK_SPI1_ISP			43
342 #define CLK_SPI0_ISP			44
343 #define CLK_SMMU_ISPCX			45
344 #define CLK_ASYNCAXIM			46
345 #define CLK_SCLK_MPWM_ISP		47
346 
347 /*
348  * Total number of clocks of CMU_ISP.
349  * NOTE: Must be equal to last clock ID increased by one.
350  */
351 #define NR_CLKS_ISP			48
352 
353 #endif /* _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H */
354