1d6dc6753SAlim Akhtar /* SPDX-License-Identifier: GPL-2.0 */ 2d6dc6753SAlim Akhtar /* 3d6dc6753SAlim Akhtar * Copyright (c) 2017 - 2022: Samsung Electronics Co., Ltd. 4d6dc6753SAlim Akhtar * https://www.samsung.com 5d6dc6753SAlim Akhtar * Copyright (c) 2017-2022 Tesla, Inc. 6d6dc6753SAlim Akhtar * https://www.tesla.com 7d6dc6753SAlim Akhtar * 8d6dc6753SAlim Akhtar * The constants defined in this header are being used in dts 9d6dc6753SAlim Akhtar * and fsd platform driver. 10d6dc6753SAlim Akhtar */ 11d6dc6753SAlim Akhtar 12d6dc6753SAlim Akhtar #ifndef _DT_BINDINGS_CLOCK_FSD_H 13d6dc6753SAlim Akhtar #define _DT_BINDINGS_CLOCK_FSD_H 14d6dc6753SAlim Akhtar 15d6dc6753SAlim Akhtar /* CMU */ 16d6dc6753SAlim Akhtar #define DOUT_CMU_PLL_SHARED0_DIV4 1 17d6dc6753SAlim Akhtar #define DOUT_CMU_PERIC_SHARED1DIV36 2 18d6dc6753SAlim Akhtar #define DOUT_CMU_PERIC_SHARED0DIV3_TBUCLK 3 19d6dc6753SAlim Akhtar #define DOUT_CMU_PERIC_SHARED0DIV20 4 20d6dc6753SAlim Akhtar #define DOUT_CMU_PERIC_SHARED1DIV4_DMACLK 5 21d6dc6753SAlim Akhtar #define DOUT_CMU_PLL_SHARED0_DIV6 6 22d6dc6753SAlim Akhtar #define DOUT_CMU_FSYS0_SHARED1DIV4 7 23d6dc6753SAlim Akhtar #define DOUT_CMU_FSYS0_SHARED0DIV4 8 24d6dc6753SAlim Akhtar #define DOUT_CMU_FSYS1_SHARED0DIV8 9 25d6dc6753SAlim Akhtar #define DOUT_CMU_FSYS1_SHARED0DIV4 10 26d6dc6753SAlim Akhtar #define CMU_CPUCL_SWITCH_GATE 11 27d6dc6753SAlim Akhtar #define DOUT_CMU_IMEM_TCUCLK 12 28d6dc6753SAlim Akhtar #define DOUT_CMU_IMEM_ACLK 13 29d6dc6753SAlim Akhtar #define DOUT_CMU_IMEM_DMACLK 14 30d6dc6753SAlim Akhtar #define GAT_CMU_FSYS0_SHARED0DIV4 15 31d6dc6753SAlim Akhtar #define CMU_NR_CLK 16 32d6dc6753SAlim Akhtar 33d6dc6753SAlim Akhtar /* PERIC */ 34d6dc6753SAlim Akhtar #define PERIC_SCLK_UART0 1 35d6dc6753SAlim Akhtar #define PERIC_PCLK_UART0 2 36d6dc6753SAlim Akhtar #define PERIC_SCLK_UART1 3 37d6dc6753SAlim Akhtar #define PERIC_PCLK_UART1 4 38d6dc6753SAlim Akhtar #define PERIC_DMA0_IPCLKPORT_ACLK 5 39d6dc6753SAlim Akhtar #define PERIC_DMA1_IPCLKPORT_ACLK 6 40d6dc6753SAlim Akhtar #define PERIC_PWM0_IPCLKPORT_I_PCLK_S0 7 41d6dc6753SAlim Akhtar #define PERIC_PWM1_IPCLKPORT_I_PCLK_S0 8 42d6dc6753SAlim Akhtar #define PERIC_PCLK_SPI0 9 43d6dc6753SAlim Akhtar #define PERIC_SCLK_SPI0 10 44d6dc6753SAlim Akhtar #define PERIC_PCLK_SPI1 11 45d6dc6753SAlim Akhtar #define PERIC_SCLK_SPI1 12 46d6dc6753SAlim Akhtar #define PERIC_PCLK_SPI2 13 47d6dc6753SAlim Akhtar #define PERIC_SCLK_SPI2 14 48d6dc6753SAlim Akhtar #define PERIC_PCLK_TDM0 15 49d6dc6753SAlim Akhtar #define PERIC_PCLK_HSI2C0 16 50d6dc6753SAlim Akhtar #define PERIC_PCLK_HSI2C1 17 51d6dc6753SAlim Akhtar #define PERIC_PCLK_HSI2C2 18 52d6dc6753SAlim Akhtar #define PERIC_PCLK_HSI2C3 19 53d6dc6753SAlim Akhtar #define PERIC_PCLK_HSI2C4 20 54d6dc6753SAlim Akhtar #define PERIC_PCLK_HSI2C5 21 55d6dc6753SAlim Akhtar #define PERIC_PCLK_HSI2C6 22 56d6dc6753SAlim Akhtar #define PERIC_PCLK_HSI2C7 23 57d6dc6753SAlim Akhtar #define PERIC_MCAN0_IPCLKPORT_CCLK 24 58d6dc6753SAlim Akhtar #define PERIC_MCAN0_IPCLKPORT_PCLK 25 59d6dc6753SAlim Akhtar #define PERIC_MCAN1_IPCLKPORT_CCLK 26 60d6dc6753SAlim Akhtar #define PERIC_MCAN1_IPCLKPORT_PCLK 27 61d6dc6753SAlim Akhtar #define PERIC_MCAN2_IPCLKPORT_CCLK 28 62d6dc6753SAlim Akhtar #define PERIC_MCAN2_IPCLKPORT_PCLK 29 63d6dc6753SAlim Akhtar #define PERIC_MCAN3_IPCLKPORT_CCLK 30 64d6dc6753SAlim Akhtar #define PERIC_MCAN3_IPCLKPORT_PCLK 31 65d6dc6753SAlim Akhtar #define PERIC_PCLK_ADCIF 32 66d6dc6753SAlim Akhtar #define PERIC_EQOS_TOP_IPCLKPORT_CLK_PTP_REF_I 33 67d6dc6753SAlim Akhtar #define PERIC_EQOS_TOP_IPCLKPORT_ACLK_I 34 68d6dc6753SAlim Akhtar #define PERIC_EQOS_TOP_IPCLKPORT_HCLK_I 35 69d6dc6753SAlim Akhtar #define PERIC_EQOS_TOP_IPCLKPORT_RGMII_CLK_I 36 70d6dc6753SAlim Akhtar #define PERIC_EQOS_TOP_IPCLKPORT_CLK_RX_I 37 71d6dc6753SAlim Akhtar #define PERIC_BUS_D_PERIC_IPCLKPORT_EQOSCLK 38 72d6dc6753SAlim Akhtar #define PERIC_BUS_P_PERIC_IPCLKPORT_EQOSCLK 39 73d6dc6753SAlim Akhtar #define PERIC_HCLK_TDM0 40 74d6dc6753SAlim Akhtar #define PERIC_PCLK_TDM1 41 75d6dc6753SAlim Akhtar #define PERIC_HCLK_TDM1 42 76d6dc6753SAlim Akhtar #define PERIC_EQOS_PHYRXCLK_MUX 43 77d6dc6753SAlim Akhtar #define PERIC_EQOS_PHYRXCLK 44 78d6dc6753SAlim Akhtar #define PERIC_DOUT_RGMII_CLK 45 79d6dc6753SAlim Akhtar #define PERIC_NR_CLK 46 80d6dc6753SAlim Akhtar 81d6dc6753SAlim Akhtar /* FSYS0 */ 82d6dc6753SAlim Akhtar #define UFS0_MPHY_REFCLK_IXTAL24 1 83d6dc6753SAlim Akhtar #define UFS0_MPHY_REFCLK_IXTAL26 2 84d6dc6753SAlim Akhtar #define UFS1_MPHY_REFCLK_IXTAL24 3 85d6dc6753SAlim Akhtar #define UFS1_MPHY_REFCLK_IXTAL26 4 86d6dc6753SAlim Akhtar #define UFS0_TOP0_HCLK_BUS 5 87d6dc6753SAlim Akhtar #define UFS0_TOP0_ACLK 6 88d6dc6753SAlim Akhtar #define UFS0_TOP0_CLK_UNIPRO 7 89d6dc6753SAlim Akhtar #define UFS0_TOP0_FMP_CLK 8 90d6dc6753SAlim Akhtar #define UFS1_TOP1_HCLK_BUS 9 91d6dc6753SAlim Akhtar #define UFS1_TOP1_ACLK 10 92d6dc6753SAlim Akhtar #define UFS1_TOP1_CLK_UNIPRO 11 93d6dc6753SAlim Akhtar #define UFS1_TOP1_FMP_CLK 12 94d6dc6753SAlim Akhtar #define PCIE_SUBCTRL_INST0_DBI_ACLK_SOC 13 95d6dc6753SAlim Akhtar #define PCIE_SUBCTRL_INST0_AUX_CLK_SOC 14 96d6dc6753SAlim Akhtar #define PCIE_SUBCTRL_INST0_MSTR_ACLK_SOC 15 97d6dc6753SAlim Akhtar #define PCIE_SUBCTRL_INST0_SLV_ACLK_SOC 16 98d6dc6753SAlim Akhtar #define FSYS0_EQOS_TOP0_IPCLKPORT_CLK_PTP_REF_I 17 99d6dc6753SAlim Akhtar #define FSYS0_EQOS_TOP0_IPCLKPORT_ACLK_I 18 100d6dc6753SAlim Akhtar #define FSYS0_EQOS_TOP0_IPCLKPORT_HCLK_I 19 101d6dc6753SAlim Akhtar #define FSYS0_EQOS_TOP0_IPCLKPORT_RGMII_CLK_I 20 102d6dc6753SAlim Akhtar #define FSYS0_EQOS_TOP0_IPCLKPORT_CLK_RX_I 21 103d6dc6753SAlim Akhtar #define FSYS0_DOUT_FSYS0_PERIBUS_GRP 22 104d6dc6753SAlim Akhtar #define FSYS0_NR_CLK 23 105d6dc6753SAlim Akhtar 106d6dc6753SAlim Akhtar /* FSYS1 */ 107d6dc6753SAlim Akhtar #define PCIE_LINK0_IPCLKPORT_DBI_ACLK 1 108d6dc6753SAlim Akhtar #define PCIE_LINK0_IPCLKPORT_AUX_ACLK 2 109d6dc6753SAlim Akhtar #define PCIE_LINK0_IPCLKPORT_MSTR_ACLK 3 110d6dc6753SAlim Akhtar #define PCIE_LINK0_IPCLKPORT_SLV_ACLK 4 111d6dc6753SAlim Akhtar #define PCIE_LINK1_IPCLKPORT_DBI_ACLK 5 112d6dc6753SAlim Akhtar #define PCIE_LINK1_IPCLKPORT_AUX_ACLK 6 113d6dc6753SAlim Akhtar #define PCIE_LINK1_IPCLKPORT_MSTR_ACLK 7 114d6dc6753SAlim Akhtar #define PCIE_LINK1_IPCLKPORT_SLV_ACLK 8 115d6dc6753SAlim Akhtar #define FSYS1_NR_CLK 9 116d6dc6753SAlim Akhtar 117d6dc6753SAlim Akhtar /* IMEM */ 118d6dc6753SAlim Akhtar #define IMEM_DMA0_IPCLKPORT_ACLK 1 119d6dc6753SAlim Akhtar #define IMEM_DMA1_IPCLKPORT_ACLK 2 120d6dc6753SAlim Akhtar #define IMEM_WDT0_IPCLKPORT_PCLK 3 121d6dc6753SAlim Akhtar #define IMEM_WDT1_IPCLKPORT_PCLK 4 122d6dc6753SAlim Akhtar #define IMEM_WDT2_IPCLKPORT_PCLK 5 123d6dc6753SAlim Akhtar #define IMEM_MCT_PCLK 6 124d6dc6753SAlim Akhtar #define IMEM_TMU_CPU0_IPCLKPORT_I_CLK_TS 7 125d6dc6753SAlim Akhtar #define IMEM_TMU_CPU2_IPCLKPORT_I_CLK_TS 8 126d6dc6753SAlim Akhtar #define IMEM_TMU_TOP_IPCLKPORT_I_CLK_TS 9 127d6dc6753SAlim Akhtar #define IMEM_TMU_GPU_IPCLKPORT_I_CLK_TS 10 128d6dc6753SAlim Akhtar #define IMEM_TMU_GT_IPCLKPORT_I_CLK_TS 11 129d6dc6753SAlim Akhtar #define IMEM_NR_CLK 12 130d6dc6753SAlim Akhtar 131d6dc6753SAlim Akhtar /* MFC */ 132d6dc6753SAlim Akhtar #define MFC_MFC_IPCLKPORT_ACLK 1 133d6dc6753SAlim Akhtar #define MFC_NR_CLK 2 134d6dc6753SAlim Akhtar 135d6dc6753SAlim Akhtar /* CAM_CSI */ 136d6dc6753SAlim Akhtar #define CAM_CSI0_0_IPCLKPORT_I_ACLK 1 137d6dc6753SAlim Akhtar #define CAM_CSI0_1_IPCLKPORT_I_ACLK 2 138d6dc6753SAlim Akhtar #define CAM_CSI0_2_IPCLKPORT_I_ACLK 3 139d6dc6753SAlim Akhtar #define CAM_CSI0_3_IPCLKPORT_I_ACLK 4 140d6dc6753SAlim Akhtar #define CAM_CSI1_0_IPCLKPORT_I_ACLK 5 141d6dc6753SAlim Akhtar #define CAM_CSI1_1_IPCLKPORT_I_ACLK 6 142d6dc6753SAlim Akhtar #define CAM_CSI1_2_IPCLKPORT_I_ACLK 7 143d6dc6753SAlim Akhtar #define CAM_CSI1_3_IPCLKPORT_I_ACLK 8 144d6dc6753SAlim Akhtar #define CAM_CSI2_0_IPCLKPORT_I_ACLK 9 145d6dc6753SAlim Akhtar #define CAM_CSI2_1_IPCLKPORT_I_ACLK 10 146d6dc6753SAlim Akhtar #define CAM_CSI2_2_IPCLKPORT_I_ACLK 11 147d6dc6753SAlim Akhtar #define CAM_CSI2_3_IPCLKPORT_I_ACLK 12 148d6dc6753SAlim Akhtar #define CAM_CSI_NR_CLK 13 149d6dc6753SAlim Akhtar 150d6dc6753SAlim Akhtar #endif /*_DT_BINDINGS_CLOCK_FSD_H */ 151