1*1ccea77eSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 2c80dfd9bSPan Wen /* 3c80dfd9bSPan Wen * Copyright (c) 2016 HiSilicon Technologies Co., Ltd. 4c80dfd9bSPan Wen */ 5c80dfd9bSPan Wen 6c80dfd9bSPan Wen #ifndef __DTS_HI3516CV300_CLOCK_H 7c80dfd9bSPan Wen #define __DTS_HI3516CV300_CLOCK_H 8c80dfd9bSPan Wen 9c80dfd9bSPan Wen /* hi3516CV300 core CRG */ 10c80dfd9bSPan Wen #define HI3516CV300_APB_CLK 0 11c80dfd9bSPan Wen #define HI3516CV300_UART0_CLK 1 12c80dfd9bSPan Wen #define HI3516CV300_UART1_CLK 2 13c80dfd9bSPan Wen #define HI3516CV300_UART2_CLK 3 14c80dfd9bSPan Wen #define HI3516CV300_SPI0_CLK 4 15c80dfd9bSPan Wen #define HI3516CV300_SPI1_CLK 5 16c80dfd9bSPan Wen #define HI3516CV300_FMC_CLK 6 17c80dfd9bSPan Wen #define HI3516CV300_MMC0_CLK 7 18c80dfd9bSPan Wen #define HI3516CV300_MMC1_CLK 8 19c80dfd9bSPan Wen #define HI3516CV300_MMC2_CLK 9 20c80dfd9bSPan Wen #define HI3516CV300_MMC3_CLK 10 21c80dfd9bSPan Wen #define HI3516CV300_ETH_CLK 11 22c80dfd9bSPan Wen #define HI3516CV300_ETH_MACIF_CLK 12 23c80dfd9bSPan Wen #define HI3516CV300_DMAC_CLK 13 24c80dfd9bSPan Wen #define HI3516CV300_PWM_CLK 14 25c80dfd9bSPan Wen #define HI3516CV300_USB2_BUS_CLK 15 26c80dfd9bSPan Wen #define HI3516CV300_USB2_OHCI48M_CLK 16 27c80dfd9bSPan Wen #define HI3516CV300_USB2_OHCI12M_CLK 17 28c80dfd9bSPan Wen #define HI3516CV300_USB2_OTG_UTMI_CLK 18 29c80dfd9bSPan Wen #define HI3516CV300_USB2_HST_PHY_CLK 19 30c80dfd9bSPan Wen #define HI3516CV300_USB2_UTMI0_CLK 20 31c80dfd9bSPan Wen #define HI3516CV300_USB2_PHY_CLK 21 32c80dfd9bSPan Wen 33c80dfd9bSPan Wen /* hi3516CV300 sysctrl CRG */ 34c80dfd9bSPan Wen #define HI3516CV300_WDT_CLK 1 35c80dfd9bSPan Wen 36c80dfd9bSPan Wen #endif /* __DTS_HI3516CV300_CLOCK_H */ 37