1*1ccea77eSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */
26c9da387SJiancheng Xue /*
36c9da387SJiancheng Xue  * Copyright (c) 2015 HiSilicon Technologies Co., Ltd.
46c9da387SJiancheng Xue  */
56c9da387SJiancheng Xue 
66c9da387SJiancheng Xue #ifndef __DTS_HI3519_CLOCK_H
76c9da387SJiancheng Xue #define __DTS_HI3519_CLOCK_H
86c9da387SJiancheng Xue 
96c9da387SJiancheng Xue #define HI3519_FMC_CLK			1
106c9da387SJiancheng Xue #define HI3519_SPI0_CLK			2
116c9da387SJiancheng Xue #define HI3519_SPI1_CLK			3
126c9da387SJiancheng Xue #define HI3519_SPI2_CLK			4
136c9da387SJiancheng Xue #define HI3519_UART0_CLK		5
146c9da387SJiancheng Xue #define HI3519_UART1_CLK		6
156c9da387SJiancheng Xue #define HI3519_UART2_CLK		7
166c9da387SJiancheng Xue #define HI3519_UART3_CLK		8
176c9da387SJiancheng Xue #define HI3519_UART4_CLK		9
186c9da387SJiancheng Xue #define HI3519_PWM_CLK			10
196c9da387SJiancheng Xue #define HI3519_DMA_CLK			11
206c9da387SJiancheng Xue #define HI3519_IR_CLK			12
216c9da387SJiancheng Xue #define HI3519_ETH_PHY_CLK		13
226c9da387SJiancheng Xue #define HI3519_ETH_MAC_CLK		14
236c9da387SJiancheng Xue #define HI3519_ETH_MACIF_CLK		15
246c9da387SJiancheng Xue #define HI3519_USB2_BUS_CLK		16
256c9da387SJiancheng Xue #define HI3519_USB2_PORT_CLK		17
266c9da387SJiancheng Xue #define HI3519_USB3_CLK			18
276c9da387SJiancheng Xue 
286c9da387SJiancheng Xue #endif	/* __DTS_HI3519_CLOCK_H */
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