1*d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2490dd880SLucas Stach /* 3490dd880SLucas Stach * Copyright 2013 Lucas Stach, Pengutronix <l.stach@pengutronix.de> 4490dd880SLucas Stach */ 5490dd880SLucas Stach 6490dd880SLucas Stach #ifndef __DT_BINDINGS_CLOCK_IMX5_H 7490dd880SLucas Stach #define __DT_BINDINGS_CLOCK_IMX5_H 8490dd880SLucas Stach 9490dd880SLucas Stach #define IMX5_CLK_DUMMY 0 10490dd880SLucas Stach #define IMX5_CLK_CKIL 1 11490dd880SLucas Stach #define IMX5_CLK_OSC 2 12490dd880SLucas Stach #define IMX5_CLK_CKIH1 3 13490dd880SLucas Stach #define IMX5_CLK_CKIH2 4 14490dd880SLucas Stach #define IMX5_CLK_AHB 5 15490dd880SLucas Stach #define IMX5_CLK_IPG 6 16490dd880SLucas Stach #define IMX5_CLK_AXI_A 7 17490dd880SLucas Stach #define IMX5_CLK_AXI_B 8 18490dd880SLucas Stach #define IMX5_CLK_UART_PRED 9 19490dd880SLucas Stach #define IMX5_CLK_UART_ROOT 10 20490dd880SLucas Stach #define IMX5_CLK_ESDHC_A_PRED 11 21490dd880SLucas Stach #define IMX5_CLK_ESDHC_B_PRED 12 22490dd880SLucas Stach #define IMX5_CLK_ESDHC_C_SEL 13 23490dd880SLucas Stach #define IMX5_CLK_ESDHC_D_SEL 14 24490dd880SLucas Stach #define IMX5_CLK_EMI_SEL 15 25490dd880SLucas Stach #define IMX5_CLK_EMI_SLOW_PODF 16 26490dd880SLucas Stach #define IMX5_CLK_NFC_PODF 17 27490dd880SLucas Stach #define IMX5_CLK_ECSPI_PRED 18 28490dd880SLucas Stach #define IMX5_CLK_ECSPI_PODF 19 29490dd880SLucas Stach #define IMX5_CLK_USBOH3_PRED 20 30490dd880SLucas Stach #define IMX5_CLK_USBOH3_PODF 21 31490dd880SLucas Stach #define IMX5_CLK_USB_PHY_PRED 22 32490dd880SLucas Stach #define IMX5_CLK_USB_PHY_PODF 23 33490dd880SLucas Stach #define IMX5_CLK_CPU_PODF 24 34490dd880SLucas Stach #define IMX5_CLK_DI_PRED 25 35490dd880SLucas Stach #define IMX5_CLK_TVE_SEL 27 36490dd880SLucas Stach #define IMX5_CLK_UART1_IPG_GATE 28 37490dd880SLucas Stach #define IMX5_CLK_UART1_PER_GATE 29 38490dd880SLucas Stach #define IMX5_CLK_UART2_IPG_GATE 30 39490dd880SLucas Stach #define IMX5_CLK_UART2_PER_GATE 31 40490dd880SLucas Stach #define IMX5_CLK_UART3_IPG_GATE 32 41490dd880SLucas Stach #define IMX5_CLK_UART3_PER_GATE 33 42490dd880SLucas Stach #define IMX5_CLK_I2C1_GATE 34 43490dd880SLucas Stach #define IMX5_CLK_I2C2_GATE 35 44490dd880SLucas Stach #define IMX5_CLK_GPT_IPG_GATE 36 45490dd880SLucas Stach #define IMX5_CLK_PWM1_IPG_GATE 37 46490dd880SLucas Stach #define IMX5_CLK_PWM1_HF_GATE 38 47490dd880SLucas Stach #define IMX5_CLK_PWM2_IPG_GATE 39 48490dd880SLucas Stach #define IMX5_CLK_PWM2_HF_GATE 40 49490dd880SLucas Stach #define IMX5_CLK_GPT_HF_GATE 41 50490dd880SLucas Stach #define IMX5_CLK_FEC_GATE 42 51490dd880SLucas Stach #define IMX5_CLK_USBOH3_PER_GATE 43 52490dd880SLucas Stach #define IMX5_CLK_ESDHC1_IPG_GATE 44 53490dd880SLucas Stach #define IMX5_CLK_ESDHC2_IPG_GATE 45 54490dd880SLucas Stach #define IMX5_CLK_ESDHC3_IPG_GATE 46 55490dd880SLucas Stach #define IMX5_CLK_ESDHC4_IPG_GATE 47 56490dd880SLucas Stach #define IMX5_CLK_SSI1_IPG_GATE 48 57490dd880SLucas Stach #define IMX5_CLK_SSI2_IPG_GATE 49 58490dd880SLucas Stach #define IMX5_CLK_SSI3_IPG_GATE 50 59490dd880SLucas Stach #define IMX5_CLK_ECSPI1_IPG_GATE 51 60490dd880SLucas Stach #define IMX5_CLK_ECSPI1_PER_GATE 52 61490dd880SLucas Stach #define IMX5_CLK_ECSPI2_IPG_GATE 53 62490dd880SLucas Stach #define IMX5_CLK_ECSPI2_PER_GATE 54 63490dd880SLucas Stach #define IMX5_CLK_CSPI_IPG_GATE 55 64490dd880SLucas Stach #define IMX5_CLK_SDMA_GATE 56 65490dd880SLucas Stach #define IMX5_CLK_EMI_SLOW_GATE 57 66490dd880SLucas Stach #define IMX5_CLK_IPU_SEL 58 67490dd880SLucas Stach #define IMX5_CLK_IPU_GATE 59 68490dd880SLucas Stach #define IMX5_CLK_NFC_GATE 60 69490dd880SLucas Stach #define IMX5_CLK_IPU_DI1_GATE 61 70490dd880SLucas Stach #define IMX5_CLK_VPU_SEL 62 71490dd880SLucas Stach #define IMX5_CLK_VPU_GATE 63 72490dd880SLucas Stach #define IMX5_CLK_VPU_REFERENCE_GATE 64 73490dd880SLucas Stach #define IMX5_CLK_UART4_IPG_GATE 65 74490dd880SLucas Stach #define IMX5_CLK_UART4_PER_GATE 66 75490dd880SLucas Stach #define IMX5_CLK_UART5_IPG_GATE 67 76490dd880SLucas Stach #define IMX5_CLK_UART5_PER_GATE 68 77490dd880SLucas Stach #define IMX5_CLK_TVE_GATE 69 78490dd880SLucas Stach #define IMX5_CLK_TVE_PRED 70 79490dd880SLucas Stach #define IMX5_CLK_ESDHC1_PER_GATE 71 80490dd880SLucas Stach #define IMX5_CLK_ESDHC2_PER_GATE 72 81490dd880SLucas Stach #define IMX5_CLK_ESDHC3_PER_GATE 73 82490dd880SLucas Stach #define IMX5_CLK_ESDHC4_PER_GATE 74 83490dd880SLucas Stach #define IMX5_CLK_USB_PHY_GATE 75 84490dd880SLucas Stach #define IMX5_CLK_HSI2C_GATE 76 85490dd880SLucas Stach #define IMX5_CLK_MIPI_HSC1_GATE 77 86490dd880SLucas Stach #define IMX5_CLK_MIPI_HSC2_GATE 78 87490dd880SLucas Stach #define IMX5_CLK_MIPI_ESC_GATE 79 88490dd880SLucas Stach #define IMX5_CLK_MIPI_HSP_GATE 80 89490dd880SLucas Stach #define IMX5_CLK_LDB_DI1_DIV_3_5 81 90490dd880SLucas Stach #define IMX5_CLK_LDB_DI1_DIV 82 91490dd880SLucas Stach #define IMX5_CLK_LDB_DI0_DIV_3_5 83 92490dd880SLucas Stach #define IMX5_CLK_LDB_DI0_DIV 84 93490dd880SLucas Stach #define IMX5_CLK_LDB_DI1_GATE 85 94490dd880SLucas Stach #define IMX5_CLK_CAN2_SERIAL_GATE 86 95490dd880SLucas Stach #define IMX5_CLK_CAN2_IPG_GATE 87 96490dd880SLucas Stach #define IMX5_CLK_I2C3_GATE 88 97490dd880SLucas Stach #define IMX5_CLK_LP_APM 89 98490dd880SLucas Stach #define IMX5_CLK_PERIPH_APM 90 99490dd880SLucas Stach #define IMX5_CLK_MAIN_BUS 91 100490dd880SLucas Stach #define IMX5_CLK_AHB_MAX 92 101490dd880SLucas Stach #define IMX5_CLK_AIPS_TZ1 93 102490dd880SLucas Stach #define IMX5_CLK_AIPS_TZ2 94 103490dd880SLucas Stach #define IMX5_CLK_TMAX1 95 104490dd880SLucas Stach #define IMX5_CLK_TMAX2 96 105490dd880SLucas Stach #define IMX5_CLK_TMAX3 97 106490dd880SLucas Stach #define IMX5_CLK_SPBA 98 107490dd880SLucas Stach #define IMX5_CLK_UART_SEL 99 108490dd880SLucas Stach #define IMX5_CLK_ESDHC_A_SEL 100 109490dd880SLucas Stach #define IMX5_CLK_ESDHC_B_SEL 101 110490dd880SLucas Stach #define IMX5_CLK_ESDHC_A_PODF 102 111490dd880SLucas Stach #define IMX5_CLK_ESDHC_B_PODF 103 112490dd880SLucas Stach #define IMX5_CLK_ECSPI_SEL 104 113490dd880SLucas Stach #define IMX5_CLK_USBOH3_SEL 105 114490dd880SLucas Stach #define IMX5_CLK_USB_PHY_SEL 106 115490dd880SLucas Stach #define IMX5_CLK_IIM_GATE 107 116490dd880SLucas Stach #define IMX5_CLK_USBOH3_GATE 108 117490dd880SLucas Stach #define IMX5_CLK_EMI_FAST_GATE 109 118490dd880SLucas Stach #define IMX5_CLK_IPU_DI0_GATE 110 119490dd880SLucas Stach #define IMX5_CLK_GPC_DVFS 111 120490dd880SLucas Stach #define IMX5_CLK_PLL1_SW 112 121490dd880SLucas Stach #define IMX5_CLK_PLL2_SW 113 122490dd880SLucas Stach #define IMX5_CLK_PLL3_SW 114 123490dd880SLucas Stach #define IMX5_CLK_IPU_DI0_SEL 115 124490dd880SLucas Stach #define IMX5_CLK_IPU_DI1_SEL 116 125490dd880SLucas Stach #define IMX5_CLK_TVE_EXT_SEL 117 126490dd880SLucas Stach #define IMX5_CLK_MX51_MIPI 118 127490dd880SLucas Stach #define IMX5_CLK_PLL4_SW 119 128490dd880SLucas Stach #define IMX5_CLK_LDB_DI1_SEL 120 129490dd880SLucas Stach #define IMX5_CLK_DI_PLL4_PODF 121 130490dd880SLucas Stach #define IMX5_CLK_LDB_DI0_SEL 122 131490dd880SLucas Stach #define IMX5_CLK_LDB_DI0_GATE 123 132490dd880SLucas Stach #define IMX5_CLK_USB_PHY1_GATE 124 133490dd880SLucas Stach #define IMX5_CLK_USB_PHY2_GATE 125 134490dd880SLucas Stach #define IMX5_CLK_PER_LP_APM 126 135490dd880SLucas Stach #define IMX5_CLK_PER_PRED1 127 136490dd880SLucas Stach #define IMX5_CLK_PER_PRED2 128 137490dd880SLucas Stach #define IMX5_CLK_PER_PODF 129 138490dd880SLucas Stach #define IMX5_CLK_PER_ROOT 130 139490dd880SLucas Stach #define IMX5_CLK_SSI_APM 131 140490dd880SLucas Stach #define IMX5_CLK_SSI1_ROOT_SEL 132 141490dd880SLucas Stach #define IMX5_CLK_SSI2_ROOT_SEL 133 142490dd880SLucas Stach #define IMX5_CLK_SSI3_ROOT_SEL 134 143490dd880SLucas Stach #define IMX5_CLK_SSI_EXT1_SEL 135 144490dd880SLucas Stach #define IMX5_CLK_SSI_EXT2_SEL 136 145490dd880SLucas Stach #define IMX5_CLK_SSI_EXT1_COM_SEL 137 146490dd880SLucas Stach #define IMX5_CLK_SSI_EXT2_COM_SEL 138 147490dd880SLucas Stach #define IMX5_CLK_SSI1_ROOT_PRED 139 148490dd880SLucas Stach #define IMX5_CLK_SSI1_ROOT_PODF 140 149490dd880SLucas Stach #define IMX5_CLK_SSI2_ROOT_PRED 141 150490dd880SLucas Stach #define IMX5_CLK_SSI2_ROOT_PODF 142 151490dd880SLucas Stach #define IMX5_CLK_SSI_EXT1_PRED 143 152490dd880SLucas Stach #define IMX5_CLK_SSI_EXT1_PODF 144 153490dd880SLucas Stach #define IMX5_CLK_SSI_EXT2_PRED 145 154490dd880SLucas Stach #define IMX5_CLK_SSI_EXT2_PODF 146 155490dd880SLucas Stach #define IMX5_CLK_SSI1_ROOT_GATE 147 156490dd880SLucas Stach #define IMX5_CLK_SSI2_ROOT_GATE 148 157490dd880SLucas Stach #define IMX5_CLK_SSI3_ROOT_GATE 149 158490dd880SLucas Stach #define IMX5_CLK_SSI_EXT1_GATE 150 159490dd880SLucas Stach #define IMX5_CLK_SSI_EXT2_GATE 151 160490dd880SLucas Stach #define IMX5_CLK_EPIT1_IPG_GATE 152 161490dd880SLucas Stach #define IMX5_CLK_EPIT1_HF_GATE 153 162490dd880SLucas Stach #define IMX5_CLK_EPIT2_IPG_GATE 154 163490dd880SLucas Stach #define IMX5_CLK_EPIT2_HF_GATE 155 164490dd880SLucas Stach #define IMX5_CLK_CAN_SEL 156 165490dd880SLucas Stach #define IMX5_CLK_CAN1_SERIAL_GATE 157 166490dd880SLucas Stach #define IMX5_CLK_CAN1_IPG_GATE 158 167490dd880SLucas Stach #define IMX5_CLK_OWIRE_GATE 159 168490dd880SLucas Stach #define IMX5_CLK_GPU3D_SEL 160 169490dd880SLucas Stach #define IMX5_CLK_GPU2D_SEL 161 170490dd880SLucas Stach #define IMX5_CLK_GPU3D_GATE 162 171490dd880SLucas Stach #define IMX5_CLK_GPU2D_GATE 163 172490dd880SLucas Stach #define IMX5_CLK_GARB_GATE 164 173490dd880SLucas Stach #define IMX5_CLK_CKO1_SEL 165 174490dd880SLucas Stach #define IMX5_CLK_CKO1_PODF 166 175490dd880SLucas Stach #define IMX5_CLK_CKO1 167 176490dd880SLucas Stach #define IMX5_CLK_CKO2_SEL 168 177490dd880SLucas Stach #define IMX5_CLK_CKO2_PODF 169 178490dd880SLucas Stach #define IMX5_CLK_CKO2 170 179490dd880SLucas Stach #define IMX5_CLK_SRTC_GATE 171 180490dd880SLucas Stach #define IMX5_CLK_PATA_GATE 172 181490dd880SLucas Stach #define IMX5_CLK_SATA_GATE 173 182490dd880SLucas Stach #define IMX5_CLK_SPDIF_XTAL_SEL 174 183490dd880SLucas Stach #define IMX5_CLK_SPDIF0_SEL 175 184490dd880SLucas Stach #define IMX5_CLK_SPDIF1_SEL 176 185490dd880SLucas Stach #define IMX5_CLK_SPDIF0_PRED 177 186490dd880SLucas Stach #define IMX5_CLK_SPDIF0_PODF 178 187490dd880SLucas Stach #define IMX5_CLK_SPDIF1_PRED 179 188490dd880SLucas Stach #define IMX5_CLK_SPDIF1_PODF 180 189490dd880SLucas Stach #define IMX5_CLK_SPDIF0_COM_SEL 181 190490dd880SLucas Stach #define IMX5_CLK_SPDIF1_COM_SEL 182 191490dd880SLucas Stach #define IMX5_CLK_SPDIF0_GATE 183 192490dd880SLucas Stach #define IMX5_CLK_SPDIF1_GATE 184 193490dd880SLucas Stach #define IMX5_CLK_SPDIF_IPG_GATE 185 194490dd880SLucas Stach #define IMX5_CLK_OCRAM 186 195490dd880SLucas Stach #define IMX5_CLK_SAHARA_IPG_GATE 187 1966fb8954bSMarek Vasut #define IMX5_CLK_SATA_REF 188 1976f0628aaSLucas Stach #define IMX5_CLK_STEP_SEL 189 1986f0628aaSLucas Stach #define IMX5_CLK_CPU_PODF_SEL 190 19982a40b54SLucas Stach #define IMX5_CLK_ARM 191 200377d6479SKalle Kankare #define IMX5_CLK_FIRI_PRED 192 201377d6479SKalle Kankare #define IMX5_CLK_FIRI_SEL 193 202377d6479SKalle Kankare #define IMX5_CLK_FIRI_PODF 194 203377d6479SKalle Kankare #define IMX5_CLK_FIRI_SERIAL_GATE 195 204377d6479SKalle Kankare #define IMX5_CLK_FIRI_IPG_GATE 196 205377d6479SKalle Kankare #define IMX5_CLK_CSI0_MCLK1_PRED 197 206377d6479SKalle Kankare #define IMX5_CLK_CSI0_MCLK1_SEL 198 207377d6479SKalle Kankare #define IMX5_CLK_CSI0_MCLK1_PODF 199 208377d6479SKalle Kankare #define IMX5_CLK_CSI0_MCLK1_GATE 200 209377d6479SKalle Kankare #define IMX5_CLK_IEEE1588_PRED 201 210377d6479SKalle Kankare #define IMX5_CLK_IEEE1588_SEL 202 211377d6479SKalle Kankare #define IMX5_CLK_IEEE1588_PODF 203 212377d6479SKalle Kankare #define IMX5_CLK_IEEE1588_GATE 204 2139b15cffbSMichael Grzeschik #define IMX5_CLK_SCC2_IPG_GATE 205 2149b15cffbSMichael Grzeschik #define IMX5_CLK_END 206 215490dd880SLucas Stach 216490dd880SLucas Stach #endif /* __DT_BINDINGS_CLOCK_IMX5_H */ 217