1*d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2d5513568SAnson Huang /* 3d5513568SAnson Huang * Copyright (C) 2014 Freescale Semiconductor, Inc. 4d5513568SAnson Huang */ 5d5513568SAnson Huang 6d5513568SAnson Huang #ifndef __DT_BINDINGS_CLOCK_IMX6SX_H 7d5513568SAnson Huang #define __DT_BINDINGS_CLOCK_IMX6SX_H 8d5513568SAnson Huang 9d5513568SAnson Huang #define IMX6SX_CLK_DUMMY 0 10d5513568SAnson Huang #define IMX6SX_CLK_CKIL 1 11d5513568SAnson Huang #define IMX6SX_CLK_CKIH 2 12d5513568SAnson Huang #define IMX6SX_CLK_OSC 3 13d5513568SAnson Huang #define IMX6SX_CLK_PLL1_SYS 4 14d5513568SAnson Huang #define IMX6SX_CLK_PLL2_BUS 5 15d5513568SAnson Huang #define IMX6SX_CLK_PLL3_USB_OTG 6 16d5513568SAnson Huang #define IMX6SX_CLK_PLL4_AUDIO 7 17d5513568SAnson Huang #define IMX6SX_CLK_PLL5_VIDEO 8 18d5513568SAnson Huang #define IMX6SX_CLK_PLL6_ENET 9 19d5513568SAnson Huang #define IMX6SX_CLK_PLL7_USB_HOST 10 20d5513568SAnson Huang #define IMX6SX_CLK_USBPHY1 11 21d5513568SAnson Huang #define IMX6SX_CLK_USBPHY2 12 22d5513568SAnson Huang #define IMX6SX_CLK_USBPHY1_GATE 13 23d5513568SAnson Huang #define IMX6SX_CLK_USBPHY2_GATE 14 24d5513568SAnson Huang #define IMX6SX_CLK_PCIE_REF 15 25d5513568SAnson Huang #define IMX6SX_CLK_PCIE_REF_125M 16 26d5513568SAnson Huang #define IMX6SX_CLK_ENET_REF 17 27d5513568SAnson Huang #define IMX6SX_CLK_PLL2_PFD0 18 28d5513568SAnson Huang #define IMX6SX_CLK_PLL2_PFD1 19 29d5513568SAnson Huang #define IMX6SX_CLK_PLL2_PFD2 20 30d5513568SAnson Huang #define IMX6SX_CLK_PLL2_PFD3 21 31d5513568SAnson Huang #define IMX6SX_CLK_PLL3_PFD0 22 32d5513568SAnson Huang #define IMX6SX_CLK_PLL3_PFD1 23 33d5513568SAnson Huang #define IMX6SX_CLK_PLL3_PFD2 24 34d5513568SAnson Huang #define IMX6SX_CLK_PLL3_PFD3 25 35d5513568SAnson Huang #define IMX6SX_CLK_PLL2_198M 26 36d5513568SAnson Huang #define IMX6SX_CLK_PLL3_120M 27 37d5513568SAnson Huang #define IMX6SX_CLK_PLL3_80M 28 38d5513568SAnson Huang #define IMX6SX_CLK_PLL3_60M 29 39d5513568SAnson Huang #define IMX6SX_CLK_TWD 30 40d5513568SAnson Huang #define IMX6SX_CLK_PLL4_POST_DIV 31 41d5513568SAnson Huang #define IMX6SX_CLK_PLL4_AUDIO_DIV 32 42d5513568SAnson Huang #define IMX6SX_CLK_PLL5_POST_DIV 33 43d5513568SAnson Huang #define IMX6SX_CLK_PLL5_VIDEO_DIV 34 44d5513568SAnson Huang #define IMX6SX_CLK_STEP 35 45d5513568SAnson Huang #define IMX6SX_CLK_PLL1_SW 36 46d5513568SAnson Huang #define IMX6SX_CLK_OCRAM_SEL 37 47d5513568SAnson Huang #define IMX6SX_CLK_PERIPH_PRE 38 48d5513568SAnson Huang #define IMX6SX_CLK_PERIPH2_PRE 39 49d5513568SAnson Huang #define IMX6SX_CLK_PERIPH_CLK2_SEL 40 50d5513568SAnson Huang #define IMX6SX_CLK_PERIPH2_CLK2_SEL 41 51d5513568SAnson Huang #define IMX6SX_CLK_PCIE_AXI_SEL 42 52d5513568SAnson Huang #define IMX6SX_CLK_GPU_AXI_SEL 43 53d5513568SAnson Huang #define IMX6SX_CLK_GPU_CORE_SEL 44 54d5513568SAnson Huang #define IMX6SX_CLK_EIM_SLOW_SEL 45 55d5513568SAnson Huang #define IMX6SX_CLK_USDHC1_SEL 46 56d5513568SAnson Huang #define IMX6SX_CLK_USDHC2_SEL 47 57d5513568SAnson Huang #define IMX6SX_CLK_USDHC3_SEL 48 58d5513568SAnson Huang #define IMX6SX_CLK_USDHC4_SEL 49 59d5513568SAnson Huang #define IMX6SX_CLK_SSI1_SEL 50 60d5513568SAnson Huang #define IMX6SX_CLK_SSI2_SEL 51 61d5513568SAnson Huang #define IMX6SX_CLK_SSI3_SEL 52 62d5513568SAnson Huang #define IMX6SX_CLK_QSPI1_SEL 53 63d5513568SAnson Huang #define IMX6SX_CLK_PERCLK_SEL 54 64d5513568SAnson Huang #define IMX6SX_CLK_VID_SEL 55 65d5513568SAnson Huang #define IMX6SX_CLK_ESAI_SEL 56 66d5513568SAnson Huang #define IMX6SX_CLK_LDB_DI0_DIV_SEL 57 67d5513568SAnson Huang #define IMX6SX_CLK_LDB_DI1_DIV_SEL 58 68d5513568SAnson Huang #define IMX6SX_CLK_CAN_SEL 59 69d5513568SAnson Huang #define IMX6SX_CLK_UART_SEL 60 70d5513568SAnson Huang #define IMX6SX_CLK_QSPI2_SEL 61 71d5513568SAnson Huang #define IMX6SX_CLK_LDB_DI1_SEL 62 72d5513568SAnson Huang #define IMX6SX_CLK_LDB_DI0_SEL 63 73d5513568SAnson Huang #define IMX6SX_CLK_SPDIF_SEL 64 74d5513568SAnson Huang #define IMX6SX_CLK_AUDIO_SEL 65 75d5513568SAnson Huang #define IMX6SX_CLK_ENET_PRE_SEL 66 76d5513568SAnson Huang #define IMX6SX_CLK_ENET_SEL 67 77d5513568SAnson Huang #define IMX6SX_CLK_M4_PRE_SEL 68 78d5513568SAnson Huang #define IMX6SX_CLK_M4_SEL 69 79d5513568SAnson Huang #define IMX6SX_CLK_ECSPI_SEL 70 80d5513568SAnson Huang #define IMX6SX_CLK_LCDIF1_PRE_SEL 71 81d5513568SAnson Huang #define IMX6SX_CLK_LCDIF2_PRE_SEL 72 82d5513568SAnson Huang #define IMX6SX_CLK_LCDIF1_SEL 73 83d5513568SAnson Huang #define IMX6SX_CLK_LCDIF2_SEL 74 84d5513568SAnson Huang #define IMX6SX_CLK_DISPLAY_SEL 75 85d5513568SAnson Huang #define IMX6SX_CLK_CSI_SEL 76 86d5513568SAnson Huang #define IMX6SX_CLK_CKO1_SEL 77 87d5513568SAnson Huang #define IMX6SX_CLK_CKO2_SEL 78 88d5513568SAnson Huang #define IMX6SX_CLK_CKO 79 89d5513568SAnson Huang #define IMX6SX_CLK_PERIPH_CLK2 80 90d5513568SAnson Huang #define IMX6SX_CLK_PERIPH2_CLK2 81 91d5513568SAnson Huang #define IMX6SX_CLK_IPG 82 92d5513568SAnson Huang #define IMX6SX_CLK_GPU_CORE_PODF 83 93d5513568SAnson Huang #define IMX6SX_CLK_GPU_AXI_PODF 84 94d5513568SAnson Huang #define IMX6SX_CLK_LCDIF1_PODF 85 95d5513568SAnson Huang #define IMX6SX_CLK_QSPI1_PODF 86 96d5513568SAnson Huang #define IMX6SX_CLK_EIM_SLOW_PODF 87 97d5513568SAnson Huang #define IMX6SX_CLK_LCDIF2_PODF 88 98d5513568SAnson Huang #define IMX6SX_CLK_PERCLK 89 99d5513568SAnson Huang #define IMX6SX_CLK_VID_PODF 90 100d5513568SAnson Huang #define IMX6SX_CLK_CAN_PODF 91 101d5513568SAnson Huang #define IMX6SX_CLK_USDHC1_PODF 92 102d5513568SAnson Huang #define IMX6SX_CLK_USDHC2_PODF 93 103d5513568SAnson Huang #define IMX6SX_CLK_USDHC3_PODF 94 104d5513568SAnson Huang #define IMX6SX_CLK_USDHC4_PODF 95 105d5513568SAnson Huang #define IMX6SX_CLK_UART_PODF 96 106d5513568SAnson Huang #define IMX6SX_CLK_ESAI_PRED 97 107d5513568SAnson Huang #define IMX6SX_CLK_ESAI_PODF 98 108d5513568SAnson Huang #define IMX6SX_CLK_SSI3_PRED 99 109d5513568SAnson Huang #define IMX6SX_CLK_SSI3_PODF 100 110d5513568SAnson Huang #define IMX6SX_CLK_SSI1_PRED 101 111d5513568SAnson Huang #define IMX6SX_CLK_SSI1_PODF 102 112d5513568SAnson Huang #define IMX6SX_CLK_QSPI2_PRED 103 113d5513568SAnson Huang #define IMX6SX_CLK_QSPI2_PODF 104 114d5513568SAnson Huang #define IMX6SX_CLK_SSI2_PRED 105 115d5513568SAnson Huang #define IMX6SX_CLK_SSI2_PODF 106 116d5513568SAnson Huang #define IMX6SX_CLK_SPDIF_PRED 107 117d5513568SAnson Huang #define IMX6SX_CLK_SPDIF_PODF 108 118d5513568SAnson Huang #define IMX6SX_CLK_AUDIO_PRED 109 119d5513568SAnson Huang #define IMX6SX_CLK_AUDIO_PODF 110 120d5513568SAnson Huang #define IMX6SX_CLK_ENET_PODF 111 121d5513568SAnson Huang #define IMX6SX_CLK_M4_PODF 112 122d5513568SAnson Huang #define IMX6SX_CLK_ECSPI_PODF 113 123d5513568SAnson Huang #define IMX6SX_CLK_LCDIF1_PRED 114 124d5513568SAnson Huang #define IMX6SX_CLK_LCDIF2_PRED 115 125d5513568SAnson Huang #define IMX6SX_CLK_DISPLAY_PODF 116 126d5513568SAnson Huang #define IMX6SX_CLK_CSI_PODF 117 127d5513568SAnson Huang #define IMX6SX_CLK_LDB_DI0_DIV_3_5 118 128d5513568SAnson Huang #define IMX6SX_CLK_LDB_DI0_DIV_7 119 129d5513568SAnson Huang #define IMX6SX_CLK_LDB_DI1_DIV_3_5 120 130d5513568SAnson Huang #define IMX6SX_CLK_LDB_DI1_DIV_7 121 131d5513568SAnson Huang #define IMX6SX_CLK_CKO1_PODF 122 132d5513568SAnson Huang #define IMX6SX_CLK_CKO2_PODF 123 133d5513568SAnson Huang #define IMX6SX_CLK_PERIPH 124 134d5513568SAnson Huang #define IMX6SX_CLK_PERIPH2 125 135d5513568SAnson Huang #define IMX6SX_CLK_OCRAM 126 136d5513568SAnson Huang #define IMX6SX_CLK_AHB 127 137d5513568SAnson Huang #define IMX6SX_CLK_MMDC_PODF 128 138d5513568SAnson Huang #define IMX6SX_CLK_ARM 129 139d5513568SAnson Huang #define IMX6SX_CLK_AIPS_TZ1 130 140d5513568SAnson Huang #define IMX6SX_CLK_AIPS_TZ2 131 141d5513568SAnson Huang #define IMX6SX_CLK_APBH_DMA 132 142d5513568SAnson Huang #define IMX6SX_CLK_ASRC_GATE 133 143d5513568SAnson Huang #define IMX6SX_CLK_CAAM_MEM 134 144d5513568SAnson Huang #define IMX6SX_CLK_CAAM_ACLK 135 145d5513568SAnson Huang #define IMX6SX_CLK_CAAM_IPG 136 146d5513568SAnson Huang #define IMX6SX_CLK_CAN1_IPG 137 147d5513568SAnson Huang #define IMX6SX_CLK_CAN1_SERIAL 138 148d5513568SAnson Huang #define IMX6SX_CLK_CAN2_IPG 139 149d5513568SAnson Huang #define IMX6SX_CLK_CAN2_SERIAL 140 150d5513568SAnson Huang #define IMX6SX_CLK_CPU_DEBUG 141 151d5513568SAnson Huang #define IMX6SX_CLK_DCIC1 142 152d5513568SAnson Huang #define IMX6SX_CLK_DCIC2 143 153d5513568SAnson Huang #define IMX6SX_CLK_AIPS_TZ3 144 154d5513568SAnson Huang #define IMX6SX_CLK_ECSPI1 145 155d5513568SAnson Huang #define IMX6SX_CLK_ECSPI2 146 156d5513568SAnson Huang #define IMX6SX_CLK_ECSPI3 147 157d5513568SAnson Huang #define IMX6SX_CLK_ECSPI4 148 158d5513568SAnson Huang #define IMX6SX_CLK_ECSPI5 149 159d5513568SAnson Huang #define IMX6SX_CLK_EPIT1 150 160d5513568SAnson Huang #define IMX6SX_CLK_EPIT2 151 161d5513568SAnson Huang #define IMX6SX_CLK_ESAI_EXTAL 152 162d5513568SAnson Huang #define IMX6SX_CLK_WAKEUP 153 163d5513568SAnson Huang #define IMX6SX_CLK_GPT_BUS 154 164d5513568SAnson Huang #define IMX6SX_CLK_GPT_SERIAL 155 165d5513568SAnson Huang #define IMX6SX_CLK_GPU 156 166d5513568SAnson Huang #define IMX6SX_CLK_OCRAM_S 157 167d5513568SAnson Huang #define IMX6SX_CLK_CANFD 158 168d5513568SAnson Huang #define IMX6SX_CLK_CSI 159 169d5513568SAnson Huang #define IMX6SX_CLK_I2C1 160 170d5513568SAnson Huang #define IMX6SX_CLK_I2C2 161 171d5513568SAnson Huang #define IMX6SX_CLK_I2C3 162 172d5513568SAnson Huang #define IMX6SX_CLK_OCOTP 163 173d5513568SAnson Huang #define IMX6SX_CLK_IOMUXC 164 174d5513568SAnson Huang #define IMX6SX_CLK_IPMUX1 165 175d5513568SAnson Huang #define IMX6SX_CLK_IPMUX2 166 176d5513568SAnson Huang #define IMX6SX_CLK_IPMUX3 167 177d5513568SAnson Huang #define IMX6SX_CLK_TZASC1 168 178d5513568SAnson Huang #define IMX6SX_CLK_LCDIF_APB 169 179d5513568SAnson Huang #define IMX6SX_CLK_PXP_AXI 170 180d5513568SAnson Huang #define IMX6SX_CLK_M4 171 181d5513568SAnson Huang #define IMX6SX_CLK_ENET 172 182d5513568SAnson Huang #define IMX6SX_CLK_DISPLAY_AXI 173 183d5513568SAnson Huang #define IMX6SX_CLK_LCDIF2_PIX 174 184d5513568SAnson Huang #define IMX6SX_CLK_LCDIF1_PIX 175 185d5513568SAnson Huang #define IMX6SX_CLK_LDB_DI0 176 186d5513568SAnson Huang #define IMX6SX_CLK_QSPI1 177 187d5513568SAnson Huang #define IMX6SX_CLK_MLB 178 188d5513568SAnson Huang #define IMX6SX_CLK_MMDC_P0_FAST 179 189d5513568SAnson Huang #define IMX6SX_CLK_MMDC_P0_IPG 180 190d5513568SAnson Huang #define IMX6SX_CLK_AXI 181 191d5513568SAnson Huang #define IMX6SX_CLK_PCIE_AXI 182 192d5513568SAnson Huang #define IMX6SX_CLK_QSPI2 183 193d5513568SAnson Huang #define IMX6SX_CLK_PER1_BCH 184 194d5513568SAnson Huang #define IMX6SX_CLK_PER2_MAIN 185 195d5513568SAnson Huang #define IMX6SX_CLK_PWM1 186 196d5513568SAnson Huang #define IMX6SX_CLK_PWM2 187 197d5513568SAnson Huang #define IMX6SX_CLK_PWM3 188 198d5513568SAnson Huang #define IMX6SX_CLK_PWM4 189 199d5513568SAnson Huang #define IMX6SX_CLK_GPMI_BCH_APB 190 200d5513568SAnson Huang #define IMX6SX_CLK_GPMI_BCH 191 201d5513568SAnson Huang #define IMX6SX_CLK_GPMI_IO 192 202d5513568SAnson Huang #define IMX6SX_CLK_GPMI_APB 193 203d5513568SAnson Huang #define IMX6SX_CLK_ROM 194 204d5513568SAnson Huang #define IMX6SX_CLK_SDMA 195 205d5513568SAnson Huang #define IMX6SX_CLK_SPBA 196 206d5513568SAnson Huang #define IMX6SX_CLK_SPDIF 197 207d5513568SAnson Huang #define IMX6SX_CLK_SSI1_IPG 198 208d5513568SAnson Huang #define IMX6SX_CLK_SSI2_IPG 199 209d5513568SAnson Huang #define IMX6SX_CLK_SSI3_IPG 200 210d5513568SAnson Huang #define IMX6SX_CLK_SSI1 201 211d5513568SAnson Huang #define IMX6SX_CLK_SSI2 202 212d5513568SAnson Huang #define IMX6SX_CLK_SSI3 203 213d5513568SAnson Huang #define IMX6SX_CLK_UART_IPG 204 214d5513568SAnson Huang #define IMX6SX_CLK_UART_SERIAL 205 215d5513568SAnson Huang #define IMX6SX_CLK_SAI1 206 216d5513568SAnson Huang #define IMX6SX_CLK_SAI2 207 217d5513568SAnson Huang #define IMX6SX_CLK_USBOH3 208 218d5513568SAnson Huang #define IMX6SX_CLK_USDHC1 209 219d5513568SAnson Huang #define IMX6SX_CLK_USDHC2 210 220d5513568SAnson Huang #define IMX6SX_CLK_USDHC3 211 221d5513568SAnson Huang #define IMX6SX_CLK_USDHC4 212 222d5513568SAnson Huang #define IMX6SX_CLK_EIM_SLOW 213 223d5513568SAnson Huang #define IMX6SX_CLK_PWM8 214 224d5513568SAnson Huang #define IMX6SX_CLK_VADC 215 225d5513568SAnson Huang #define IMX6SX_CLK_GIS 216 226d5513568SAnson Huang #define IMX6SX_CLK_I2C4 217 227d5513568SAnson Huang #define IMX6SX_CLK_PWM5 218 228d5513568SAnson Huang #define IMX6SX_CLK_PWM6 219 229d5513568SAnson Huang #define IMX6SX_CLK_PWM7 220 230d5513568SAnson Huang #define IMX6SX_CLK_CKO1 221 231d5513568SAnson Huang #define IMX6SX_CLK_CKO2 222 232d5513568SAnson Huang #define IMX6SX_CLK_IPP_DI0 223 233d5513568SAnson Huang #define IMX6SX_CLK_IPP_DI1 224 234d5513568SAnson Huang #define IMX6SX_CLK_ENET_AHB 225 235d5513568SAnson Huang #define IMX6SX_CLK_OCRAM_PODF 226 236d5513568SAnson Huang #define IMX6SX_CLK_GPT_3M 227 237d5513568SAnson Huang #define IMX6SX_CLK_ENET_PTP 228 238d5513568SAnson Huang #define IMX6SX_CLK_ENET_PTP_REF 229 239d5513568SAnson Huang #define IMX6SX_CLK_ENET2_REF 230 240d5513568SAnson Huang #define IMX6SX_CLK_ENET2_REF_125M 231 241d5513568SAnson Huang #define IMX6SX_CLK_AUDIO 232 242d5513568SAnson Huang #define IMX6SX_CLK_LVDS1_SEL 233 243d5513568SAnson Huang #define IMX6SX_CLK_LVDS1_OUT 234 244d5513568SAnson Huang #define IMX6SX_CLK_ASRC_IPG 235 245d5513568SAnson Huang #define IMX6SX_CLK_ASRC_MEM 236 246d5513568SAnson Huang #define IMX6SX_CLK_SAI1_IPG 237 247d5513568SAnson Huang #define IMX6SX_CLK_SAI2_IPG 238 248d5513568SAnson Huang #define IMX6SX_CLK_ESAI_IPG 239 249d5513568SAnson Huang #define IMX6SX_CLK_ESAI_MEM 240 250db7c0659SShawn Guo #define IMX6SX_CLK_LVDS1_IN 241 251db7c0659SShawn Guo #define IMX6SX_CLK_ANACLK1 242 252db7c0659SShawn Guo #define IMX6SX_PLL1_BYPASS_SRC 243 253db7c0659SShawn Guo #define IMX6SX_PLL2_BYPASS_SRC 244 254db7c0659SShawn Guo #define IMX6SX_PLL3_BYPASS_SRC 245 255db7c0659SShawn Guo #define IMX6SX_PLL4_BYPASS_SRC 246 256db7c0659SShawn Guo #define IMX6SX_PLL5_BYPASS_SRC 247 257db7c0659SShawn Guo #define IMX6SX_PLL6_BYPASS_SRC 248 258db7c0659SShawn Guo #define IMX6SX_PLL7_BYPASS_SRC 249 259db7c0659SShawn Guo #define IMX6SX_CLK_PLL1 250 260db7c0659SShawn Guo #define IMX6SX_CLK_PLL2 251 261db7c0659SShawn Guo #define IMX6SX_CLK_PLL3 252 262db7c0659SShawn Guo #define IMX6SX_CLK_PLL4 253 263db7c0659SShawn Guo #define IMX6SX_CLK_PLL5 254 264db7c0659SShawn Guo #define IMX6SX_CLK_PLL6 255 265db7c0659SShawn Guo #define IMX6SX_CLK_PLL7 256 266db7c0659SShawn Guo #define IMX6SX_PLL1_BYPASS 257 267db7c0659SShawn Guo #define IMX6SX_PLL2_BYPASS 258 268db7c0659SShawn Guo #define IMX6SX_PLL3_BYPASS 259 269db7c0659SShawn Guo #define IMX6SX_PLL4_BYPASS 260 270db7c0659SShawn Guo #define IMX6SX_PLL5_BYPASS 261 271db7c0659SShawn Guo #define IMX6SX_PLL6_BYPASS 262 272db7c0659SShawn Guo #define IMX6SX_PLL7_BYPASS 263 27384a87250SShengjiu Wang #define IMX6SX_CLK_SPDIF_GCLK 264 2745cc73ff7SAnson Huang #define IMX6SX_CLK_LVDS2_SEL 265 2755cc73ff7SAnson Huang #define IMX6SX_CLK_LVDS2_OUT 266 2765cc73ff7SAnson Huang #define IMX6SX_CLK_LVDS2_IN 267 2775cc73ff7SAnson Huang #define IMX6SX_CLK_ANACLK2 268 278891f30bfSAnson Huang #define IMX6SX_CLK_MMDC_P1_IPG 269 279891f30bfSAnson Huang #define IMX6SX_CLK_CLK_END 270 280d5513568SAnson Huang 281d5513568SAnson Huang #endif /* __DT_BINDINGS_CLOCK_IMX6SX_H */ 282