1d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 20ed4668aSFrank Li /* 30ed4668aSFrank Li * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. 40ed4668aSFrank Li */ 50ed4668aSFrank Li 60ed4668aSFrank Li #ifndef __DT_BINDINGS_CLOCK_IMX7D_H 70ed4668aSFrank Li #define __DT_BINDINGS_CLOCK_IMX7D_H 80ed4668aSFrank Li 90ed4668aSFrank Li #define IMX7D_OSC_24M_CLK 0 100ed4668aSFrank Li #define IMX7D_PLL_ARM_MAIN 1 110ed4668aSFrank Li #define IMX7D_PLL_ARM_MAIN_CLK 2 120ed4668aSFrank Li #define IMX7D_PLL_ARM_MAIN_SRC 3 130ed4668aSFrank Li #define IMX7D_PLL_ARM_MAIN_BYPASS 4 140ed4668aSFrank Li #define IMX7D_PLL_SYS_MAIN 5 150ed4668aSFrank Li #define IMX7D_PLL_SYS_MAIN_CLK 6 160ed4668aSFrank Li #define IMX7D_PLL_SYS_MAIN_SRC 7 170ed4668aSFrank Li #define IMX7D_PLL_SYS_MAIN_BYPASS 8 180ed4668aSFrank Li #define IMX7D_PLL_SYS_MAIN_480M 9 190ed4668aSFrank Li #define IMX7D_PLL_SYS_MAIN_240M 10 200ed4668aSFrank Li #define IMX7D_PLL_SYS_MAIN_120M 11 210ed4668aSFrank Li #define IMX7D_PLL_SYS_MAIN_480M_CLK 12 220ed4668aSFrank Li #define IMX7D_PLL_SYS_MAIN_240M_CLK 13 230ed4668aSFrank Li #define IMX7D_PLL_SYS_MAIN_120M_CLK 14 240ed4668aSFrank Li #define IMX7D_PLL_SYS_PFD0_392M_CLK 15 250ed4668aSFrank Li #define IMX7D_PLL_SYS_PFD0_196M 16 260ed4668aSFrank Li #define IMX7D_PLL_SYS_PFD0_196M_CLK 17 270ed4668aSFrank Li #define IMX7D_PLL_SYS_PFD1_332M_CLK 18 280ed4668aSFrank Li #define IMX7D_PLL_SYS_PFD1_166M 19 290ed4668aSFrank Li #define IMX7D_PLL_SYS_PFD1_166M_CLK 20 300ed4668aSFrank Li #define IMX7D_PLL_SYS_PFD2_270M_CLK 21 310ed4668aSFrank Li #define IMX7D_PLL_SYS_PFD2_135M 22 320ed4668aSFrank Li #define IMX7D_PLL_SYS_PFD2_135M_CLK 23 330ed4668aSFrank Li #define IMX7D_PLL_SYS_PFD3_CLK 24 340ed4668aSFrank Li #define IMX7D_PLL_SYS_PFD4_CLK 25 350ed4668aSFrank Li #define IMX7D_PLL_SYS_PFD5_CLK 26 360ed4668aSFrank Li #define IMX7D_PLL_SYS_PFD6_CLK 27 370ed4668aSFrank Li #define IMX7D_PLL_SYS_PFD7_CLK 28 380ed4668aSFrank Li #define IMX7D_PLL_ENET_MAIN 29 390ed4668aSFrank Li #define IMX7D_PLL_ENET_MAIN_CLK 30 400ed4668aSFrank Li #define IMX7D_PLL_ENET_MAIN_SRC 31 410ed4668aSFrank Li #define IMX7D_PLL_ENET_MAIN_BYPASS 32 420ed4668aSFrank Li #define IMX7D_PLL_ENET_MAIN_500M 33 430ed4668aSFrank Li #define IMX7D_PLL_ENET_MAIN_250M 34 440ed4668aSFrank Li #define IMX7D_PLL_ENET_MAIN_125M 35 450ed4668aSFrank Li #define IMX7D_PLL_ENET_MAIN_100M 36 460ed4668aSFrank Li #define IMX7D_PLL_ENET_MAIN_50M 37 470ed4668aSFrank Li #define IMX7D_PLL_ENET_MAIN_40M 38 480ed4668aSFrank Li #define IMX7D_PLL_ENET_MAIN_25M 39 490ed4668aSFrank Li #define IMX7D_PLL_ENET_MAIN_500M_CLK 40 500ed4668aSFrank Li #define IMX7D_PLL_ENET_MAIN_250M_CLK 41 510ed4668aSFrank Li #define IMX7D_PLL_ENET_MAIN_125M_CLK 42 520ed4668aSFrank Li #define IMX7D_PLL_ENET_MAIN_100M_CLK 43 530ed4668aSFrank Li #define IMX7D_PLL_ENET_MAIN_50M_CLK 44 540ed4668aSFrank Li #define IMX7D_PLL_ENET_MAIN_40M_CLK 45 550ed4668aSFrank Li #define IMX7D_PLL_ENET_MAIN_25M_CLK 46 560ed4668aSFrank Li #define IMX7D_PLL_DRAM_MAIN 47 570ed4668aSFrank Li #define IMX7D_PLL_DRAM_MAIN_CLK 48 580ed4668aSFrank Li #define IMX7D_PLL_DRAM_MAIN_SRC 49 590ed4668aSFrank Li #define IMX7D_PLL_DRAM_MAIN_BYPASS 50 600ed4668aSFrank Li #define IMX7D_PLL_DRAM_MAIN_533M 51 610ed4668aSFrank Li #define IMX7D_PLL_DRAM_MAIN_533M_CLK 52 620ed4668aSFrank Li #define IMX7D_PLL_AUDIO_MAIN 53 630ed4668aSFrank Li #define IMX7D_PLL_AUDIO_MAIN_CLK 54 640ed4668aSFrank Li #define IMX7D_PLL_AUDIO_MAIN_SRC 55 650ed4668aSFrank Li #define IMX7D_PLL_AUDIO_MAIN_BYPASS 56 660ed4668aSFrank Li #define IMX7D_PLL_VIDEO_MAIN_CLK 57 670ed4668aSFrank Li #define IMX7D_PLL_VIDEO_MAIN 58 680ed4668aSFrank Li #define IMX7D_PLL_VIDEO_MAIN_SRC 59 690ed4668aSFrank Li #define IMX7D_PLL_VIDEO_MAIN_BYPASS 60 700ed4668aSFrank Li #define IMX7D_USB_MAIN_480M_CLK 61 710ed4668aSFrank Li #define IMX7D_ARM_A7_ROOT_CLK 62 720ed4668aSFrank Li #define IMX7D_ARM_A7_ROOT_SRC 63 730ed4668aSFrank Li #define IMX7D_ARM_A7_ROOT_CG 64 740ed4668aSFrank Li #define IMX7D_ARM_A7_ROOT_DIV 65 750ed4668aSFrank Li #define IMX7D_ARM_M4_ROOT_CLK 66 760ed4668aSFrank Li #define IMX7D_ARM_M4_ROOT_SRC 67 770ed4668aSFrank Li #define IMX7D_ARM_M4_ROOT_CG 68 780ed4668aSFrank Li #define IMX7D_ARM_M4_ROOT_DIV 69 79259bc283SAdriana Reus #define IMX7D_ARM_M0_ROOT_CLK 70 /* unused */ 80259bc283SAdriana Reus #define IMX7D_ARM_M0_ROOT_SRC 71 /* unused */ 81259bc283SAdriana Reus #define IMX7D_ARM_M0_ROOT_CG 72 /* unused */ 82259bc283SAdriana Reus #define IMX7D_ARM_M0_ROOT_DIV 73 /* unused */ 830ed4668aSFrank Li #define IMX7D_MAIN_AXI_ROOT_CLK 74 840ed4668aSFrank Li #define IMX7D_MAIN_AXI_ROOT_SRC 75 850ed4668aSFrank Li #define IMX7D_MAIN_AXI_ROOT_CG 76 860ed4668aSFrank Li #define IMX7D_MAIN_AXI_ROOT_DIV 77 870ed4668aSFrank Li #define IMX7D_DISP_AXI_ROOT_CLK 78 880ed4668aSFrank Li #define IMX7D_DISP_AXI_ROOT_SRC 79 890ed4668aSFrank Li #define IMX7D_DISP_AXI_ROOT_CG 80 900ed4668aSFrank Li #define IMX7D_DISP_AXI_ROOT_DIV 81 910ed4668aSFrank Li #define IMX7D_ENET_AXI_ROOT_CLK 82 920ed4668aSFrank Li #define IMX7D_ENET_AXI_ROOT_SRC 83 930ed4668aSFrank Li #define IMX7D_ENET_AXI_ROOT_CG 84 940ed4668aSFrank Li #define IMX7D_ENET_AXI_ROOT_DIV 85 950ed4668aSFrank Li #define IMX7D_NAND_USDHC_BUS_ROOT_CLK 86 960ed4668aSFrank Li #define IMX7D_NAND_USDHC_BUS_ROOT_SRC 87 970ed4668aSFrank Li #define IMX7D_NAND_USDHC_BUS_ROOT_CG 88 980ed4668aSFrank Li #define IMX7D_NAND_USDHC_BUS_ROOT_DIV 89 990ed4668aSFrank Li #define IMX7D_AHB_CHANNEL_ROOT_CLK 90 1000ed4668aSFrank Li #define IMX7D_AHB_CHANNEL_ROOT_SRC 91 1010ed4668aSFrank Li #define IMX7D_AHB_CHANNEL_ROOT_CG 92 1020ed4668aSFrank Li #define IMX7D_AHB_CHANNEL_ROOT_DIV 93 1030ed4668aSFrank Li #define IMX7D_DRAM_PHYM_ROOT_CLK 94 1040ed4668aSFrank Li #define IMX7D_DRAM_PHYM_ROOT_SRC 95 1050ed4668aSFrank Li #define IMX7D_DRAM_PHYM_ROOT_CG 96 1060ed4668aSFrank Li #define IMX7D_DRAM_PHYM_ROOT_DIV 97 1070ed4668aSFrank Li #define IMX7D_DRAM_ROOT_CLK 98 1080ed4668aSFrank Li #define IMX7D_DRAM_ROOT_SRC 99 1090ed4668aSFrank Li #define IMX7D_DRAM_ROOT_CG 100 1100ed4668aSFrank Li #define IMX7D_DRAM_ROOT_DIV 101 1110ed4668aSFrank Li #define IMX7D_DRAM_PHYM_ALT_ROOT_CLK 102 1120ed4668aSFrank Li #define IMX7D_DRAM_PHYM_ALT_ROOT_SRC 103 1130ed4668aSFrank Li #define IMX7D_DRAM_PHYM_ALT_ROOT_CG 104 1140ed4668aSFrank Li #define IMX7D_DRAM_PHYM_ALT_ROOT_DIV 105 1150ed4668aSFrank Li #define IMX7D_DRAM_ALT_ROOT_CLK 106 1160ed4668aSFrank Li #define IMX7D_DRAM_ALT_ROOT_SRC 107 1170ed4668aSFrank Li #define IMX7D_DRAM_ALT_ROOT_CG 108 1180ed4668aSFrank Li #define IMX7D_DRAM_ALT_ROOT_DIV 109 1190ed4668aSFrank Li #define IMX7D_USB_HSIC_ROOT_CLK 110 1200ed4668aSFrank Li #define IMX7D_USB_HSIC_ROOT_SRC 111 1210ed4668aSFrank Li #define IMX7D_USB_HSIC_ROOT_CG 112 1220ed4668aSFrank Li #define IMX7D_USB_HSIC_ROOT_DIV 113 1230ed4668aSFrank Li #define IMX7D_PCIE_CTRL_ROOT_CLK 114 1240ed4668aSFrank Li #define IMX7D_PCIE_CTRL_ROOT_SRC 115 1250ed4668aSFrank Li #define IMX7D_PCIE_CTRL_ROOT_CG 116 1260ed4668aSFrank Li #define IMX7D_PCIE_CTRL_ROOT_DIV 117 1270ed4668aSFrank Li #define IMX7D_PCIE_PHY_ROOT_CLK 118 1280ed4668aSFrank Li #define IMX7D_PCIE_PHY_ROOT_SRC 119 1290ed4668aSFrank Li #define IMX7D_PCIE_PHY_ROOT_CG 120 1300ed4668aSFrank Li #define IMX7D_PCIE_PHY_ROOT_DIV 121 1310ed4668aSFrank Li #define IMX7D_EPDC_PIXEL_ROOT_CLK 122 1320ed4668aSFrank Li #define IMX7D_EPDC_PIXEL_ROOT_SRC 123 1330ed4668aSFrank Li #define IMX7D_EPDC_PIXEL_ROOT_CG 124 1340ed4668aSFrank Li #define IMX7D_EPDC_PIXEL_ROOT_DIV 125 1350ed4668aSFrank Li #define IMX7D_LCDIF_PIXEL_ROOT_CLK 126 1360ed4668aSFrank Li #define IMX7D_LCDIF_PIXEL_ROOT_SRC 127 1370ed4668aSFrank Li #define IMX7D_LCDIF_PIXEL_ROOT_CG 128 1380ed4668aSFrank Li #define IMX7D_LCDIF_PIXEL_ROOT_DIV 129 1390ed4668aSFrank Li #define IMX7D_MIPI_DSI_ROOT_CLK 130 1400ed4668aSFrank Li #define IMX7D_MIPI_DSI_ROOT_SRC 131 1410ed4668aSFrank Li #define IMX7D_MIPI_DSI_ROOT_CG 132 1420ed4668aSFrank Li #define IMX7D_MIPI_DSI_ROOT_DIV 133 1430ed4668aSFrank Li #define IMX7D_MIPI_CSI_ROOT_CLK 134 1440ed4668aSFrank Li #define IMX7D_MIPI_CSI_ROOT_SRC 135 1450ed4668aSFrank Li #define IMX7D_MIPI_CSI_ROOT_CG 136 1460ed4668aSFrank Li #define IMX7D_MIPI_CSI_ROOT_DIV 137 1470ed4668aSFrank Li #define IMX7D_MIPI_DPHY_ROOT_CLK 138 1480ed4668aSFrank Li #define IMX7D_MIPI_DPHY_ROOT_SRC 139 1490ed4668aSFrank Li #define IMX7D_MIPI_DPHY_ROOT_CG 140 1500ed4668aSFrank Li #define IMX7D_MIPI_DPHY_ROOT_DIV 141 1510ed4668aSFrank Li #define IMX7D_SAI1_ROOT_CLK 142 1520ed4668aSFrank Li #define IMX7D_SAI1_ROOT_SRC 143 1530ed4668aSFrank Li #define IMX7D_SAI1_ROOT_CG 144 1540ed4668aSFrank Li #define IMX7D_SAI1_ROOT_DIV 145 1550ed4668aSFrank Li #define IMX7D_SAI2_ROOT_CLK 146 1560ed4668aSFrank Li #define IMX7D_SAI2_ROOT_SRC 147 1570ed4668aSFrank Li #define IMX7D_SAI2_ROOT_CG 148 1580ed4668aSFrank Li #define IMX7D_SAI2_ROOT_DIV 149 1590ed4668aSFrank Li #define IMX7D_SAI3_ROOT_CLK 150 1600ed4668aSFrank Li #define IMX7D_SAI3_ROOT_SRC 151 1610ed4668aSFrank Li #define IMX7D_SAI3_ROOT_CG 152 1620ed4668aSFrank Li #define IMX7D_SAI3_ROOT_DIV 153 1630ed4668aSFrank Li #define IMX7D_SPDIF_ROOT_CLK 154 1640ed4668aSFrank Li #define IMX7D_SPDIF_ROOT_SRC 155 1650ed4668aSFrank Li #define IMX7D_SPDIF_ROOT_CG 156 1660ed4668aSFrank Li #define IMX7D_SPDIF_ROOT_DIV 157 1679c7150daSAnson Huang #define IMX7D_ENET1_IPG_ROOT_CLK 158 1680ed4668aSFrank Li #define IMX7D_ENET1_REF_ROOT_SRC 159 1690ed4668aSFrank Li #define IMX7D_ENET1_REF_ROOT_CG 160 1700ed4668aSFrank Li #define IMX7D_ENET1_REF_ROOT_DIV 161 1710ed4668aSFrank Li #define IMX7D_ENET1_TIME_ROOT_CLK 162 1720ed4668aSFrank Li #define IMX7D_ENET1_TIME_ROOT_SRC 163 1730ed4668aSFrank Li #define IMX7D_ENET1_TIME_ROOT_CG 164 1740ed4668aSFrank Li #define IMX7D_ENET1_TIME_ROOT_DIV 165 1759c7150daSAnson Huang #define IMX7D_ENET2_IPG_ROOT_CLK 166 1760ed4668aSFrank Li #define IMX7D_ENET2_REF_ROOT_SRC 167 1770ed4668aSFrank Li #define IMX7D_ENET2_REF_ROOT_CG 168 1780ed4668aSFrank Li #define IMX7D_ENET2_REF_ROOT_DIV 169 1790ed4668aSFrank Li #define IMX7D_ENET2_TIME_ROOT_CLK 170 1800ed4668aSFrank Li #define IMX7D_ENET2_TIME_ROOT_SRC 171 1810ed4668aSFrank Li #define IMX7D_ENET2_TIME_ROOT_CG 172 1820ed4668aSFrank Li #define IMX7D_ENET2_TIME_ROOT_DIV 173 1830ed4668aSFrank Li #define IMX7D_ENET_PHY_REF_ROOT_CLK 174 1840ed4668aSFrank Li #define IMX7D_ENET_PHY_REF_ROOT_SRC 175 1850ed4668aSFrank Li #define IMX7D_ENET_PHY_REF_ROOT_CG 176 1860ed4668aSFrank Li #define IMX7D_ENET_PHY_REF_ROOT_DIV 177 1870ed4668aSFrank Li #define IMX7D_EIM_ROOT_CLK 178 1880ed4668aSFrank Li #define IMX7D_EIM_ROOT_SRC 179 1890ed4668aSFrank Li #define IMX7D_EIM_ROOT_CG 180 1900ed4668aSFrank Li #define IMX7D_EIM_ROOT_DIV 181 1910ed4668aSFrank Li #define IMX7D_NAND_ROOT_CLK 182 1920ed4668aSFrank Li #define IMX7D_NAND_ROOT_SRC 183 1930ed4668aSFrank Li #define IMX7D_NAND_ROOT_CG 184 1940ed4668aSFrank Li #define IMX7D_NAND_ROOT_DIV 185 1950ed4668aSFrank Li #define IMX7D_QSPI_ROOT_CLK 186 1960ed4668aSFrank Li #define IMX7D_QSPI_ROOT_SRC 187 1970ed4668aSFrank Li #define IMX7D_QSPI_ROOT_CG 188 1980ed4668aSFrank Li #define IMX7D_QSPI_ROOT_DIV 189 1990ed4668aSFrank Li #define IMX7D_USDHC1_ROOT_CLK 190 2000ed4668aSFrank Li #define IMX7D_USDHC1_ROOT_SRC 191 2010ed4668aSFrank Li #define IMX7D_USDHC1_ROOT_CG 192 2020ed4668aSFrank Li #define IMX7D_USDHC1_ROOT_DIV 193 2030ed4668aSFrank Li #define IMX7D_USDHC2_ROOT_CLK 194 2040ed4668aSFrank Li #define IMX7D_USDHC2_ROOT_SRC 195 2050ed4668aSFrank Li #define IMX7D_USDHC2_ROOT_CG 196 2060ed4668aSFrank Li #define IMX7D_USDHC2_ROOT_DIV 197 2070ed4668aSFrank Li #define IMX7D_USDHC3_ROOT_CLK 198 2080ed4668aSFrank Li #define IMX7D_USDHC3_ROOT_SRC 199 2090ed4668aSFrank Li #define IMX7D_USDHC3_ROOT_CG 200 2100ed4668aSFrank Li #define IMX7D_USDHC3_ROOT_DIV 201 2110ed4668aSFrank Li #define IMX7D_CAN1_ROOT_CLK 202 2120ed4668aSFrank Li #define IMX7D_CAN1_ROOT_SRC 203 2130ed4668aSFrank Li #define IMX7D_CAN1_ROOT_CG 204 2140ed4668aSFrank Li #define IMX7D_CAN1_ROOT_DIV 205 2150ed4668aSFrank Li #define IMX7D_CAN2_ROOT_CLK 206 2160ed4668aSFrank Li #define IMX7D_CAN2_ROOT_SRC 207 2170ed4668aSFrank Li #define IMX7D_CAN2_ROOT_CG 208 2180ed4668aSFrank Li #define IMX7D_CAN2_ROOT_DIV 209 2190ed4668aSFrank Li #define IMX7D_I2C1_ROOT_CLK 210 2200ed4668aSFrank Li #define IMX7D_I2C1_ROOT_SRC 211 2210ed4668aSFrank Li #define IMX7D_I2C1_ROOT_CG 212 2220ed4668aSFrank Li #define IMX7D_I2C1_ROOT_DIV 213 2230ed4668aSFrank Li #define IMX7D_I2C2_ROOT_CLK 214 2240ed4668aSFrank Li #define IMX7D_I2C2_ROOT_SRC 215 2250ed4668aSFrank Li #define IMX7D_I2C2_ROOT_CG 216 2260ed4668aSFrank Li #define IMX7D_I2C2_ROOT_DIV 217 2270ed4668aSFrank Li #define IMX7D_I2C3_ROOT_CLK 218 2280ed4668aSFrank Li #define IMX7D_I2C3_ROOT_SRC 219 2290ed4668aSFrank Li #define IMX7D_I2C3_ROOT_CG 220 2300ed4668aSFrank Li #define IMX7D_I2C3_ROOT_DIV 221 2310ed4668aSFrank Li #define IMX7D_I2C4_ROOT_CLK 222 2320ed4668aSFrank Li #define IMX7D_I2C4_ROOT_SRC 223 2330ed4668aSFrank Li #define IMX7D_I2C4_ROOT_CG 224 2340ed4668aSFrank Li #define IMX7D_I2C4_ROOT_DIV 225 2350ed4668aSFrank Li #define IMX7D_UART1_ROOT_CLK 226 2360ed4668aSFrank Li #define IMX7D_UART1_ROOT_SRC 227 2370ed4668aSFrank Li #define IMX7D_UART1_ROOT_CG 228 2380ed4668aSFrank Li #define IMX7D_UART1_ROOT_DIV 229 2390ed4668aSFrank Li #define IMX7D_UART2_ROOT_CLK 230 2400ed4668aSFrank Li #define IMX7D_UART2_ROOT_SRC 231 2410ed4668aSFrank Li #define IMX7D_UART2_ROOT_CG 232 2420ed4668aSFrank Li #define IMX7D_UART2_ROOT_DIV 233 2430ed4668aSFrank Li #define IMX7D_UART3_ROOT_CLK 234 2440ed4668aSFrank Li #define IMX7D_UART3_ROOT_SRC 235 2450ed4668aSFrank Li #define IMX7D_UART3_ROOT_CG 236 2460ed4668aSFrank Li #define IMX7D_UART3_ROOT_DIV 237 2470ed4668aSFrank Li #define IMX7D_UART4_ROOT_CLK 238 2480ed4668aSFrank Li #define IMX7D_UART4_ROOT_SRC 239 2490ed4668aSFrank Li #define IMX7D_UART4_ROOT_CG 240 2500ed4668aSFrank Li #define IMX7D_UART4_ROOT_DIV 241 2510ed4668aSFrank Li #define IMX7D_UART5_ROOT_CLK 242 2520ed4668aSFrank Li #define IMX7D_UART5_ROOT_SRC 243 2530ed4668aSFrank Li #define IMX7D_UART5_ROOT_CG 244 2540ed4668aSFrank Li #define IMX7D_UART5_ROOT_DIV 245 2550ed4668aSFrank Li #define IMX7D_UART6_ROOT_CLK 246 2560ed4668aSFrank Li #define IMX7D_UART6_ROOT_SRC 247 2570ed4668aSFrank Li #define IMX7D_UART6_ROOT_CG 248 2580ed4668aSFrank Li #define IMX7D_UART6_ROOT_DIV 249 2590ed4668aSFrank Li #define IMX7D_UART7_ROOT_CLK 250 2600ed4668aSFrank Li #define IMX7D_UART7_ROOT_SRC 251 2610ed4668aSFrank Li #define IMX7D_UART7_ROOT_CG 252 2620ed4668aSFrank Li #define IMX7D_UART7_ROOT_DIV 253 2630ed4668aSFrank Li #define IMX7D_ECSPI1_ROOT_CLK 254 2640ed4668aSFrank Li #define IMX7D_ECSPI1_ROOT_SRC 255 2650ed4668aSFrank Li #define IMX7D_ECSPI1_ROOT_CG 256 2660ed4668aSFrank Li #define IMX7D_ECSPI1_ROOT_DIV 257 2670ed4668aSFrank Li #define IMX7D_ECSPI2_ROOT_CLK 258 2680ed4668aSFrank Li #define IMX7D_ECSPI2_ROOT_SRC 259 2690ed4668aSFrank Li #define IMX7D_ECSPI2_ROOT_CG 260 2700ed4668aSFrank Li #define IMX7D_ECSPI2_ROOT_DIV 261 2710ed4668aSFrank Li #define IMX7D_ECSPI3_ROOT_CLK 262 2720ed4668aSFrank Li #define IMX7D_ECSPI3_ROOT_SRC 263 2730ed4668aSFrank Li #define IMX7D_ECSPI3_ROOT_CG 264 2740ed4668aSFrank Li #define IMX7D_ECSPI3_ROOT_DIV 265 2750ed4668aSFrank Li #define IMX7D_ECSPI4_ROOT_CLK 266 2760ed4668aSFrank Li #define IMX7D_ECSPI4_ROOT_SRC 267 2770ed4668aSFrank Li #define IMX7D_ECSPI4_ROOT_CG 268 2780ed4668aSFrank Li #define IMX7D_ECSPI4_ROOT_DIV 269 2790ed4668aSFrank Li #define IMX7D_PWM1_ROOT_CLK 270 2800ed4668aSFrank Li #define IMX7D_PWM1_ROOT_SRC 271 2810ed4668aSFrank Li #define IMX7D_PWM1_ROOT_CG 272 2820ed4668aSFrank Li #define IMX7D_PWM1_ROOT_DIV 273 2830ed4668aSFrank Li #define IMX7D_PWM2_ROOT_CLK 274 2840ed4668aSFrank Li #define IMX7D_PWM2_ROOT_SRC 275 2850ed4668aSFrank Li #define IMX7D_PWM2_ROOT_CG 276 2860ed4668aSFrank Li #define IMX7D_PWM2_ROOT_DIV 277 2870ed4668aSFrank Li #define IMX7D_PWM3_ROOT_CLK 278 2880ed4668aSFrank Li #define IMX7D_PWM3_ROOT_SRC 279 2890ed4668aSFrank Li #define IMX7D_PWM3_ROOT_CG 280 2900ed4668aSFrank Li #define IMX7D_PWM3_ROOT_DIV 281 2910ed4668aSFrank Li #define IMX7D_PWM4_ROOT_CLK 282 2920ed4668aSFrank Li #define IMX7D_PWM4_ROOT_SRC 283 2930ed4668aSFrank Li #define IMX7D_PWM4_ROOT_CG 284 2940ed4668aSFrank Li #define IMX7D_PWM4_ROOT_DIV 285 2950ed4668aSFrank Li #define IMX7D_FLEXTIMER1_ROOT_CLK 286 2960ed4668aSFrank Li #define IMX7D_FLEXTIMER1_ROOT_SRC 287 2970ed4668aSFrank Li #define IMX7D_FLEXTIMER1_ROOT_CG 288 2980ed4668aSFrank Li #define IMX7D_FLEXTIMER1_ROOT_DIV 289 2990ed4668aSFrank Li #define IMX7D_FLEXTIMER2_ROOT_CLK 290 3000ed4668aSFrank Li #define IMX7D_FLEXTIMER2_ROOT_SRC 291 3010ed4668aSFrank Li #define IMX7D_FLEXTIMER2_ROOT_CG 292 3020ed4668aSFrank Li #define IMX7D_FLEXTIMER2_ROOT_DIV 293 3030ed4668aSFrank Li #define IMX7D_SIM1_ROOT_CLK 294 3040ed4668aSFrank Li #define IMX7D_SIM1_ROOT_SRC 295 3050ed4668aSFrank Li #define IMX7D_SIM1_ROOT_CG 296 3060ed4668aSFrank Li #define IMX7D_SIM1_ROOT_DIV 297 3070ed4668aSFrank Li #define IMX7D_SIM2_ROOT_CLK 298 3080ed4668aSFrank Li #define IMX7D_SIM2_ROOT_SRC 299 3090ed4668aSFrank Li #define IMX7D_SIM2_ROOT_CG 300 3100ed4668aSFrank Li #define IMX7D_SIM2_ROOT_DIV 301 3110ed4668aSFrank Li #define IMX7D_GPT1_ROOT_CLK 302 3120ed4668aSFrank Li #define IMX7D_GPT1_ROOT_SRC 303 3130ed4668aSFrank Li #define IMX7D_GPT1_ROOT_CG 304 3140ed4668aSFrank Li #define IMX7D_GPT1_ROOT_DIV 305 3150ed4668aSFrank Li #define IMX7D_GPT2_ROOT_CLK 306 3160ed4668aSFrank Li #define IMX7D_GPT2_ROOT_SRC 307 3170ed4668aSFrank Li #define IMX7D_GPT2_ROOT_CG 308 3180ed4668aSFrank Li #define IMX7D_GPT2_ROOT_DIV 309 3190ed4668aSFrank Li #define IMX7D_GPT3_ROOT_CLK 310 3200ed4668aSFrank Li #define IMX7D_GPT3_ROOT_SRC 311 3210ed4668aSFrank Li #define IMX7D_GPT3_ROOT_CG 312 3220ed4668aSFrank Li #define IMX7D_GPT3_ROOT_DIV 313 3230ed4668aSFrank Li #define IMX7D_GPT4_ROOT_CLK 314 3240ed4668aSFrank Li #define IMX7D_GPT4_ROOT_SRC 315 3250ed4668aSFrank Li #define IMX7D_GPT4_ROOT_CG 316 3260ed4668aSFrank Li #define IMX7D_GPT4_ROOT_DIV 317 3270ed4668aSFrank Li #define IMX7D_TRACE_ROOT_CLK 318 3280ed4668aSFrank Li #define IMX7D_TRACE_ROOT_SRC 319 3290ed4668aSFrank Li #define IMX7D_TRACE_ROOT_CG 320 3300ed4668aSFrank Li #define IMX7D_TRACE_ROOT_DIV 321 3310ed4668aSFrank Li #define IMX7D_WDOG1_ROOT_CLK 322 3320ed4668aSFrank Li #define IMX7D_WDOG_ROOT_SRC 323 3330ed4668aSFrank Li #define IMX7D_WDOG_ROOT_CG 324 3340ed4668aSFrank Li #define IMX7D_WDOG_ROOT_DIV 325 3350ed4668aSFrank Li #define IMX7D_CSI_MCLK_ROOT_CLK 326 3360ed4668aSFrank Li #define IMX7D_CSI_MCLK_ROOT_SRC 327 3370ed4668aSFrank Li #define IMX7D_CSI_MCLK_ROOT_CG 328 3380ed4668aSFrank Li #define IMX7D_CSI_MCLK_ROOT_DIV 329 3390ed4668aSFrank Li #define IMX7D_AUDIO_MCLK_ROOT_CLK 330 3400ed4668aSFrank Li #define IMX7D_AUDIO_MCLK_ROOT_SRC 331 3410ed4668aSFrank Li #define IMX7D_AUDIO_MCLK_ROOT_CG 332 3420ed4668aSFrank Li #define IMX7D_AUDIO_MCLK_ROOT_DIV 333 3430ed4668aSFrank Li #define IMX7D_WRCLK_ROOT_CLK 334 3440ed4668aSFrank Li #define IMX7D_WRCLK_ROOT_SRC 335 3450ed4668aSFrank Li #define IMX7D_WRCLK_ROOT_CG 336 3460ed4668aSFrank Li #define IMX7D_WRCLK_ROOT_DIV 337 3470ed4668aSFrank Li #define IMX7D_CLKO1_ROOT_SRC 338 3480ed4668aSFrank Li #define IMX7D_CLKO1_ROOT_CG 339 3490ed4668aSFrank Li #define IMX7D_CLKO1_ROOT_DIV 340 3500ed4668aSFrank Li #define IMX7D_CLKO2_ROOT_SRC 341 3510ed4668aSFrank Li #define IMX7D_CLKO2_ROOT_CG 342 3520ed4668aSFrank Li #define IMX7D_CLKO2_ROOT_DIV 343 3530ed4668aSFrank Li #define IMX7D_MAIN_AXI_ROOT_PRE_DIV 344 3540ed4668aSFrank Li #define IMX7D_DISP_AXI_ROOT_PRE_DIV 345 3550ed4668aSFrank Li #define IMX7D_ENET_AXI_ROOT_PRE_DIV 346 3560ed4668aSFrank Li #define IMX7D_NAND_USDHC_BUS_ROOT_PRE_DIV 347 3570ed4668aSFrank Li #define IMX7D_AHB_CHANNEL_ROOT_PRE_DIV 348 3580ed4668aSFrank Li #define IMX7D_USB_HSIC_ROOT_PRE_DIV 349 3590ed4668aSFrank Li #define IMX7D_PCIE_CTRL_ROOT_PRE_DIV 350 3600ed4668aSFrank Li #define IMX7D_PCIE_PHY_ROOT_PRE_DIV 351 3610ed4668aSFrank Li #define IMX7D_EPDC_PIXEL_ROOT_PRE_DIV 352 3620ed4668aSFrank Li #define IMX7D_LCDIF_PIXEL_ROOT_PRE_DIV 353 3630ed4668aSFrank Li #define IMX7D_MIPI_DSI_ROOT_PRE_DIV 354 3640ed4668aSFrank Li #define IMX7D_MIPI_CSI_ROOT_PRE_DIV 355 3650ed4668aSFrank Li #define IMX7D_MIPI_DPHY_ROOT_PRE_DIV 356 3660ed4668aSFrank Li #define IMX7D_SAI1_ROOT_PRE_DIV 357 3670ed4668aSFrank Li #define IMX7D_SAI2_ROOT_PRE_DIV 358 3680ed4668aSFrank Li #define IMX7D_SAI3_ROOT_PRE_DIV 359 3690ed4668aSFrank Li #define IMX7D_SPDIF_ROOT_PRE_DIV 360 3700ed4668aSFrank Li #define IMX7D_ENET1_REF_ROOT_PRE_DIV 361 3710ed4668aSFrank Li #define IMX7D_ENET1_TIME_ROOT_PRE_DIV 362 3720ed4668aSFrank Li #define IMX7D_ENET2_REF_ROOT_PRE_DIV 363 3730ed4668aSFrank Li #define IMX7D_ENET2_TIME_ROOT_PRE_DIV 364 3740ed4668aSFrank Li #define IMX7D_ENET_PHY_REF_ROOT_PRE_DIV 365 3750ed4668aSFrank Li #define IMX7D_EIM_ROOT_PRE_DIV 366 3760ed4668aSFrank Li #define IMX7D_NAND_ROOT_PRE_DIV 367 3770ed4668aSFrank Li #define IMX7D_QSPI_ROOT_PRE_DIV 368 3780ed4668aSFrank Li #define IMX7D_USDHC1_ROOT_PRE_DIV 369 3790ed4668aSFrank Li #define IMX7D_USDHC2_ROOT_PRE_DIV 370 3800ed4668aSFrank Li #define IMX7D_USDHC3_ROOT_PRE_DIV 371 3810ed4668aSFrank Li #define IMX7D_CAN1_ROOT_PRE_DIV 372 3820ed4668aSFrank Li #define IMX7D_CAN2_ROOT_PRE_DIV 373 3830ed4668aSFrank Li #define IMX7D_I2C1_ROOT_PRE_DIV 374 3840ed4668aSFrank Li #define IMX7D_I2C2_ROOT_PRE_DIV 375 3850ed4668aSFrank Li #define IMX7D_I2C3_ROOT_PRE_DIV 376 3860ed4668aSFrank Li #define IMX7D_I2C4_ROOT_PRE_DIV 377 3870ed4668aSFrank Li #define IMX7D_UART1_ROOT_PRE_DIV 378 3880ed4668aSFrank Li #define IMX7D_UART2_ROOT_PRE_DIV 379 3890ed4668aSFrank Li #define IMX7D_UART3_ROOT_PRE_DIV 380 3900ed4668aSFrank Li #define IMX7D_UART4_ROOT_PRE_DIV 381 3910ed4668aSFrank Li #define IMX7D_UART5_ROOT_PRE_DIV 382 3920ed4668aSFrank Li #define IMX7D_UART6_ROOT_PRE_DIV 383 3930ed4668aSFrank Li #define IMX7D_UART7_ROOT_PRE_DIV 384 3940ed4668aSFrank Li #define IMX7D_ECSPI1_ROOT_PRE_DIV 385 3950ed4668aSFrank Li #define IMX7D_ECSPI2_ROOT_PRE_DIV 386 3960ed4668aSFrank Li #define IMX7D_ECSPI3_ROOT_PRE_DIV 387 3970ed4668aSFrank Li #define IMX7D_ECSPI4_ROOT_PRE_DIV 388 3980ed4668aSFrank Li #define IMX7D_PWM1_ROOT_PRE_DIV 389 3990ed4668aSFrank Li #define IMX7D_PWM2_ROOT_PRE_DIV 390 4000ed4668aSFrank Li #define IMX7D_PWM3_ROOT_PRE_DIV 391 4010ed4668aSFrank Li #define IMX7D_PWM4_ROOT_PRE_DIV 392 4020ed4668aSFrank Li #define IMX7D_FLEXTIMER1_ROOT_PRE_DIV 393 4030ed4668aSFrank Li #define IMX7D_FLEXTIMER2_ROOT_PRE_DIV 394 4040ed4668aSFrank Li #define IMX7D_SIM1_ROOT_PRE_DIV 395 4050ed4668aSFrank Li #define IMX7D_SIM2_ROOT_PRE_DIV 396 4060ed4668aSFrank Li #define IMX7D_GPT1_ROOT_PRE_DIV 397 4070ed4668aSFrank Li #define IMX7D_GPT2_ROOT_PRE_DIV 398 4080ed4668aSFrank Li #define IMX7D_GPT3_ROOT_PRE_DIV 399 4090ed4668aSFrank Li #define IMX7D_GPT4_ROOT_PRE_DIV 400 4100ed4668aSFrank Li #define IMX7D_TRACE_ROOT_PRE_DIV 401 4110ed4668aSFrank Li #define IMX7D_WDOG_ROOT_PRE_DIV 402 4120ed4668aSFrank Li #define IMX7D_CSI_MCLK_ROOT_PRE_DIV 403 4130ed4668aSFrank Li #define IMX7D_AUDIO_MCLK_ROOT_PRE_DIV 404 4140ed4668aSFrank Li #define IMX7D_WRCLK_ROOT_PRE_DIV 405 4150ed4668aSFrank Li #define IMX7D_CLKO1_ROOT_PRE_DIV 406 4160ed4668aSFrank Li #define IMX7D_CLKO2_ROOT_PRE_DIV 407 4170ed4668aSFrank Li #define IMX7D_DRAM_PHYM_ALT_ROOT_PRE_DIV 408 4180ed4668aSFrank Li #define IMX7D_DRAM_ALT_ROOT_PRE_DIV 409 4190ed4668aSFrank Li #define IMX7D_LVDS1_IN_CLK 410 4200ed4668aSFrank Li #define IMX7D_LVDS1_OUT_SEL 411 4210ed4668aSFrank Li #define IMX7D_LVDS1_OUT_CLK 412 4220ed4668aSFrank Li #define IMX7D_CLK_DUMMY 413 4230ed4668aSFrank Li #define IMX7D_GPT_3M_CLK 414 4240ed4668aSFrank Li #define IMX7D_OCRAM_CLK 415 4250ed4668aSFrank Li #define IMX7D_OCRAM_S_CLK 416 4260ed4668aSFrank Li #define IMX7D_WDOG2_ROOT_CLK 417 4270ed4668aSFrank Li #define IMX7D_WDOG3_ROOT_CLK 418 4280ed4668aSFrank Li #define IMX7D_WDOG4_ROOT_CLK 419 4290ed4668aSFrank Li #define IMX7D_SDMA_CORE_CLK 420 4300ed4668aSFrank Li #define IMX7D_USB1_MAIN_480M_CLK 421 4310ed4668aSFrank Li #define IMX7D_USB_CTRL_CLK 422 4320ed4668aSFrank Li #define IMX7D_USB_PHY1_CLK 423 4330ed4668aSFrank Li #define IMX7D_USB_PHY2_CLK 424 4340ed4668aSFrank Li #define IMX7D_IPG_ROOT_CLK 425 4350ed4668aSFrank Li #define IMX7D_SAI1_IPG_CLK 426 4360ed4668aSFrank Li #define IMX7D_SAI2_IPG_CLK 427 4370ed4668aSFrank Li #define IMX7D_SAI3_IPG_CLK 428 4380ed4668aSFrank Li #define IMX7D_PLL_AUDIO_TEST_DIV 429 4390ed4668aSFrank Li #define IMX7D_PLL_AUDIO_POST_DIV 430 4400ed4668aSFrank Li #define IMX7D_PLL_VIDEO_TEST_DIV 431 4410ed4668aSFrank Li #define IMX7D_PLL_VIDEO_POST_DIV 432 4420ed4668aSFrank Li #define IMX7D_MU_ROOT_CLK 433 4430ed4668aSFrank Li #define IMX7D_SEMA4_HS_ROOT_CLK 434 4440ed4668aSFrank Li #define IMX7D_PLL_DRAM_TEST_DIV 435 445ab4c6a24SHaibo Chen #define IMX7D_ADC_ROOT_CLK 436 446fdb868cdSBai Ping #define IMX7D_CLK_ARM 437 4474aba2755SGary Bisson #define IMX7D_CKIL 438 4486847c4c2SFabio Estevam #define IMX7D_OCOTP_CLK 439 44922039d15SStefan Agner #define IMX7D_NAND_RAWNAND_CLK 440 45022039d15SStefan Agner #define IMX7D_NAND_USDHC_BUS_RAWNAND_CLK 441 451d931ba53SAnson Huang #define IMX7D_SNVS_CLK 442 452baf15cbfSRui Miguel Silva #define IMX7D_CAAM_CLK 443 4531691cc37SStefan Agner #define IMX7D_KPP_ROOT_CLK 444 454*4ae9afbaSLaurent Pinchart #define IMX7D_PXP_CLK 445 455*4ae9afbaSLaurent Pinchart #define IMX7D_CLK_END 446 4560ed4668aSFrank Li #endif /* __DT_BINDINGS_CLOCK_IMX7D_H */ 457