1*d2d04debSAjit Pandey /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2*d2d04debSAjit Pandey /* 3*d2d04debSAjit Pandey * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. 4*d2d04debSAjit Pandey */ 5*d2d04debSAjit Pandey 6*d2d04debSAjit Pandey #ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM4450_H 7*d2d04debSAjit Pandey #define _DT_BINDINGS_CLK_QCOM_GCC_SM4450_H 8*d2d04debSAjit Pandey 9*d2d04debSAjit Pandey /* GCC clocks */ 10*d2d04debSAjit Pandey #define GCC_AGGRE_NOC_PCIE_0_AXI_CLK 0 11*d2d04debSAjit Pandey #define GCC_AGGRE_UFS_PHY_AXI_CLK 1 12*d2d04debSAjit Pandey #define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 2 13*d2d04debSAjit Pandey #define GCC_AGGRE_USB3_PRIM_AXI_CLK 3 14*d2d04debSAjit Pandey #define GCC_BOOT_ROM_AHB_CLK 4 15*d2d04debSAjit Pandey #define GCC_CAMERA_AHB_CLK 5 16*d2d04debSAjit Pandey #define GCC_CAMERA_HF_AXI_CLK 6 17*d2d04debSAjit Pandey #define GCC_CAMERA_SF_AXI_CLK 7 18*d2d04debSAjit Pandey #define GCC_CAMERA_SLEEP_CLK 8 19*d2d04debSAjit Pandey #define GCC_CAMERA_XO_CLK 9 20*d2d04debSAjit Pandey #define GCC_CFG_NOC_PCIE_ANOC_AHB_CLK 10 21*d2d04debSAjit Pandey #define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 11 22*d2d04debSAjit Pandey #define GCC_DDRSS_GPU_AXI_CLK 12 23*d2d04debSAjit Pandey #define GCC_DDRSS_PCIE_SF_TBU_CLK 13 24*d2d04debSAjit Pandey #define GCC_DISP_AHB_CLK 14 25*d2d04debSAjit Pandey #define GCC_DISP_HF_AXI_CLK 15 26*d2d04debSAjit Pandey #define GCC_DISP_XO_CLK 16 27*d2d04debSAjit Pandey #define GCC_EUSB3_0_CLKREF_EN 17 28*d2d04debSAjit Pandey #define GCC_GP1_CLK 18 29*d2d04debSAjit Pandey #define GCC_GP1_CLK_SRC 19 30*d2d04debSAjit Pandey #define GCC_GP2_CLK 20 31*d2d04debSAjit Pandey #define GCC_GP2_CLK_SRC 21 32*d2d04debSAjit Pandey #define GCC_GP3_CLK 22 33*d2d04debSAjit Pandey #define GCC_GP3_CLK_SRC 23 34*d2d04debSAjit Pandey #define GCC_GPLL0 24 35*d2d04debSAjit Pandey #define GCC_GPLL0_OUT_EVEN 25 36*d2d04debSAjit Pandey #define GCC_GPLL0_OUT_ODD 26 37*d2d04debSAjit Pandey #define GCC_GPLL1 27 38*d2d04debSAjit Pandey #define GCC_GPLL3 28 39*d2d04debSAjit Pandey #define GCC_GPLL4 29 40*d2d04debSAjit Pandey #define GCC_GPLL9 30 41*d2d04debSAjit Pandey #define GCC_GPLL10 31 42*d2d04debSAjit Pandey #define GCC_GPU_CFG_AHB_CLK 32 43*d2d04debSAjit Pandey #define GCC_GPU_GPLL0_CLK_SRC 33 44*d2d04debSAjit Pandey #define GCC_GPU_GPLL0_DIV_CLK_SRC 34 45*d2d04debSAjit Pandey #define GCC_GPU_MEMNOC_GFX_CLK 35 46*d2d04debSAjit Pandey #define GCC_GPU_SNOC_DVM_GFX_CLK 36 47*d2d04debSAjit Pandey #define GCC_HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK 37 48*d2d04debSAjit Pandey #define GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK 38 49*d2d04debSAjit Pandey #define GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_CLK 39 50*d2d04debSAjit Pandey #define GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_CLK 40 51*d2d04debSAjit Pandey #define GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF0_CLK 41 52*d2d04debSAjit Pandey #define GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF1_CLK 42 53*d2d04debSAjit Pandey #define GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF0_CLK 43 54*d2d04debSAjit Pandey #define GCC_HLOS1_VOTE_MMU_TCU_CLK 44 55*d2d04debSAjit Pandey #define GCC_PCIE_0_AUX_CLK 45 56*d2d04debSAjit Pandey #define GCC_PCIE_0_AUX_CLK_SRC 46 57*d2d04debSAjit Pandey #define GCC_PCIE_0_CFG_AHB_CLK 47 58*d2d04debSAjit Pandey #define GCC_PCIE_0_CLKREF_EN 48 59*d2d04debSAjit Pandey #define GCC_PCIE_0_MSTR_AXI_CLK 49 60*d2d04debSAjit Pandey #define GCC_PCIE_0_PHY_RCHNG_CLK 50 61*d2d04debSAjit Pandey #define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 51 62*d2d04debSAjit Pandey #define GCC_PCIE_0_PIPE_CLK 52 63*d2d04debSAjit Pandey #define GCC_PCIE_0_PIPE_CLK_SRC 53 64*d2d04debSAjit Pandey #define GCC_PCIE_0_PIPE_DIV2_CLK 54 65*d2d04debSAjit Pandey #define GCC_PCIE_0_PIPE_DIV2_CLK_SRC 55 66*d2d04debSAjit Pandey #define GCC_PCIE_0_SLV_AXI_CLK 56 67*d2d04debSAjit Pandey #define GCC_PCIE_0_SLV_Q2A_AXI_CLK 57 68*d2d04debSAjit Pandey #define GCC_PDM2_CLK 58 69*d2d04debSAjit Pandey #define GCC_PDM2_CLK_SRC 59 70*d2d04debSAjit Pandey #define GCC_PDM_AHB_CLK 60 71*d2d04debSAjit Pandey #define GCC_PDM_XO4_CLK 61 72*d2d04debSAjit Pandey #define GCC_QMIP_CAMERA_NRT_AHB_CLK 62 73*d2d04debSAjit Pandey #define GCC_QMIP_CAMERA_RT_AHB_CLK 63 74*d2d04debSAjit Pandey #define GCC_QMIP_DISP_AHB_CLK 64 75*d2d04debSAjit Pandey #define GCC_QMIP_GPU_AHB_CLK 65 76*d2d04debSAjit Pandey #define GCC_QMIP_PCIE_AHB_CLK 66 77*d2d04debSAjit Pandey #define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 67 78*d2d04debSAjit Pandey #define GCC_QUPV3_WRAP0_CORE_2X_CLK 68 79*d2d04debSAjit Pandey #define GCC_QUPV3_WRAP0_CORE_CLK 69 80*d2d04debSAjit Pandey #define GCC_QUPV3_WRAP0_S0_CLK 70 81*d2d04debSAjit Pandey #define GCC_QUPV3_WRAP0_S0_CLK_SRC 71 82*d2d04debSAjit Pandey #define GCC_QUPV3_WRAP0_S1_CLK 72 83*d2d04debSAjit Pandey #define GCC_QUPV3_WRAP0_S1_CLK_SRC 73 84*d2d04debSAjit Pandey #define GCC_QUPV3_WRAP0_S2_CLK 74 85*d2d04debSAjit Pandey #define GCC_QUPV3_WRAP0_S2_CLK_SRC 75 86*d2d04debSAjit Pandey #define GCC_QUPV3_WRAP0_S3_CLK 76 87*d2d04debSAjit Pandey #define GCC_QUPV3_WRAP0_S3_CLK_SRC 77 88*d2d04debSAjit Pandey #define GCC_QUPV3_WRAP0_S4_CLK 78 89*d2d04debSAjit Pandey #define GCC_QUPV3_WRAP0_S4_CLK_SRC 79 90*d2d04debSAjit Pandey #define GCC_QUPV3_WRAP1_CORE_2X_CLK 80 91*d2d04debSAjit Pandey #define GCC_QUPV3_WRAP1_CORE_CLK 81 92*d2d04debSAjit Pandey #define GCC_QUPV3_WRAP1_S0_CLK 82 93*d2d04debSAjit Pandey #define GCC_QUPV3_WRAP1_S0_CLK_SRC 83 94*d2d04debSAjit Pandey #define GCC_QUPV3_WRAP1_S1_CLK 84 95*d2d04debSAjit Pandey #define GCC_QUPV3_WRAP1_S1_CLK_SRC 85 96*d2d04debSAjit Pandey #define GCC_QUPV3_WRAP1_S2_CLK 86 97*d2d04debSAjit Pandey #define GCC_QUPV3_WRAP1_S2_CLK_SRC 87 98*d2d04debSAjit Pandey #define GCC_QUPV3_WRAP1_S3_CLK 88 99*d2d04debSAjit Pandey #define GCC_QUPV3_WRAP1_S3_CLK_SRC 89 100*d2d04debSAjit Pandey #define GCC_QUPV3_WRAP1_S4_CLK 90 101*d2d04debSAjit Pandey #define GCC_QUPV3_WRAP1_S4_CLK_SRC 91 102*d2d04debSAjit Pandey #define GCC_QUPV3_WRAP_0_M_AHB_CLK 92 103*d2d04debSAjit Pandey #define GCC_QUPV3_WRAP_0_S_AHB_CLK 93 104*d2d04debSAjit Pandey #define GCC_QUPV3_WRAP_1_M_AHB_CLK 94 105*d2d04debSAjit Pandey #define GCC_QUPV3_WRAP_1_S_AHB_CLK 95 106*d2d04debSAjit Pandey #define GCC_SDCC1_AHB_CLK 96 107*d2d04debSAjit Pandey #define GCC_SDCC1_APPS_CLK 97 108*d2d04debSAjit Pandey #define GCC_SDCC1_APPS_CLK_SRC 98 109*d2d04debSAjit Pandey #define GCC_SDCC1_ICE_CORE_CLK 99 110*d2d04debSAjit Pandey #define GCC_SDCC1_ICE_CORE_CLK_SRC 100 111*d2d04debSAjit Pandey #define GCC_SDCC2_AHB_CLK 101 112*d2d04debSAjit Pandey #define GCC_SDCC2_APPS_CLK 102 113*d2d04debSAjit Pandey #define GCC_SDCC2_APPS_CLK_SRC 103 114*d2d04debSAjit Pandey #define GCC_UFS_0_CLKREF_EN 104 115*d2d04debSAjit Pandey #define GCC_UFS_PAD_CLKREF_EN 105 116*d2d04debSAjit Pandey #define GCC_UFS_PHY_AHB_CLK 106 117*d2d04debSAjit Pandey #define GCC_UFS_PHY_AXI_CLK 107 118*d2d04debSAjit Pandey #define GCC_UFS_PHY_AXI_CLK_SRC 108 119*d2d04debSAjit Pandey #define GCC_UFS_PHY_AXI_HW_CTL_CLK 109 120*d2d04debSAjit Pandey #define GCC_UFS_PHY_ICE_CORE_CLK 110 121*d2d04debSAjit Pandey #define GCC_UFS_PHY_ICE_CORE_CLK_SRC 111 122*d2d04debSAjit Pandey #define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 112 123*d2d04debSAjit Pandey #define GCC_UFS_PHY_PHY_AUX_CLK 113 124*d2d04debSAjit Pandey #define GCC_UFS_PHY_PHY_AUX_CLK_SRC 114 125*d2d04debSAjit Pandey #define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 115 126*d2d04debSAjit Pandey #define GCC_UFS_PHY_RX_SYMBOL_0_CLK 116 127*d2d04debSAjit Pandey #define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 117 128*d2d04debSAjit Pandey #define GCC_UFS_PHY_RX_SYMBOL_1_CLK 118 129*d2d04debSAjit Pandey #define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 119 130*d2d04debSAjit Pandey #define GCC_UFS_PHY_TX_SYMBOL_0_CLK 120 131*d2d04debSAjit Pandey #define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 121 132*d2d04debSAjit Pandey #define GCC_UFS_PHY_UNIPRO_CORE_CLK 122 133*d2d04debSAjit Pandey #define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 123 134*d2d04debSAjit Pandey #define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 124 135*d2d04debSAjit Pandey #define GCC_USB30_PRIM_MASTER_CLK 125 136*d2d04debSAjit Pandey #define GCC_USB30_PRIM_MASTER_CLK_SRC 126 137*d2d04debSAjit Pandey #define GCC_USB30_PRIM_MOCK_UTMI_CLK 127 138*d2d04debSAjit Pandey #define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 128 139*d2d04debSAjit Pandey #define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 129 140*d2d04debSAjit Pandey #define GCC_USB30_PRIM_SLEEP_CLK 130 141*d2d04debSAjit Pandey #define GCC_USB3_0_CLKREF_EN 131 142*d2d04debSAjit Pandey #define GCC_USB3_PRIM_PHY_AUX_CLK 132 143*d2d04debSAjit Pandey #define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 133 144*d2d04debSAjit Pandey #define GCC_USB3_PRIM_PHY_COM_AUX_CLK 134 145*d2d04debSAjit Pandey #define GCC_USB3_PRIM_PHY_PIPE_CLK 135 146*d2d04debSAjit Pandey #define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 136 147*d2d04debSAjit Pandey #define GCC_VCODEC0_AXI_CLK 137 148*d2d04debSAjit Pandey #define GCC_VENUS_CTL_AXI_CLK 138 149*d2d04debSAjit Pandey #define GCC_VIDEO_AHB_CLK 139 150*d2d04debSAjit Pandey #define GCC_VIDEO_THROTTLE_CORE_CLK 140 151*d2d04debSAjit Pandey #define GCC_VIDEO_VCODEC0_SYS_CLK 141 152*d2d04debSAjit Pandey #define GCC_VIDEO_VENUS_CLK_SRC 142 153*d2d04debSAjit Pandey #define GCC_VIDEO_VENUS_CTL_CLK 143 154*d2d04debSAjit Pandey #define GCC_VIDEO_XO_CLK 144 155*d2d04debSAjit Pandey 156*d2d04debSAjit Pandey /* GCC power domains */ 157*d2d04debSAjit Pandey #define GCC_PCIE_0_GDSC 0 158*d2d04debSAjit Pandey #define GCC_UFS_PHY_GDSC 1 159*d2d04debSAjit Pandey #define GCC_USB30_PRIM_GDSC 2 160*d2d04debSAjit Pandey #define GCC_VCODEC0_GDSC 3 161*d2d04debSAjit Pandey #define GCC_VENUS_GDSC 4 162*d2d04debSAjit Pandey 163*d2d04debSAjit Pandey /* GCC resets */ 164*d2d04debSAjit Pandey #define GCC_CAMERA_BCR 0 165*d2d04debSAjit Pandey #define GCC_DISPLAY_BCR 1 166*d2d04debSAjit Pandey #define GCC_GPU_BCR 2 167*d2d04debSAjit Pandey #define GCC_PCIE_0_BCR 3 168*d2d04debSAjit Pandey #define GCC_PCIE_0_LINK_DOWN_BCR 4 169*d2d04debSAjit Pandey #define GCC_PCIE_0_NOCSR_COM_PHY_BCR 5 170*d2d04debSAjit Pandey #define GCC_PCIE_0_PHY_BCR 6 171*d2d04debSAjit Pandey #define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 7 172*d2d04debSAjit Pandey #define GCC_PCIE_PHY_BCR 8 173*d2d04debSAjit Pandey #define GCC_PCIE_PHY_CFG_AHB_BCR 9 174*d2d04debSAjit Pandey #define GCC_PCIE_PHY_COM_BCR 10 175*d2d04debSAjit Pandey #define GCC_PDM_BCR 11 176*d2d04debSAjit Pandey #define GCC_QUPV3_WRAPPER_0_BCR 12 177*d2d04debSAjit Pandey #define GCC_QUPV3_WRAPPER_1_BCR 13 178*d2d04debSAjit Pandey #define GCC_QUSB2PHY_PRIM_BCR 14 179*d2d04debSAjit Pandey #define GCC_QUSB2PHY_SEC_BCR 15 180*d2d04debSAjit Pandey #define GCC_SDCC1_BCR 16 181*d2d04debSAjit Pandey #define GCC_SDCC2_BCR 17 182*d2d04debSAjit Pandey #define GCC_UFS_PHY_BCR 18 183*d2d04debSAjit Pandey #define GCC_USB30_PRIM_BCR 19 184*d2d04debSAjit Pandey #define GCC_USB3_DP_PHY_PRIM_BCR 20 185*d2d04debSAjit Pandey #define GCC_USB3_DP_PHY_SEC_BCR 21 186*d2d04debSAjit Pandey #define GCC_USB3_PHY_PRIM_BCR 22 187*d2d04debSAjit Pandey #define GCC_USB3_PHY_SEC_BCR 23 188*d2d04debSAjit Pandey #define GCC_USB3PHY_PHY_PRIM_BCR 24 189*d2d04debSAjit Pandey #define GCC_USB3PHY_PHY_SEC_BCR 25 190*d2d04debSAjit Pandey #define GCC_VCODEC0_BCR 26 191*d2d04debSAjit Pandey #define GCC_VENUS_BCR 27 192*d2d04debSAjit Pandey #define GCC_VIDEO_BCR 28 193*d2d04debSAjit Pandey #define GCC_VIDEO_VENUS_BCR 29 194*d2d04debSAjit Pandey #define GCC_VENUS_CTL_AXI_CLK_ARES 30 195*d2d04debSAjit Pandey #define GCC_VIDEO_VENUS_CTL_CLK_ARES 31 196*d2d04debSAjit Pandey 197*d2d04debSAjit Pandey #endif 198