1*fde35c9cSChris Brandt /* SPDX-License-Identifier: GPL-2.0 2*fde35c9cSChris Brandt * 3*fde35c9cSChris Brandt * Copyright (C) 2018 Renesas Electronics Corp. 4*fde35c9cSChris Brandt * 5*fde35c9cSChris Brandt */ 6*fde35c9cSChris Brandt 7*fde35c9cSChris Brandt #ifndef __DT_BINDINGS_CLOCK_R7S9210_CPG_MSSR_H__ 8*fde35c9cSChris Brandt #define __DT_BINDINGS_CLOCK_R7S9210_CPG_MSSR_H__ 9*fde35c9cSChris Brandt 10*fde35c9cSChris Brandt #include <dt-bindings/clock/renesas-cpg-mssr.h> 11*fde35c9cSChris Brandt 12*fde35c9cSChris Brandt /* R7S9210 CPG Core Clocks */ 13*fde35c9cSChris Brandt #define R7S9210_CLK_I 0 14*fde35c9cSChris Brandt #define R7S9210_CLK_G 1 15*fde35c9cSChris Brandt #define R7S9210_CLK_B 2 16*fde35c9cSChris Brandt #define R7S9210_CLK_P1 3 17*fde35c9cSChris Brandt #define R7S9210_CLK_P1C 4 18*fde35c9cSChris Brandt #define R7S9210_CLK_P0 5 19*fde35c9cSChris Brandt 20*fde35c9cSChris Brandt #endif /* __DT_BINDINGS_CLOCK_R7S9210_CPG_MSSR_H__ */ 21