196055bf7SPhil Edworthy /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 296055bf7SPhil Edworthy * 396055bf7SPhil Edworthy * Copyright (C) 2022 Renesas Electronics Corp. 496055bf7SPhil Edworthy */ 596055bf7SPhil Edworthy #ifndef __DT_BINDINGS_CLOCK_R9A09G011_CPG_H__ 696055bf7SPhil Edworthy #define __DT_BINDINGS_CLOCK_R9A09G011_CPG_H__ 796055bf7SPhil Edworthy 896055bf7SPhil Edworthy #include <dt-bindings/clock/renesas-cpg-mssr.h> 996055bf7SPhil Edworthy 1096055bf7SPhil Edworthy /* Module Clocks */ 1196055bf7SPhil Edworthy #define R9A09G011_SYS_CLK 0 1296055bf7SPhil Edworthy #define R9A09G011_PFC_PCLK 1 1396055bf7SPhil Edworthy #define R9A09G011_PMC_CORE_CLOCK 2 1496055bf7SPhil Edworthy #define R9A09G011_GIC_CLK 3 1596055bf7SPhil Edworthy #define R9A09G011_RAMA_ACLK 4 1696055bf7SPhil Edworthy #define R9A09G011_ROMA_ACLK 5 1796055bf7SPhil Edworthy #define R9A09G011_SEC_ACLK 6 1896055bf7SPhil Edworthy #define R9A09G011_SEC_PCLK 7 1996055bf7SPhil Edworthy #define R9A09G011_SEC_TCLK 8 2096055bf7SPhil Edworthy #define R9A09G011_DMAA_ACLK 9 2196055bf7SPhil Edworthy #define R9A09G011_TSU0_PCLK 10 2296055bf7SPhil Edworthy #define R9A09G011_TSU1_PCLK 11 2396055bf7SPhil Edworthy 2496055bf7SPhil Edworthy #define R9A09G011_CST_TRACECLK 12 2596055bf7SPhil Edworthy #define R9A09G011_CST_SB_CLK 13 2696055bf7SPhil Edworthy #define R9A09G011_CST_AHB_CLK 14 2796055bf7SPhil Edworthy #define R9A09G011_CST_ATB_SB_CLK 15 2896055bf7SPhil Edworthy #define R9A09G011_CST_TS_SB_CLK 16 2996055bf7SPhil Edworthy 3096055bf7SPhil Edworthy #define R9A09G011_SDI0_ACLK 17 3196055bf7SPhil Edworthy #define R9A09G011_SDI0_IMCLK 18 3296055bf7SPhil Edworthy #define R9A09G011_SDI0_IMCLK2 19 3396055bf7SPhil Edworthy #define R9A09G011_SDI0_CLK_HS 20 3496055bf7SPhil Edworthy #define R9A09G011_SDI1_ACLK 21 3596055bf7SPhil Edworthy #define R9A09G011_SDI1_IMCLK 22 3696055bf7SPhil Edworthy #define R9A09G011_SDI1_IMCLK2 23 3796055bf7SPhil Edworthy #define R9A09G011_SDI1_CLK_HS 24 3896055bf7SPhil Edworthy #define R9A09G011_EMM_ACLK 25 3996055bf7SPhil Edworthy #define R9A09G011_EMM_IMCLK 26 4096055bf7SPhil Edworthy #define R9A09G011_EMM_IMCLK2 27 4196055bf7SPhil Edworthy #define R9A09G011_EMM_CLK_HS 28 4296055bf7SPhil Edworthy #define R9A09G011_NFI_ACLK 29 4396055bf7SPhil Edworthy #define R9A09G011_NFI_NF_CLK 30 4496055bf7SPhil Edworthy 4596055bf7SPhil Edworthy #define R9A09G011_PCI_ACLK 31 4696055bf7SPhil Edworthy #define R9A09G011_PCI_CLK_PMU 32 4796055bf7SPhil Edworthy #define R9A09G011_PCI_APB_CLK 33 4896055bf7SPhil Edworthy #define R9A09G011_USB_ACLK_H 34 4996055bf7SPhil Edworthy #define R9A09G011_USB_ACLK_P 35 5096055bf7SPhil Edworthy #define R9A09G011_USB_PCLK 36 5196055bf7SPhil Edworthy #define R9A09G011_ETH0_CLK_AXI 37 5296055bf7SPhil Edworthy #define R9A09G011_ETH0_CLK_CHI 38 5396055bf7SPhil Edworthy #define R9A09G011_ETH0_GPTP_EXT 39 5496055bf7SPhil Edworthy 5596055bf7SPhil Edworthy #define R9A09G011_SDT_CLK 40 5696055bf7SPhil Edworthy #define R9A09G011_SDT_CLKAPB 41 5796055bf7SPhil Edworthy #define R9A09G011_SDT_CLK48 42 5896055bf7SPhil Edworthy #define R9A09G011_GRP_CLK 43 5996055bf7SPhil Edworthy #define R9A09G011_CIF_P0_CLK 44 6096055bf7SPhil Edworthy #define R9A09G011_CIF_P1_CLK 45 6196055bf7SPhil Edworthy #define R9A09G011_CIF_APB_CLK 46 6296055bf7SPhil Edworthy #define R9A09G011_DCI_CLKAXI 47 6396055bf7SPhil Edworthy #define R9A09G011_DCI_CLKAPB 48 6496055bf7SPhil Edworthy #define R9A09G011_DCI_CLKDCI2 49 6596055bf7SPhil Edworthy 6696055bf7SPhil Edworthy #define R9A09G011_HMI_PCLK 50 6796055bf7SPhil Edworthy #define R9A09G011_LCI_PCLK 51 6896055bf7SPhil Edworthy #define R9A09G011_LCI_ACLK 52 6996055bf7SPhil Edworthy #define R9A09G011_LCI_VCLK 53 7096055bf7SPhil Edworthy #define R9A09G011_LCI_LPCLK 54 7196055bf7SPhil Edworthy 7296055bf7SPhil Edworthy #define R9A09G011_AUI_CLK 55 7396055bf7SPhil Edworthy #define R9A09G011_AUI_CLKAXI 56 7496055bf7SPhil Edworthy #define R9A09G011_AUI_CLKAPB 57 7596055bf7SPhil Edworthy #define R9A09G011_AUMCLK 58 7696055bf7SPhil Edworthy #define R9A09G011_GMCLK0 59 7796055bf7SPhil Edworthy #define R9A09G011_GMCLK1 60 7896055bf7SPhil Edworthy #define R9A09G011_MTR_CLK0 61 7996055bf7SPhil Edworthy #define R9A09G011_MTR_CLK1 62 8096055bf7SPhil Edworthy #define R9A09G011_MTR_CLKAPB 63 8196055bf7SPhil Edworthy #define R9A09G011_GFT_CLK 64 8296055bf7SPhil Edworthy #define R9A09G011_GFT_CLKAPB 65 8396055bf7SPhil Edworthy #define R9A09G011_GFT_MCLK 66 8496055bf7SPhil Edworthy 8596055bf7SPhil Edworthy #define R9A09G011_ATGA_CLK 67 8696055bf7SPhil Edworthy #define R9A09G011_ATGA_CLKAPB 68 8796055bf7SPhil Edworthy #define R9A09G011_ATGB_CLK 69 8896055bf7SPhil Edworthy #define R9A09G011_ATGB_CLKAPB 70 8996055bf7SPhil Edworthy #define R9A09G011_SYC_CNT_CLK 71 9096055bf7SPhil Edworthy 9196055bf7SPhil Edworthy #define R9A09G011_CPERI_GRPA_PCLK 72 9296055bf7SPhil Edworthy #define R9A09G011_TIM0_CLK 73 9396055bf7SPhil Edworthy #define R9A09G011_TIM1_CLK 74 9496055bf7SPhil Edworthy #define R9A09G011_TIM2_CLK 75 9596055bf7SPhil Edworthy #define R9A09G011_TIM3_CLK 76 9696055bf7SPhil Edworthy #define R9A09G011_TIM4_CLK 77 9796055bf7SPhil Edworthy #define R9A09G011_TIM5_CLK 78 9896055bf7SPhil Edworthy #define R9A09G011_TIM6_CLK 79 9996055bf7SPhil Edworthy #define R9A09G011_TIM7_CLK 80 10096055bf7SPhil Edworthy #define R9A09G011_IIC_PCLK0 81 10196055bf7SPhil Edworthy 10296055bf7SPhil Edworthy #define R9A09G011_CPERI_GRPB_PCLK 82 10396055bf7SPhil Edworthy #define R9A09G011_TIM8_CLK 83 10496055bf7SPhil Edworthy #define R9A09G011_TIM9_CLK 84 10596055bf7SPhil Edworthy #define R9A09G011_TIM10_CLK 85 10696055bf7SPhil Edworthy #define R9A09G011_TIM11_CLK 86 10796055bf7SPhil Edworthy #define R9A09G011_TIM12_CLK 87 10896055bf7SPhil Edworthy #define R9A09G011_TIM13_CLK 88 10996055bf7SPhil Edworthy #define R9A09G011_TIM14_CLK 89 11096055bf7SPhil Edworthy #define R9A09G011_TIM15_CLK 90 11196055bf7SPhil Edworthy #define R9A09G011_IIC_PCLK1 91 11296055bf7SPhil Edworthy 11396055bf7SPhil Edworthy #define R9A09G011_CPERI_GRPC_PCLK 92 11496055bf7SPhil Edworthy #define R9A09G011_TIM16_CLK 93 11596055bf7SPhil Edworthy #define R9A09G011_TIM17_CLK 94 11696055bf7SPhil Edworthy #define R9A09G011_TIM18_CLK 95 11796055bf7SPhil Edworthy #define R9A09G011_TIM19_CLK 96 11896055bf7SPhil Edworthy #define R9A09G011_TIM20_CLK 97 11996055bf7SPhil Edworthy #define R9A09G011_TIM21_CLK 98 12096055bf7SPhil Edworthy #define R9A09G011_TIM22_CLK 99 12196055bf7SPhil Edworthy #define R9A09G011_TIM23_CLK 100 12296055bf7SPhil Edworthy #define R9A09G011_WDT0_PCLK 101 12396055bf7SPhil Edworthy #define R9A09G011_WDT0_CLK 102 12496055bf7SPhil Edworthy #define R9A09G011_WDT1_PCLK 103 12596055bf7SPhil Edworthy #define R9A09G011_WDT1_CLK 104 12696055bf7SPhil Edworthy 12796055bf7SPhil Edworthy #define R9A09G011_CPERI_GRPD_PCLK 105 12896055bf7SPhil Edworthy #define R9A09G011_TIM24_CLK 106 12996055bf7SPhil Edworthy #define R9A09G011_TIM25_CLK 107 13096055bf7SPhil Edworthy #define R9A09G011_TIM26_CLK 108 13196055bf7SPhil Edworthy #define R9A09G011_TIM27_CLK 109 13296055bf7SPhil Edworthy #define R9A09G011_TIM28_CLK 110 13396055bf7SPhil Edworthy #define R9A09G011_TIM29_CLK 111 13496055bf7SPhil Edworthy #define R9A09G011_TIM30_CLK 112 13596055bf7SPhil Edworthy #define R9A09G011_TIM31_CLK 113 13696055bf7SPhil Edworthy 13796055bf7SPhil Edworthy #define R9A09G011_CPERI_GRPE_PCLK 114 13896055bf7SPhil Edworthy #define R9A09G011_PWM0_CLK 115 13996055bf7SPhil Edworthy #define R9A09G011_PWM1_CLK 116 14096055bf7SPhil Edworthy #define R9A09G011_PWM2_CLK 117 14196055bf7SPhil Edworthy #define R9A09G011_PWM3_CLK 118 14296055bf7SPhil Edworthy #define R9A09G011_PWM4_CLK 119 14396055bf7SPhil Edworthy #define R9A09G011_PWM5_CLK 120 14496055bf7SPhil Edworthy #define R9A09G011_PWM6_CLK 121 14596055bf7SPhil Edworthy #define R9A09G011_PWM7_CLK 122 14696055bf7SPhil Edworthy 14796055bf7SPhil Edworthy #define R9A09G011_CPERI_GRPF_PCLK 123 14896055bf7SPhil Edworthy #define R9A09G011_PWM8_CLK 124 14996055bf7SPhil Edworthy #define R9A09G011_PWM9_CLK 125 15096055bf7SPhil Edworthy #define R9A09G011_PWM10_CLK 126 15196055bf7SPhil Edworthy #define R9A09G011_PWM11_CLK 127 15296055bf7SPhil Edworthy #define R9A09G011_PWM12_CLK 128 15396055bf7SPhil Edworthy #define R9A09G011_PWM13_CLK 129 15496055bf7SPhil Edworthy #define R9A09G011_PWM14_CLK 130 15596055bf7SPhil Edworthy #define R9A09G011_PWM15_CLK 131 15696055bf7SPhil Edworthy 15796055bf7SPhil Edworthy #define R9A09G011_CPERI_GRPG_PCLK 132 15896055bf7SPhil Edworthy #define R9A09G011_CPERI_GRPH_PCLK 133 15996055bf7SPhil Edworthy #define R9A09G011_URT_PCLK 134 16096055bf7SPhil Edworthy #define R9A09G011_URT0_CLK 135 16196055bf7SPhil Edworthy #define R9A09G011_URT1_CLK 136 16296055bf7SPhil Edworthy #define R9A09G011_CSI0_CLK 137 16396055bf7SPhil Edworthy #define R9A09G011_CSI1_CLK 138 16496055bf7SPhil Edworthy #define R9A09G011_CSI2_CLK 139 16596055bf7SPhil Edworthy #define R9A09G011_CSI3_CLK 140 16696055bf7SPhil Edworthy #define R9A09G011_CSI4_CLK 141 16796055bf7SPhil Edworthy #define R9A09G011_CSI5_CLK 142 16896055bf7SPhil Edworthy 16996055bf7SPhil Edworthy #define R9A09G011_ICB_ACLK1 143 17096055bf7SPhil Edworthy #define R9A09G011_ICB_GIC_CLK 144 17196055bf7SPhil Edworthy #define R9A09G011_ICB_MPCLK1 145 17296055bf7SPhil Edworthy #define R9A09G011_ICB_SPCLK1 146 17396055bf7SPhil Edworthy #define R9A09G011_ICB_CLK48 147 17496055bf7SPhil Edworthy #define R9A09G011_ICB_CLK48_2 148 17596055bf7SPhil Edworthy #define R9A09G011_ICB_CLK48_3 149 17696055bf7SPhil Edworthy #define R9A09G011_ICB_CLK48_4L 150 17796055bf7SPhil Edworthy #define R9A09G011_ICB_CLK48_4R 151 17896055bf7SPhil Edworthy #define R9A09G011_ICB_CLK48_5 152 17996055bf7SPhil Edworthy #define R9A09G011_ICB_CST_ATB_SB_CLK 153 18096055bf7SPhil Edworthy #define R9A09G011_ICB_CST_CS_CLK 154 18196055bf7SPhil Edworthy #define R9A09G011_ICB_CLK100_1 155 18296055bf7SPhil Edworthy #define R9A09G011_ICB_ETH0_CLK_AXI 156 18396055bf7SPhil Edworthy #define R9A09G011_ICB_DCI_CLKAXI 157 18496055bf7SPhil Edworthy #define R9A09G011_ICB_SYC_CNT_CLK 158 18596055bf7SPhil Edworthy 18696055bf7SPhil Edworthy #define R9A09G011_ICB_DRPA_ACLK 159 18796055bf7SPhil Edworthy #define R9A09G011_ICB_RFX_ACLK 160 18896055bf7SPhil Edworthy #define R9A09G011_ICB_RFX_PCLK5 161 18996055bf7SPhil Edworthy #define R9A09G011_ICB_MMC_ACLK 162 19096055bf7SPhil Edworthy 19196055bf7SPhil Edworthy #define R9A09G011_ICB_MPCLK3 163 19296055bf7SPhil Edworthy #define R9A09G011_ICB_CIMA_CLK 164 19396055bf7SPhil Edworthy #define R9A09G011_ICB_CIMB_CLK 165 19496055bf7SPhil Edworthy #define R9A09G011_ICB_BIMA_CLK 166 19596055bf7SPhil Edworthy #define R9A09G011_ICB_FCD_CLKAXI 167 19696055bf7SPhil Edworthy #define R9A09G011_ICB_VD_ACLK4 168 19796055bf7SPhil Edworthy #define R9A09G011_ICB_MPCLK4 169 19896055bf7SPhil Edworthy #define R9A09G011_ICB_VCD_PCLK4 170 19996055bf7SPhil Edworthy 20096055bf7SPhil Edworthy #define R9A09G011_CA53_CLK 171 20196055bf7SPhil Edworthy #define R9A09G011_CA53_ACLK 172 20296055bf7SPhil Edworthy #define R9A09G011_CA53_APCLK_DBG 173 20396055bf7SPhil Edworthy #define R9A09G011_CST_APB_CA53_CLK 174 20496055bf7SPhil Edworthy #define R9A09G011_CA53_ATCLK 175 20596055bf7SPhil Edworthy #define R9A09G011_CST_CS_CLK 176 20696055bf7SPhil Edworthy #define R9A09G011_CA53_TSCLK 177 20796055bf7SPhil Edworthy #define R9A09G011_CST_TS_CLK 178 20896055bf7SPhil Edworthy #define R9A09G011_CA53_APCLK_REG 179 20996055bf7SPhil Edworthy 21096055bf7SPhil Edworthy #define R9A09G011_DRPA_ACLK 180 21196055bf7SPhil Edworthy #define R9A09G011_DRPA_DCLK 181 21296055bf7SPhil Edworthy #define R9A09G011_DRPA_INITCLK 182 21396055bf7SPhil Edworthy 21496055bf7SPhil Edworthy #define R9A09G011_RAMB0_ACLK 183 21596055bf7SPhil Edworthy #define R9A09G011_RAMB1_ACLK 184 21696055bf7SPhil Edworthy #define R9A09G011_RAMB2_ACLK 185 21796055bf7SPhil Edworthy #define R9A09G011_RAMB3_ACLK 186 21896055bf7SPhil Edworthy 21996055bf7SPhil Edworthy #define R9A09G011_CIMA_CLKAPB 187 22096055bf7SPhil Edworthy #define R9A09G011_CIMA_CLK 188 22196055bf7SPhil Edworthy #define R9A09G011_CIMB_CLK 189 22296055bf7SPhil Edworthy #define R9A09G011_FAFA_CLK 190 22396055bf7SPhil Edworthy #define R9A09G011_STG_CLKAXI 191 22496055bf7SPhil Edworthy #define R9A09G011_STG_CLK0 192 22596055bf7SPhil Edworthy 22696055bf7SPhil Edworthy #define R9A09G011_BIMA_CLKAPB 193 22796055bf7SPhil Edworthy #define R9A09G011_BIMA_CLK 194 22896055bf7SPhil Edworthy #define R9A09G011_FAFB_CLK 195 22996055bf7SPhil Edworthy #define R9A09G011_FCD_CLK 196 23096055bf7SPhil Edworthy #define R9A09G011_FCD_CLKAXI 197 23196055bf7SPhil Edworthy 23296055bf7SPhil Edworthy #define R9A09G011_RIM_CLK 198 23396055bf7SPhil Edworthy #define R9A09G011_VCD_ACLK 199 23496055bf7SPhil Edworthy #define R9A09G011_VCD_PCLK 200 23596055bf7SPhil Edworthy #define R9A09G011_JPG0_CLK 201 23696055bf7SPhil Edworthy #define R9A09G011_JPG0_ACLK 202 23796055bf7SPhil Edworthy 23896055bf7SPhil Edworthy #define R9A09G011_MMC_CORE_DDRC_CLK 203 23996055bf7SPhil Edworthy #define R9A09G011_MMC_ACLK 204 24096055bf7SPhil Edworthy #define R9A09G011_MMC_PCLK 205 24196055bf7SPhil Edworthy #define R9A09G011_DDI_APBCLK 206 24296055bf7SPhil Edworthy 24396055bf7SPhil Edworthy /* Resets */ 24496055bf7SPhil Edworthy #define R9A09G011_SYS_RST_N 0 24596055bf7SPhil Edworthy #define R9A09G011_PFC_PRESETN 1 24696055bf7SPhil Edworthy #define R9A09G011_RAMA_ARESETN 2 24796055bf7SPhil Edworthy #define R9A09G011_ROM_ARESETN 3 24896055bf7SPhil Edworthy #define R9A09G011_DMAA_ARESETN 4 24996055bf7SPhil Edworthy #define R9A09G011_SEC_ARESETN 5 25096055bf7SPhil Edworthy #define R9A09G011_SEC_PRESETN 6 25196055bf7SPhil Edworthy #define R9A09G011_SEC_RSTB 7 25296055bf7SPhil Edworthy #define R9A09G011_TSU0_RESETN 8 25396055bf7SPhil Edworthy #define R9A09G011_TSU1_RESETN 9 25496055bf7SPhil Edworthy #define R9A09G011_PMC_RESET_N 10 25596055bf7SPhil Edworthy 25696055bf7SPhil Edworthy #define R9A09G011_CST_NTRST 11 25796055bf7SPhil Edworthy #define R9A09G011_CST_NPOTRST 12 25896055bf7SPhil Edworthy #define R9A09G011_CST_NTRST2 13 25996055bf7SPhil Edworthy #define R9A09G011_CST_CS_RESETN 14 26096055bf7SPhil Edworthy #define R9A09G011_CST_TS_RESETN 15 26196055bf7SPhil Edworthy #define R9A09G011_CST_TRESETN 16 26296055bf7SPhil Edworthy #define R9A09G011_CST_SB_RESETN 17 26396055bf7SPhil Edworthy #define R9A09G011_CST_AHB_RESETN 18 26496055bf7SPhil Edworthy #define R9A09G011_CST_TS_SB_RESETN 19 26596055bf7SPhil Edworthy #define R9A09G011_CST_APB_CA53_RESETN 20 26696055bf7SPhil Edworthy #define R9A09G011_CST_ATB_SB_RESETN 21 26796055bf7SPhil Edworthy 26896055bf7SPhil Edworthy #define R9A09G011_SDI0_IXRST 22 26996055bf7SPhil Edworthy #define R9A09G011_SDI1_IXRST 23 27096055bf7SPhil Edworthy #define R9A09G011_EMM_IXRST 24 27196055bf7SPhil Edworthy #define R9A09G011_NFI_MARESETN 25 27296055bf7SPhil Edworthy #define R9A09G011_NFI_REG_RST_N 26 27396055bf7SPhil Edworthy #define R9A09G011_USB_PRESET_N 27 27496055bf7SPhil Edworthy #define R9A09G011_USB_DRD_RESET 28 27596055bf7SPhil Edworthy #define R9A09G011_USB_ARESETN_P 29 27696055bf7SPhil Edworthy #define R9A09G011_USB_ARESETN_H 30 27796055bf7SPhil Edworthy #define R9A09G011_ETH0_RST_HW_N 31 27896055bf7SPhil Edworthy #define R9A09G011_PCI_ARESETN 32 27996055bf7SPhil Edworthy 28096055bf7SPhil Edworthy #define R9A09G011_SDT_RSTSYSAX 33 28196055bf7SPhil Edworthy #define R9A09G011_GRP_RESETN 34 28296055bf7SPhil Edworthy #define R9A09G011_CIF_RST_N 35 28396055bf7SPhil Edworthy #define R9A09G011_DCU_RSTSYSAX 36 28496055bf7SPhil Edworthy #define R9A09G011_HMI_RST_N 37 28596055bf7SPhil Edworthy #define R9A09G011_HMI_PRESETN 38 28696055bf7SPhil Edworthy #define R9A09G011_LCI_PRESETN 39 28796055bf7SPhil Edworthy #define R9A09G011_LCI_ARESETN 40 28896055bf7SPhil Edworthy 28996055bf7SPhil Edworthy #define R9A09G011_AUI_RSTSYSAX 41 29096055bf7SPhil Edworthy #define R9A09G011_MTR_RSTSYSAX 42 29196055bf7SPhil Edworthy #define R9A09G011_GFT_RSTSYSAX 43 29296055bf7SPhil Edworthy #define R9A09G011_ATGA_RSTSYSAX 44 29396055bf7SPhil Edworthy #define R9A09G011_ATGB_RSTSYSAX 45 29496055bf7SPhil Edworthy #define R9A09G011_SYC_RST_N 46 29596055bf7SPhil Edworthy 29696055bf7SPhil Edworthy #define R9A09G011_TIM_GPA_PRESETN 47 29796055bf7SPhil Edworthy #define R9A09G011_TIM_GPB_PRESETN 48 29896055bf7SPhil Edworthy #define R9A09G011_TIM_GPC_PRESETN 49 29996055bf7SPhil Edworthy #define R9A09G011_TIM_GPD_PRESETN 50 30096055bf7SPhil Edworthy #define R9A09G011_PWM_GPE_PRESETN 51 30196055bf7SPhil Edworthy #define R9A09G011_PWM_GPF_PRESETN 52 30296055bf7SPhil Edworthy #define R9A09G011_CSI_GPG_PRESETN 53 30396055bf7SPhil Edworthy #define R9A09G011_CSI_GPH_PRESETN 54 30496055bf7SPhil Edworthy #define R9A09G011_IIC_GPA_PRESETN 55 30596055bf7SPhil Edworthy #define R9A09G011_IIC_GPB_PRESETN 56 30696055bf7SPhil Edworthy #define R9A09G011_URT_PRESETN 57 30796055bf7SPhil Edworthy #define R9A09G011_WDT0_PRESETN 58 30896055bf7SPhil Edworthy #define R9A09G011_WDT1_PRESETN 59 30996055bf7SPhil Edworthy 31096055bf7SPhil Edworthy #define R9A09G011_ICB_PD_AWO_RST_N 60 31196055bf7SPhil Edworthy #define R9A09G011_ICB_PD_MMC_RST_N 61 31296055bf7SPhil Edworthy #define R9A09G011_ICB_PD_VD0_RST_N 62 31396055bf7SPhil Edworthy #define R9A09G011_ICB_PD_VD1_RST_N 63 31496055bf7SPhil Edworthy #define R9A09G011_ICB_PD_RFX_RST_N 64 31596055bf7SPhil Edworthy 31696055bf7SPhil Edworthy #define R9A09G011_CA53_NCPUPORESET0 65 31796055bf7SPhil Edworthy #define R9A09G011_CA53_NCPUPORESET1 66 31896055bf7SPhil Edworthy #define R9A09G011_CA53_NCORERESET0 67 31996055bf7SPhil Edworthy #define R9A09G011_CA53_NCORERESET1 68 32096055bf7SPhil Edworthy #define R9A09G011_CA53_NPRESETDBG 69 32196055bf7SPhil Edworthy #define R9A09G011_CA53_L2RESET 70 32296055bf7SPhil Edworthy #define R9A09G011_CA53_NMISCRESET_HM 71 32396055bf7SPhil Edworthy #define R9A09G011_CA53_NMISCRESET_SM 72 32496055bf7SPhil Edworthy #define R9A09G011_CA53_NARESET 73 32596055bf7SPhil Edworthy 32696055bf7SPhil Edworthy #define R9A09G011_DRPA_ARESETN 74 32796055bf7SPhil Edworthy 32896055bf7SPhil Edworthy #define R9A09G011_RAMB0_ARESETN 75 32996055bf7SPhil Edworthy #define R9A09G011_RAMB1_ARESETN 76 33096055bf7SPhil Edworthy #define R9A09G011_RAMB2_ARESETN 77 33196055bf7SPhil Edworthy #define R9A09G011_RAMB3_ARESETN 78 33296055bf7SPhil Edworthy 33396055bf7SPhil Edworthy #define R9A09G011_CIMA_RSTSYSAX 79 33496055bf7SPhil Edworthy #define R9A09G011_CIMB_RSTSYSAX 80 33596055bf7SPhil Edworthy #define R9A09G011_FAFA_RSTSYSAX 81 33696055bf7SPhil Edworthy #define R9A09G011_STG_RSTSYSAX 82 33796055bf7SPhil Edworthy 33896055bf7SPhil Edworthy #define R9A09G011_BIMA_RSTSYSAX 83 33996055bf7SPhil Edworthy #define R9A09G011_FAFB_RSTSYSAX 84 34096055bf7SPhil Edworthy #define R9A09G011_FCD_RSTSYSAX 85 34196055bf7SPhil Edworthy #define R9A09G011_RIM_RSTSYSAX 86 34296055bf7SPhil Edworthy #define R9A09G011_VCD_RESETN 87 34396055bf7SPhil Edworthy #define R9A09G011_JPG_XRESET 88 34496055bf7SPhil Edworthy 34596055bf7SPhil Edworthy #define R9A09G011_MMC_CORE_DDRC_RSTN 89 34696055bf7SPhil Edworthy #define R9A09G011_MMC_ARESETN_N 90 34796055bf7SPhil Edworthy #define R9A09G011_MMC_PRESETN 91 34896055bf7SPhil Edworthy #define R9A09G011_DDI_PWROK 92 34996055bf7SPhil Edworthy #define R9A09G011_DDI_RESET 93 35096055bf7SPhil Edworthy #define R9A09G011_DDI_RESETN_APB 94 35196055bf7SPhil Edworthy 35296055bf7SPhil Edworthy #endif /* __DT_BINDINGS_CLOCK_R9A09G011_CPG_H__ */ 353