1680e1c83SChanho Park /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2680e1c83SChanho Park /* 3680e1c83SChanho Park * Copyright (c) 2022 Samsung Electronics Co., Ltd. 4680e1c83SChanho Park * Author: Chanho Park <chanho61.park@samsung.com> 5680e1c83SChanho Park * 6680e1c83SChanho Park * Device Tree binding constants for Exynos Auto V9 clock controller. 7680e1c83SChanho Park */ 8680e1c83SChanho Park 9680e1c83SChanho Park #ifndef _DT_BINDINGS_CLOCK_EXYNOSAUTOV9_H 10680e1c83SChanho Park #define _DT_BINDINGS_CLOCK_EXYNOSAUTOV9_H 11680e1c83SChanho Park 12680e1c83SChanho Park /* CMU_TOP */ 13680e1c83SChanho Park #define FOUT_SHARED0_PLL 1 14680e1c83SChanho Park #define FOUT_SHARED1_PLL 2 15680e1c83SChanho Park #define FOUT_SHARED2_PLL 3 16680e1c83SChanho Park #define FOUT_SHARED3_PLL 4 17680e1c83SChanho Park #define FOUT_SHARED4_PLL 5 18680e1c83SChanho Park 19680e1c83SChanho Park /* MUX in CMU_TOP */ 20680e1c83SChanho Park #define MOUT_SHARED0_PLL 6 21680e1c83SChanho Park #define MOUT_SHARED1_PLL 7 22680e1c83SChanho Park #define MOUT_SHARED2_PLL 8 23680e1c83SChanho Park #define MOUT_SHARED3_PLL 9 24680e1c83SChanho Park #define MOUT_SHARED4_PLL 10 25680e1c83SChanho Park #define MOUT_CLKCMU_CMU_BOOST 11 26680e1c83SChanho Park #define MOUT_CLKCMU_CMU_CMUREF 12 27680e1c83SChanho Park #define MOUT_CLKCMU_ACC_BUS 13 28680e1c83SChanho Park #define MOUT_CLKCMU_APM_BUS 14 29680e1c83SChanho Park #define MOUT_CLKCMU_AUD_CPU 15 30680e1c83SChanho Park #define MOUT_CLKCMU_AUD_BUS 16 31680e1c83SChanho Park #define MOUT_CLKCMU_BUSC_BUS 17 32680e1c83SChanho Park #define MOUT_CLKCMU_BUSMC_BUS 19 33680e1c83SChanho Park #define MOUT_CLKCMU_CORE_BUS 20 34680e1c83SChanho Park #define MOUT_CLKCMU_CPUCL0_SWITCH 21 35680e1c83SChanho Park #define MOUT_CLKCMU_CPUCL0_CLUSTER 22 36680e1c83SChanho Park #define MOUT_CLKCMU_CPUCL1_SWITCH 24 37680e1c83SChanho Park #define MOUT_CLKCMU_CPUCL1_CLUSTER 25 38680e1c83SChanho Park #define MOUT_CLKCMU_DPTX_BUS 26 39680e1c83SChanho Park #define MOUT_CLKCMU_DPTX_DPGTC 27 40680e1c83SChanho Park #define MOUT_CLKCMU_DPUM_BUS 28 41680e1c83SChanho Park #define MOUT_CLKCMU_DPUS0_BUS 29 42680e1c83SChanho Park #define MOUT_CLKCMU_DPUS1_BUS 30 43680e1c83SChanho Park #define MOUT_CLKCMU_FSYS0_BUS 31 44680e1c83SChanho Park #define MOUT_CLKCMU_FSYS0_PCIE 32 45680e1c83SChanho Park #define MOUT_CLKCMU_FSYS1_BUS 33 46680e1c83SChanho Park #define MOUT_CLKCMU_FSYS1_USBDRD 34 47680e1c83SChanho Park #define MOUT_CLKCMU_FSYS1_MMC_CARD 35 48680e1c83SChanho Park #define MOUT_CLKCMU_FSYS2_BUS 36 49680e1c83SChanho Park #define MOUT_CLKCMU_FSYS2_UFS_EMBD 37 50680e1c83SChanho Park #define MOUT_CLKCMU_FSYS2_ETHERNET 38 51680e1c83SChanho Park #define MOUT_CLKCMU_G2D_G2D 39 52680e1c83SChanho Park #define MOUT_CLKCMU_G2D_MSCL 40 53680e1c83SChanho Park #define MOUT_CLKCMU_G3D00_SWITCH 41 54680e1c83SChanho Park #define MOUT_CLKCMU_G3D01_SWITCH 42 55680e1c83SChanho Park #define MOUT_CLKCMU_G3D1_SWITCH 43 56680e1c83SChanho Park #define MOUT_CLKCMU_ISPB_BUS 44 57680e1c83SChanho Park #define MOUT_CLKCMU_MFC_MFC 45 58680e1c83SChanho Park #define MOUT_CLKCMU_MFC_WFD 46 59680e1c83SChanho Park #define MOUT_CLKCMU_MIF_SWITCH 47 60680e1c83SChanho Park #define MOUT_CLKCMU_MIF_BUSP 48 61680e1c83SChanho Park #define MOUT_CLKCMU_NPU_BUS 49 62680e1c83SChanho Park #define MOUT_CLKCMU_PERIC0_BUS 50 63680e1c83SChanho Park #define MOUT_CLKCMU_PERIC0_IP 51 64680e1c83SChanho Park #define MOUT_CLKCMU_PERIC1_BUS 52 65680e1c83SChanho Park #define MOUT_CLKCMU_PERIC1_IP 53 66680e1c83SChanho Park #define MOUT_CLKCMU_PERIS_BUS 54 67680e1c83SChanho Park 68680e1c83SChanho Park /* DIV in CMU_TOP */ 69680e1c83SChanho Park #define DOUT_SHARED0_DIV3 101 70680e1c83SChanho Park #define DOUT_SHARED0_DIV2 102 71680e1c83SChanho Park #define DOUT_SHARED1_DIV3 103 72680e1c83SChanho Park #define DOUT_SHARED1_DIV2 104 73680e1c83SChanho Park #define DOUT_SHARED1_DIV4 105 74680e1c83SChanho Park #define DOUT_SHARED2_DIV3 106 75680e1c83SChanho Park #define DOUT_SHARED2_DIV2 107 76680e1c83SChanho Park #define DOUT_SHARED2_DIV4 108 77680e1c83SChanho Park #define DOUT_SHARED4_DIV2 109 78680e1c83SChanho Park #define DOUT_SHARED4_DIV4 110 79680e1c83SChanho Park #define DOUT_CLKCMU_CMU_BOOST 111 80680e1c83SChanho Park #define DOUT_CLKCMU_ACC_BUS 112 81680e1c83SChanho Park #define DOUT_CLKCMU_APM_BUS 113 82680e1c83SChanho Park #define DOUT_CLKCMU_AUD_CPU 114 83680e1c83SChanho Park #define DOUT_CLKCMU_AUD_BUS 115 84680e1c83SChanho Park #define DOUT_CLKCMU_BUSC_BUS 116 85680e1c83SChanho Park #define DOUT_CLKCMU_BUSMC_BUS 118 86680e1c83SChanho Park #define DOUT_CLKCMU_CORE_BUS 119 87680e1c83SChanho Park #define DOUT_CLKCMU_CPUCL0_SWITCH 120 88680e1c83SChanho Park #define DOUT_CLKCMU_CPUCL0_CLUSTER 121 89680e1c83SChanho Park #define DOUT_CLKCMU_CPUCL1_SWITCH 123 90680e1c83SChanho Park #define DOUT_CLKCMU_CPUCL1_CLUSTER 124 91680e1c83SChanho Park #define DOUT_CLKCMU_DPTX_BUS 125 92680e1c83SChanho Park #define DOUT_CLKCMU_DPTX_DPGTC 126 93680e1c83SChanho Park #define DOUT_CLKCMU_DPUM_BUS 127 94680e1c83SChanho Park #define DOUT_CLKCMU_DPUS0_BUS 128 95680e1c83SChanho Park #define DOUT_CLKCMU_DPUS1_BUS 129 96680e1c83SChanho Park #define DOUT_CLKCMU_FSYS0_BUS 130 97680e1c83SChanho Park #define DOUT_CLKCMU_FSYS0_PCIE 131 98680e1c83SChanho Park #define DOUT_CLKCMU_FSYS1_BUS 132 99680e1c83SChanho Park #define DOUT_CLKCMU_FSYS1_USBDRD 133 100680e1c83SChanho Park #define DOUT_CLKCMU_FSYS2_BUS 134 101680e1c83SChanho Park #define DOUT_CLKCMU_FSYS2_UFS_EMBD 135 102680e1c83SChanho Park #define DOUT_CLKCMU_FSYS2_ETHERNET 136 103680e1c83SChanho Park #define DOUT_CLKCMU_G2D_G2D 137 104680e1c83SChanho Park #define DOUT_CLKCMU_G2D_MSCL 138 105680e1c83SChanho Park #define DOUT_CLKCMU_G3D00_SWITCH 139 106680e1c83SChanho Park #define DOUT_CLKCMU_G3D01_SWITCH 140 107680e1c83SChanho Park #define DOUT_CLKCMU_G3D1_SWITCH 141 108680e1c83SChanho Park #define DOUT_CLKCMU_ISPB_BUS 142 109680e1c83SChanho Park #define DOUT_CLKCMU_MFC_MFC 143 110680e1c83SChanho Park #define DOUT_CLKCMU_MFC_WFD 144 111680e1c83SChanho Park #define DOUT_CLKCMU_MIF_SWITCH 145 112680e1c83SChanho Park #define DOUT_CLKCMU_MIF_BUSP 146 113680e1c83SChanho Park #define DOUT_CLKCMU_NPU_BUS 147 114680e1c83SChanho Park #define DOUT_CLKCMU_PERIC0_BUS 148 115680e1c83SChanho Park #define DOUT_CLKCMU_PERIC0_IP 149 116680e1c83SChanho Park #define DOUT_CLKCMU_PERIC1_BUS 150 117680e1c83SChanho Park #define DOUT_CLKCMU_PERIC1_IP 151 118680e1c83SChanho Park #define DOUT_CLKCMU_PERIS_BUS 152 119680e1c83SChanho Park 120680e1c83SChanho Park /* GAT in CMU_TOP */ 121680e1c83SChanho Park #define GOUT_CLKCMU_CMU_BOOST 201 122680e1c83SChanho Park #define GOUT_CLKCMU_CPUCL0_BOOST 202 123680e1c83SChanho Park #define GOUT_CLKCMU_CPUCL1_BOOST 203 124680e1c83SChanho Park #define GOUT_CLKCMU_CORE_BOOST 204 125680e1c83SChanho Park #define GOUT_CLKCMU_BUSC_BOOST 205 126680e1c83SChanho Park #define GOUT_CLKCMU_BUSMC_BOOST 206 127680e1c83SChanho Park #define GOUT_CLKCMU_MIF_BOOST 207 128680e1c83SChanho Park #define GOUT_CLKCMU_ACC_BUS 208 129680e1c83SChanho Park #define GOUT_CLKCMU_APM_BUS 209 130680e1c83SChanho Park #define GOUT_CLKCMU_AUD_CPU 210 131680e1c83SChanho Park #define GOUT_CLKCMU_AUD_BUS 211 132680e1c83SChanho Park #define GOUT_CLKCMU_BUSC_BUS 212 133680e1c83SChanho Park #define GOUT_CLKCMU_BUSMC_BUS 214 134680e1c83SChanho Park #define GOUT_CLKCMU_CORE_BUS 215 135680e1c83SChanho Park #define GOUT_CLKCMU_CPUCL0_SWITCH 216 136680e1c83SChanho Park #define GOUT_CLKCMU_CPUCL0_CLUSTER 217 137680e1c83SChanho Park #define GOUT_CLKCMU_CPUCL1_SWITCH 219 138680e1c83SChanho Park #define GOUT_CLKCMU_CPUCL1_CLUSTER 220 139680e1c83SChanho Park #define GOUT_CLKCMU_DPTX_BUS 221 140680e1c83SChanho Park #define GOUT_CLKCMU_DPTX_DPGTC 222 141680e1c83SChanho Park #define GOUT_CLKCMU_DPUM_BUS 223 142680e1c83SChanho Park #define GOUT_CLKCMU_DPUS0_BUS 224 143680e1c83SChanho Park #define GOUT_CLKCMU_DPUS1_BUS 225 144680e1c83SChanho Park #define GOUT_CLKCMU_FSYS0_BUS 226 145680e1c83SChanho Park #define GOUT_CLKCMU_FSYS0_PCIE 227 146680e1c83SChanho Park #define GOUT_CLKCMU_FSYS1_BUS 228 147680e1c83SChanho Park #define GOUT_CLKCMU_FSYS1_USBDRD 229 148680e1c83SChanho Park #define GOUT_CLKCMU_FSYS1_MMC_CARD 230 149680e1c83SChanho Park #define GOUT_CLKCMU_FSYS2_BUS 231 150680e1c83SChanho Park #define GOUT_CLKCMU_FSYS2_UFS_EMBD 232 151680e1c83SChanho Park #define GOUT_CLKCMU_FSYS2_ETHERNET 233 152680e1c83SChanho Park #define GOUT_CLKCMU_G2D_G2D 234 153680e1c83SChanho Park #define GOUT_CLKCMU_G2D_MSCL 235 154680e1c83SChanho Park #define GOUT_CLKCMU_G3D00_SWITCH 236 155680e1c83SChanho Park #define GOUT_CLKCMU_G3D01_SWITCH 237 156680e1c83SChanho Park #define GOUT_CLKCMU_G3D1_SWITCH 238 157680e1c83SChanho Park #define GOUT_CLKCMU_ISPB_BUS 239 158680e1c83SChanho Park #define GOUT_CLKCMU_MFC_MFC 240 159680e1c83SChanho Park #define GOUT_CLKCMU_MFC_WFD 241 160680e1c83SChanho Park #define GOUT_CLKCMU_MIF_SWITCH 242 161680e1c83SChanho Park #define GOUT_CLKCMU_MIF_BUSP 243 162680e1c83SChanho Park #define GOUT_CLKCMU_NPU_BUS 244 163680e1c83SChanho Park #define GOUT_CLKCMU_PERIC0_BUS 245 164680e1c83SChanho Park #define GOUT_CLKCMU_PERIC0_IP 246 165680e1c83SChanho Park #define GOUT_CLKCMU_PERIC1_BUS 247 166680e1c83SChanho Park #define GOUT_CLKCMU_PERIC1_IP 248 167680e1c83SChanho Park #define GOUT_CLKCMU_PERIS_BUS 249 168680e1c83SChanho Park 169680e1c83SChanho Park /* CMU_BUSMC */ 170680e1c83SChanho Park #define CLK_MOUT_BUSMC_BUS_USER 1 171680e1c83SChanho Park #define CLK_DOUT_BUSMC_BUSP 2 172680e1c83SChanho Park #define CLK_GOUT_BUSMC_PDMA0_PCLK 3 173680e1c83SChanho Park #define CLK_GOUT_BUSMC_SPDMA_PCLK 4 174680e1c83SChanho Park 175680e1c83SChanho Park /* CMU_CORE */ 176680e1c83SChanho Park #define CLK_MOUT_CORE_BUS_USER 1 177680e1c83SChanho Park #define CLK_DOUT_CORE_BUSP 2 178680e1c83SChanho Park #define CLK_GOUT_CORE_CCI_CLK 3 179680e1c83SChanho Park #define CLK_GOUT_CORE_CCI_PCLK 4 180680e1c83SChanho Park #define CLK_GOUT_CORE_CMU_CORE_PCLK 5 181680e1c83SChanho Park 182153da489SChanho Park /* CMU_FSYS0 */ 183153da489SChanho Park #define CLK_MOUT_FSYS0_BUS_USER 1 184153da489SChanho Park #define CLK_MOUT_FSYS0_PCIE_USER 2 185153da489SChanho Park #define CLK_GOUT_FSYS0_BUS_PCLK 3 186153da489SChanho Park 187153da489SChanho Park #define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_REFCLK 4 188153da489SChanho Park #define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_REFCLK 5 189153da489SChanho Park #define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_DBI_ACLK 6 190153da489SChanho Park #define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_MSTR_ACLK 7 191153da489SChanho Park #define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_SLV_ACLK 8 192153da489SChanho Park #define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_DBI_ACLK 9 193153da489SChanho Park #define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_MSTR_ACLK 10 194153da489SChanho Park #define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_SLV_ACLK 11 195153da489SChanho Park #define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_PIPE_CLK 12 196153da489SChanho Park #define CLK_GOUT_FSYS0_PCIE_GEN3A_2L0_CLK 13 197153da489SChanho Park #define CLK_GOUT_FSYS0_PCIE_GEN3B_2L0_CLK 14 198153da489SChanho Park 199153da489SChanho Park #define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_REFCLK 15 200153da489SChanho Park #define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_REFCLK 16 201153da489SChanho Park #define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_DBI_ACLK 17 202153da489SChanho Park #define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_MSTR_ACLK 18 203153da489SChanho Park #define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_SLV_ACLK 19 204153da489SChanho Park #define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_DBI_ACLK 20 205153da489SChanho Park #define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_MSTR_ACLK 21 206153da489SChanho Park #define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_SLV_ACLK 22 207153da489SChanho Park #define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_PIPE_CLK 23 208153da489SChanho Park #define CLK_GOUT_FSYS0_PCIE_GEN3A_2L1_CLK 24 209153da489SChanho Park #define CLK_GOUT_FSYS0_PCIE_GEN3B_2L1_CLK 25 210153da489SChanho Park 211153da489SChanho Park #define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_REFCLK 26 212153da489SChanho Park #define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_REFCLK 27 213153da489SChanho Park #define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_DBI_ACLK 28 214153da489SChanho Park #define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_MSTR_ACLK 29 215153da489SChanho Park #define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_SLV_ACLK 30 216153da489SChanho Park #define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_DBI_ACLK 31 217153da489SChanho Park #define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_MSTR_ACLK 32 218153da489SChanho Park #define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_SLV_ACLK 33 219153da489SChanho Park #define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_PIPE_CLK 34 220153da489SChanho Park #define CLK_GOUT_FSYS0_PCIE_GEN3A_4L_CLK 35 221153da489SChanho Park #define CLK_GOUT_FSYS0_PCIE_GEN3B_4L_CLK 36 222153da489SChanho Park 223*3c073243SChanho Park /* CMU_FSYS1 */ 224*3c073243SChanho Park #define FOUT_MMC_PLL 1 225*3c073243SChanho Park 226*3c073243SChanho Park #define CLK_MOUT_FSYS1_BUS_USER 2 227*3c073243SChanho Park #define CLK_MOUT_FSYS1_MMC_PLL 3 228*3c073243SChanho Park #define CLK_MOUT_FSYS1_MMC_CARD_USER 4 229*3c073243SChanho Park #define CLK_MOUT_FSYS1_USBDRD_USER 5 230*3c073243SChanho Park #define CLK_MOUT_FSYS1_MMC_CARD 6 231*3c073243SChanho Park 232*3c073243SChanho Park #define CLK_DOUT_FSYS1_MMC_CARD 7 233*3c073243SChanho Park 234*3c073243SChanho Park #define CLK_GOUT_FSYS1_PCLK 8 235*3c073243SChanho Park #define CLK_GOUT_FSYS1_MMC_CARD_SDCLKIN 9 236*3c073243SChanho Park #define CLK_GOUT_FSYS1_MMC_CARD_ACLK 10 237*3c073243SChanho Park #define CLK_GOUT_FSYS1_USB20DRD_0_REFCLK 11 238*3c073243SChanho Park #define CLK_GOUT_FSYS1_USB20DRD_1_REFCLK 12 239*3c073243SChanho Park #define CLK_GOUT_FSYS1_USB30DRD_0_REFCLK 13 240*3c073243SChanho Park #define CLK_GOUT_FSYS1_USB30DRD_1_REFCLK 14 241*3c073243SChanho Park #define CLK_GOUT_FSYS1_USB20_0_ACLK 15 242*3c073243SChanho Park #define CLK_GOUT_FSYS1_USB20_1_ACLK 16 243*3c073243SChanho Park #define CLK_GOUT_FSYS1_USB30_0_ACLK 17 244*3c073243SChanho Park #define CLK_GOUT_FSYS1_USB30_1_ACLK 18 245*3c073243SChanho Park 246680e1c83SChanho Park /* CMU_FSYS2 */ 247680e1c83SChanho Park #define CLK_MOUT_FSYS2_BUS_USER 1 248680e1c83SChanho Park #define CLK_MOUT_FSYS2_UFS_EMBD_USER 2 249680e1c83SChanho Park #define CLK_MOUT_FSYS2_ETHERNET_USER 3 250680e1c83SChanho Park #define CLK_GOUT_FSYS2_UFS_EMBD0_ACLK 4 251680e1c83SChanho Park #define CLK_GOUT_FSYS2_UFS_EMBD0_UNIPRO 5 252680e1c83SChanho Park #define CLK_GOUT_FSYS2_UFS_EMBD1_ACLK 6 253680e1c83SChanho Park #define CLK_GOUT_FSYS2_UFS_EMBD1_UNIPRO 7 254680e1c83SChanho Park 255680e1c83SChanho Park /* CMU_PERIC0 */ 256680e1c83SChanho Park #define CLK_MOUT_PERIC0_BUS_USER 1 257680e1c83SChanho Park #define CLK_MOUT_PERIC0_IP_USER 2 258680e1c83SChanho Park #define CLK_MOUT_PERIC0_USI00_USI 3 259680e1c83SChanho Park #define CLK_MOUT_PERIC0_USI01_USI 4 260680e1c83SChanho Park #define CLK_MOUT_PERIC0_USI02_USI 5 261680e1c83SChanho Park #define CLK_MOUT_PERIC0_USI03_USI 6 262680e1c83SChanho Park #define CLK_MOUT_PERIC0_USI04_USI 7 263680e1c83SChanho Park #define CLK_MOUT_PERIC0_USI05_USI 8 264680e1c83SChanho Park #define CLK_MOUT_PERIC0_USI_I2C 9 265680e1c83SChanho Park 266680e1c83SChanho Park #define CLK_DOUT_PERIC0_USI00_USI 10 267680e1c83SChanho Park #define CLK_DOUT_PERIC0_USI01_USI 11 268680e1c83SChanho Park #define CLK_DOUT_PERIC0_USI02_USI 12 269680e1c83SChanho Park #define CLK_DOUT_PERIC0_USI03_USI 13 270680e1c83SChanho Park #define CLK_DOUT_PERIC0_USI04_USI 14 271680e1c83SChanho Park #define CLK_DOUT_PERIC0_USI05_USI 15 272680e1c83SChanho Park #define CLK_DOUT_PERIC0_USI_I2C 16 273680e1c83SChanho Park 274680e1c83SChanho Park #define CLK_GOUT_PERIC0_IPCLK_0 20 275680e1c83SChanho Park #define CLK_GOUT_PERIC0_IPCLK_1 21 276680e1c83SChanho Park #define CLK_GOUT_PERIC0_IPCLK_2 22 277680e1c83SChanho Park #define CLK_GOUT_PERIC0_IPCLK_3 23 278680e1c83SChanho Park #define CLK_GOUT_PERIC0_IPCLK_4 24 279680e1c83SChanho Park #define CLK_GOUT_PERIC0_IPCLK_5 25 280680e1c83SChanho Park #define CLK_GOUT_PERIC0_IPCLK_6 26 281680e1c83SChanho Park #define CLK_GOUT_PERIC0_IPCLK_7 27 282680e1c83SChanho Park #define CLK_GOUT_PERIC0_IPCLK_8 28 283680e1c83SChanho Park #define CLK_GOUT_PERIC0_IPCLK_9 29 284680e1c83SChanho Park #define CLK_GOUT_PERIC0_IPCLK_10 30 285b6740089SChanho Park #define CLK_GOUT_PERIC0_IPCLK_11 31 286b6740089SChanho Park #define CLK_GOUT_PERIC0_PCLK_0 32 287b6740089SChanho Park #define CLK_GOUT_PERIC0_PCLK_1 33 288b6740089SChanho Park #define CLK_GOUT_PERIC0_PCLK_2 34 289b6740089SChanho Park #define CLK_GOUT_PERIC0_PCLK_3 35 290b6740089SChanho Park #define CLK_GOUT_PERIC0_PCLK_4 36 291b6740089SChanho Park #define CLK_GOUT_PERIC0_PCLK_5 37 292b6740089SChanho Park #define CLK_GOUT_PERIC0_PCLK_6 38 293b6740089SChanho Park #define CLK_GOUT_PERIC0_PCLK_7 39 294b6740089SChanho Park #define CLK_GOUT_PERIC0_PCLK_8 40 295b6740089SChanho Park #define CLK_GOUT_PERIC0_PCLK_9 41 296b6740089SChanho Park #define CLK_GOUT_PERIC0_PCLK_10 42 297b6740089SChanho Park #define CLK_GOUT_PERIC0_PCLK_11 43 298680e1c83SChanho Park 299680e1c83SChanho Park /* CMU_PERIC1 */ 300680e1c83SChanho Park #define CLK_MOUT_PERIC1_BUS_USER 1 301680e1c83SChanho Park #define CLK_MOUT_PERIC1_IP_USER 2 302680e1c83SChanho Park #define CLK_MOUT_PERIC1_USI06_USI 3 303680e1c83SChanho Park #define CLK_MOUT_PERIC1_USI07_USI 4 304680e1c83SChanho Park #define CLK_MOUT_PERIC1_USI08_USI 5 305680e1c83SChanho Park #define CLK_MOUT_PERIC1_USI09_USI 6 306680e1c83SChanho Park #define CLK_MOUT_PERIC1_USI10_USI 7 307680e1c83SChanho Park #define CLK_MOUT_PERIC1_USI11_USI 8 308680e1c83SChanho Park #define CLK_MOUT_PERIC1_USI_I2C 9 309680e1c83SChanho Park 310680e1c83SChanho Park #define CLK_DOUT_PERIC1_USI06_USI 10 311680e1c83SChanho Park #define CLK_DOUT_PERIC1_USI07_USI 11 312680e1c83SChanho Park #define CLK_DOUT_PERIC1_USI08_USI 12 313680e1c83SChanho Park #define CLK_DOUT_PERIC1_USI09_USI 13 314680e1c83SChanho Park #define CLK_DOUT_PERIC1_USI10_USI 14 315680e1c83SChanho Park #define CLK_DOUT_PERIC1_USI11_USI 15 316680e1c83SChanho Park #define CLK_DOUT_PERIC1_USI_I2C 16 317680e1c83SChanho Park 318680e1c83SChanho Park #define CLK_GOUT_PERIC1_IPCLK_0 20 319680e1c83SChanho Park #define CLK_GOUT_PERIC1_IPCLK_1 21 320680e1c83SChanho Park #define CLK_GOUT_PERIC1_IPCLK_2 22 321680e1c83SChanho Park #define CLK_GOUT_PERIC1_IPCLK_3 23 322680e1c83SChanho Park #define CLK_GOUT_PERIC1_IPCLK_4 24 323680e1c83SChanho Park #define CLK_GOUT_PERIC1_IPCLK_5 25 324680e1c83SChanho Park #define CLK_GOUT_PERIC1_IPCLK_6 26 325680e1c83SChanho Park #define CLK_GOUT_PERIC1_IPCLK_7 27 326680e1c83SChanho Park #define CLK_GOUT_PERIC1_IPCLK_8 28 327680e1c83SChanho Park #define CLK_GOUT_PERIC1_IPCLK_9 29 328680e1c83SChanho Park #define CLK_GOUT_PERIC1_IPCLK_10 30 329b6740089SChanho Park #define CLK_GOUT_PERIC1_IPCLK_11 31 330b6740089SChanho Park #define CLK_GOUT_PERIC1_PCLK_0 32 331b6740089SChanho Park #define CLK_GOUT_PERIC1_PCLK_1 33 332b6740089SChanho Park #define CLK_GOUT_PERIC1_PCLK_2 34 333b6740089SChanho Park #define CLK_GOUT_PERIC1_PCLK_3 35 334b6740089SChanho Park #define CLK_GOUT_PERIC1_PCLK_4 36 335b6740089SChanho Park #define CLK_GOUT_PERIC1_PCLK_5 37 336b6740089SChanho Park #define CLK_GOUT_PERIC1_PCLK_6 38 337b6740089SChanho Park #define CLK_GOUT_PERIC1_PCLK_7 39 338b6740089SChanho Park #define CLK_GOUT_PERIC1_PCLK_8 40 339b6740089SChanho Park #define CLK_GOUT_PERIC1_PCLK_9 41 340b6740089SChanho Park #define CLK_GOUT_PERIC1_PCLK_10 42 341b6740089SChanho Park #define CLK_GOUT_PERIC1_PCLK_11 43 342680e1c83SChanho Park 343680e1c83SChanho Park /* CMU_PERIS */ 344680e1c83SChanho Park #define CLK_MOUT_PERIS_BUS_USER 1 345680e1c83SChanho Park #define CLK_GOUT_SYSREG_PERIS_PCLK 2 346680e1c83SChanho Park #define CLK_GOUT_WDT_CLUSTER0 3 347680e1c83SChanho Park #define CLK_GOUT_WDT_CLUSTER1 4 348680e1c83SChanho Park 349680e1c83SChanho Park #endif /* _DT_BINDINGS_CLOCK_EXYNOSAUTOV9_H */ 350