1*8c18feceSCixi Geng /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2*8c18feceSCixi Geng /* 3*8c18feceSCixi Geng * Unisoc UMS512 SoC DTS file 4*8c18feceSCixi Geng * 5*8c18feceSCixi Geng * Copyright (C) 2022, Unisoc Inc. 6*8c18feceSCixi Geng */ 7*8c18feceSCixi Geng 8*8c18feceSCixi Geng #ifndef _DT_BINDINGS_CLK_UMS512_H_ 9*8c18feceSCixi Geng #define _DT_BINDINGS_CLK_UMS512_H_ 10*8c18feceSCixi Geng 11*8c18feceSCixi Geng #define CLK_26M_AUD 0 12*8c18feceSCixi Geng #define CLK_13M 1 13*8c18feceSCixi Geng #define CLK_6M5 2 14*8c18feceSCixi Geng #define CLK_4M3 3 15*8c18feceSCixi Geng #define CLK_2M 4 16*8c18feceSCixi Geng #define CLK_1M 5 17*8c18feceSCixi Geng #define CLK_250K 6 18*8c18feceSCixi Geng #define CLK_RCO_25M 7 19*8c18feceSCixi Geng #define CLK_RCO_4M 8 20*8c18feceSCixi Geng #define CLK_RCO_2M 9 21*8c18feceSCixi Geng #define CLK_ISPPLL_GATE 10 22*8c18feceSCixi Geng #define CLK_DPLL0_GATE 11 23*8c18feceSCixi Geng #define CLK_DPLL1_GATE 12 24*8c18feceSCixi Geng #define CLK_LPLL_GATE 13 25*8c18feceSCixi Geng #define CLK_TWPLL_GATE 14 26*8c18feceSCixi Geng #define CLK_GPLL_GATE 15 27*8c18feceSCixi Geng #define CLK_RPLL_GATE 16 28*8c18feceSCixi Geng #define CLK_CPPLL_GATE 17 29*8c18feceSCixi Geng #define CLK_MPLL0_GATE 18 30*8c18feceSCixi Geng #define CLK_MPLL1_GATE 19 31*8c18feceSCixi Geng #define CLK_MPLL2_GATE 20 32*8c18feceSCixi Geng #define CLK_PMU_GATE_NUM (CLK_MPLL2_GATE + 1) 33*8c18feceSCixi Geng 34*8c18feceSCixi Geng #define CLK_DPLL0 0 35*8c18feceSCixi Geng #define CLK_DPLL0_58M31 1 36*8c18feceSCixi Geng #define CLK_ANLG_PHY_G0_NUM (CLK_DPLL0_58M31 + 1) 37*8c18feceSCixi Geng 38*8c18feceSCixi Geng #define CLK_MPLL1 0 39*8c18feceSCixi Geng #define CLK_MPLL1_63M38 1 40*8c18feceSCixi Geng #define CLK_ANLG_PHY_G2_NUM (CLK_MPLL1_63M38 + 1) 41*8c18feceSCixi Geng 42*8c18feceSCixi Geng #define CLK_RPLL 0 43*8c18feceSCixi Geng #define CLK_AUDIO_GATE 1 44*8c18feceSCixi Geng #define CLK_MPLL0 2 45*8c18feceSCixi Geng #define CLK_MPLL0_56M88 3 46*8c18feceSCixi Geng #define CLK_MPLL2 4 47*8c18feceSCixi Geng #define CLK_MPLL2_47M13 5 48*8c18feceSCixi Geng #define CLK_ANLG_PHY_G3_NUM (CLK_MPLL2_47M13 + 1) 49*8c18feceSCixi Geng 50*8c18feceSCixi Geng #define CLK_TWPLL 0 51*8c18feceSCixi Geng #define CLK_TWPLL_768M 1 52*8c18feceSCixi Geng #define CLK_TWPLL_384M 2 53*8c18feceSCixi Geng #define CLK_TWPLL_192M 3 54*8c18feceSCixi Geng #define CLK_TWPLL_96M 4 55*8c18feceSCixi Geng #define CLK_TWPLL_48M 5 56*8c18feceSCixi Geng #define CLK_TWPLL_24M 6 57*8c18feceSCixi Geng #define CLK_TWPLL_12M 7 58*8c18feceSCixi Geng #define CLK_TWPLL_512M 8 59*8c18feceSCixi Geng #define CLK_TWPLL_256M 9 60*8c18feceSCixi Geng #define CLK_TWPLL_128M 10 61*8c18feceSCixi Geng #define CLK_TWPLL_64M 11 62*8c18feceSCixi Geng #define CLK_TWPLL_307M2 12 63*8c18feceSCixi Geng #define CLK_TWPLL_219M4 13 64*8c18feceSCixi Geng #define CLK_TWPLL_170M6 14 65*8c18feceSCixi Geng #define CLK_TWPLL_153M6 15 66*8c18feceSCixi Geng #define CLK_TWPLL_76M8 16 67*8c18feceSCixi Geng #define CLK_TWPLL_51M2 17 68*8c18feceSCixi Geng #define CLK_TWPLL_38M4 18 69*8c18feceSCixi Geng #define CLK_TWPLL_19M2 19 70*8c18feceSCixi Geng #define CLK_TWPLL_12M29 20 71*8c18feceSCixi Geng #define CLK_LPLL 21 72*8c18feceSCixi Geng #define CLK_LPLL_614M4 22 73*8c18feceSCixi Geng #define CLK_LPLL_409M6 23 74*8c18feceSCixi Geng #define CLK_LPLL_245M76 24 75*8c18feceSCixi Geng #define CLK_LPLL_30M72 25 76*8c18feceSCixi Geng #define CLK_ISPPLL 26 77*8c18feceSCixi Geng #define CLK_ISPPLL_468M 27 78*8c18feceSCixi Geng #define CLK_ISPPLL_78M 28 79*8c18feceSCixi Geng #define CLK_GPLL 29 80*8c18feceSCixi Geng #define CLK_GPLL_40M 30 81*8c18feceSCixi Geng #define CLK_CPPLL 31 82*8c18feceSCixi Geng #define CLK_CPPLL_39M32 32 83*8c18feceSCixi Geng #define CLK_ANLG_PHY_GC_NUM (CLK_CPPLL_39M32 + 1) 84*8c18feceSCixi Geng 85*8c18feceSCixi Geng #define CLK_AP_APB 0 86*8c18feceSCixi Geng #define CLK_IPI 1 87*8c18feceSCixi Geng #define CLK_AP_UART0 2 88*8c18feceSCixi Geng #define CLK_AP_UART1 3 89*8c18feceSCixi Geng #define CLK_AP_UART2 4 90*8c18feceSCixi Geng #define CLK_AP_I2C0 5 91*8c18feceSCixi Geng #define CLK_AP_I2C1 6 92*8c18feceSCixi Geng #define CLK_AP_I2C2 7 93*8c18feceSCixi Geng #define CLK_AP_I2C3 8 94*8c18feceSCixi Geng #define CLK_AP_I2C4 9 95*8c18feceSCixi Geng #define CLK_AP_SPI0 10 96*8c18feceSCixi Geng #define CLK_AP_SPI1 11 97*8c18feceSCixi Geng #define CLK_AP_SPI2 12 98*8c18feceSCixi Geng #define CLK_AP_SPI3 13 99*8c18feceSCixi Geng #define CLK_AP_IIS0 14 100*8c18feceSCixi Geng #define CLK_AP_IIS1 15 101*8c18feceSCixi Geng #define CLK_AP_IIS2 16 102*8c18feceSCixi Geng #define CLK_AP_SIM 17 103*8c18feceSCixi Geng #define CLK_AP_CE 18 104*8c18feceSCixi Geng #define CLK_SDIO0_2X 19 105*8c18feceSCixi Geng #define CLK_SDIO1_2X 20 106*8c18feceSCixi Geng #define CLK_EMMC_2X 21 107*8c18feceSCixi Geng #define CLK_VSP 22 108*8c18feceSCixi Geng #define CLK_DISPC0 23 109*8c18feceSCixi Geng #define CLK_DISPC0_DPI 24 110*8c18feceSCixi Geng #define CLK_DSI_APB 25 111*8c18feceSCixi Geng #define CLK_DSI_RXESC 26 112*8c18feceSCixi Geng #define CLK_DSI_LANEBYTE 27 113*8c18feceSCixi Geng #define CLK_VDSP 28 114*8c18feceSCixi Geng #define CLK_VDSP_M 29 115*8c18feceSCixi Geng #define CLK_AP_CLK_NUM (CLK_VDSP_M + 1) 116*8c18feceSCixi Geng 117*8c18feceSCixi Geng #define CLK_DSI_EB 0 118*8c18feceSCixi Geng #define CLK_DISPC_EB 1 119*8c18feceSCixi Geng #define CLK_VSP_EB 2 120*8c18feceSCixi Geng #define CLK_VDMA_EB 3 121*8c18feceSCixi Geng #define CLK_DMA_PUB_EB 4 122*8c18feceSCixi Geng #define CLK_DMA_SEC_EB 5 123*8c18feceSCixi Geng #define CLK_IPI_EB 6 124*8c18feceSCixi Geng #define CLK_AHB_CKG_EB 7 125*8c18feceSCixi Geng #define CLK_BM_CLK_EB 8 126*8c18feceSCixi Geng #define CLK_AP_AHB_GATE_NUM (CLK_BM_CLK_EB + 1) 127*8c18feceSCixi Geng 128*8c18feceSCixi Geng #define CLK_AON_APB 0 129*8c18feceSCixi Geng #define CLK_ADI 1 130*8c18feceSCixi Geng #define CLK_AUX0 2 131*8c18feceSCixi Geng #define CLK_AUX1 3 132*8c18feceSCixi Geng #define CLK_AUX2 4 133*8c18feceSCixi Geng #define CLK_PROBE 5 134*8c18feceSCixi Geng #define CLK_PWM0 6 135*8c18feceSCixi Geng #define CLK_PWM1 7 136*8c18feceSCixi Geng #define CLK_PWM2 8 137*8c18feceSCixi Geng #define CLK_PWM3 9 138*8c18feceSCixi Geng #define CLK_EFUSE 10 139*8c18feceSCixi Geng #define CLK_UART0 11 140*8c18feceSCixi Geng #define CLK_UART1 12 141*8c18feceSCixi Geng #define CLK_THM0 13 142*8c18feceSCixi Geng #define CLK_THM1 14 143*8c18feceSCixi Geng #define CLK_THM2 15 144*8c18feceSCixi Geng #define CLK_THM3 16 145*8c18feceSCixi Geng #define CLK_AON_I2C 17 146*8c18feceSCixi Geng #define CLK_AON_IIS 18 147*8c18feceSCixi Geng #define CLK_SCC 19 148*8c18feceSCixi Geng #define CLK_APCPU_DAP 20 149*8c18feceSCixi Geng #define CLK_APCPU_DAP_MTCK 21 150*8c18feceSCixi Geng #define CLK_APCPU_TS 22 151*8c18feceSCixi Geng #define CLK_DEBUG_TS 23 152*8c18feceSCixi Geng #define CLK_DSI_TEST_S 24 153*8c18feceSCixi Geng #define CLK_DJTAG_TCK 25 154*8c18feceSCixi Geng #define CLK_DJTAG_TCK_HW 26 155*8c18feceSCixi Geng #define CLK_AON_TMR 27 156*8c18feceSCixi Geng #define CLK_AON_PMU 28 157*8c18feceSCixi Geng #define CLK_DEBOUNCE 29 158*8c18feceSCixi Geng #define CLK_APCPU_PMU 30 159*8c18feceSCixi Geng #define CLK_TOP_DVFS 31 160*8c18feceSCixi Geng #define CLK_OTG_UTMI 32 161*8c18feceSCixi Geng #define CLK_OTG_REF 33 162*8c18feceSCixi Geng #define CLK_CSSYS 34 163*8c18feceSCixi Geng #define CLK_CSSYS_PUB 35 164*8c18feceSCixi Geng #define CLK_CSSYS_APB 36 165*8c18feceSCixi Geng #define CLK_AP_AXI 37 166*8c18feceSCixi Geng #define CLK_AP_MM 38 167*8c18feceSCixi Geng #define CLK_SDIO2_2X 39 168*8c18feceSCixi Geng #define CLK_ANALOG_IO_APB 40 169*8c18feceSCixi Geng #define CLK_DMC_REF_CLK 41 170*8c18feceSCixi Geng #define CLK_EMC 42 171*8c18feceSCixi Geng #define CLK_USB 43 172*8c18feceSCixi Geng #define CLK_26M_PMU 44 173*8c18feceSCixi Geng #define CLK_AON_APB_NUM (CLK_26M_PMU + 1) 174*8c18feceSCixi Geng 175*8c18feceSCixi Geng #define CLK_MM_AHB 0 176*8c18feceSCixi Geng #define CLK_MM_MTX 1 177*8c18feceSCixi Geng #define CLK_SENSOR0 2 178*8c18feceSCixi Geng #define CLK_SENSOR1 3 179*8c18feceSCixi Geng #define CLK_SENSOR2 4 180*8c18feceSCixi Geng #define CLK_CPP 5 181*8c18feceSCixi Geng #define CLK_JPG 6 182*8c18feceSCixi Geng #define CLK_FD 7 183*8c18feceSCixi Geng #define CLK_DCAM_IF 8 184*8c18feceSCixi Geng #define CLK_DCAM_AXI 9 185*8c18feceSCixi Geng #define CLK_ISP 10 186*8c18feceSCixi Geng #define CLK_MIPI_CSI0 11 187*8c18feceSCixi Geng #define CLK_MIPI_CSI1 12 188*8c18feceSCixi Geng #define CLK_MIPI_CSI2 13 189*8c18feceSCixi Geng #define CLK_MM_CLK_NUM (CLK_MIPI_CSI2 + 1) 190*8c18feceSCixi Geng 191*8c18feceSCixi Geng #define CLK_RC100M_CAL_EB 0 192*8c18feceSCixi Geng #define CLK_DJTAG_TCK_EB 1 193*8c18feceSCixi Geng #define CLK_DJTAG_EB 2 194*8c18feceSCixi Geng #define CLK_AUX0_EB 3 195*8c18feceSCixi Geng #define CLK_AUX1_EB 4 196*8c18feceSCixi Geng #define CLK_AUX2_EB 5 197*8c18feceSCixi Geng #define CLK_PROBE_EB 6 198*8c18feceSCixi Geng #define CLK_MM_EB 7 199*8c18feceSCixi Geng #define CLK_GPU_EB 8 200*8c18feceSCixi Geng #define CLK_MSPI_EB 9 201*8c18feceSCixi Geng #define CLK_APCPU_DAP_EB 10 202*8c18feceSCixi Geng #define CLK_AON_CSSYS_EB 11 203*8c18feceSCixi Geng #define CLK_CSSYS_APB_EB 12 204*8c18feceSCixi Geng #define CLK_CSSYS_PUB_EB 13 205*8c18feceSCixi Geng #define CLK_SDPHY_CFG_EB 14 206*8c18feceSCixi Geng #define CLK_SDPHY_REF_EB 15 207*8c18feceSCixi Geng #define CLK_EFUSE_EB 16 208*8c18feceSCixi Geng #define CLK_GPIO_EB 17 209*8c18feceSCixi Geng #define CLK_MBOX_EB 18 210*8c18feceSCixi Geng #define CLK_KPD_EB 19 211*8c18feceSCixi Geng #define CLK_AON_SYST_EB 20 212*8c18feceSCixi Geng #define CLK_AP_SYST_EB 21 213*8c18feceSCixi Geng #define CLK_AON_TMR_EB 22 214*8c18feceSCixi Geng #define CLK_OTG_UTMI_EB 23 215*8c18feceSCixi Geng #define CLK_OTG_PHY_EB 24 216*8c18feceSCixi Geng #define CLK_SPLK_EB 25 217*8c18feceSCixi Geng #define CLK_PIN_EB 26 218*8c18feceSCixi Geng #define CLK_ANA_EB 27 219*8c18feceSCixi Geng #define CLK_APCPU_TS0_EB 28 220*8c18feceSCixi Geng #define CLK_APB_BUSMON_EB 29 221*8c18feceSCixi Geng #define CLK_AON_IIS_EB 30 222*8c18feceSCixi Geng #define CLK_SCC_EB 31 223*8c18feceSCixi Geng #define CLK_THM0_EB 32 224*8c18feceSCixi Geng #define CLK_THM1_EB 33 225*8c18feceSCixi Geng #define CLK_THM2_EB 34 226*8c18feceSCixi Geng #define CLK_ASIM_TOP_EB 35 227*8c18feceSCixi Geng #define CLK_I2C_EB 36 228*8c18feceSCixi Geng #define CLK_PMU_EB 37 229*8c18feceSCixi Geng #define CLK_ADI_EB 38 230*8c18feceSCixi Geng #define CLK_EIC_EB 39 231*8c18feceSCixi Geng #define CLK_AP_INTC0_EB 40 232*8c18feceSCixi Geng #define CLK_AP_INTC1_EB 41 233*8c18feceSCixi Geng #define CLK_AP_INTC2_EB 42 234*8c18feceSCixi Geng #define CLK_AP_INTC3_EB 43 235*8c18feceSCixi Geng #define CLK_AP_INTC4_EB 44 236*8c18feceSCixi Geng #define CLK_AP_INTC5_EB 45 237*8c18feceSCixi Geng #define CLK_AUDCP_INTC_EB 46 238*8c18feceSCixi Geng #define CLK_AP_TMR0_EB 47 239*8c18feceSCixi Geng #define CLK_AP_TMR1_EB 48 240*8c18feceSCixi Geng #define CLK_AP_TMR2_EB 49 241*8c18feceSCixi Geng #define CLK_PWM0_EB 50 242*8c18feceSCixi Geng #define CLK_PWM1_EB 51 243*8c18feceSCixi Geng #define CLK_PWM2_EB 52 244*8c18feceSCixi Geng #define CLK_PWM3_EB 53 245*8c18feceSCixi Geng #define CLK_AP_WDG_EB 54 246*8c18feceSCixi Geng #define CLK_APCPU_WDG_EB 55 247*8c18feceSCixi Geng #define CLK_SERDES_EB 56 248*8c18feceSCixi Geng #define CLK_ARCH_RTC_EB 57 249*8c18feceSCixi Geng #define CLK_KPD_RTC_EB 58 250*8c18feceSCixi Geng #define CLK_AON_SYST_RTC_EB 59 251*8c18feceSCixi Geng #define CLK_AP_SYST_RTC_EB 60 252*8c18feceSCixi Geng #define CLK_AON_TMR_RTC_EB 61 253*8c18feceSCixi Geng #define CLK_EIC_RTC_EB 62 254*8c18feceSCixi Geng #define CLK_EIC_RTCDV5_EB 63 255*8c18feceSCixi Geng #define CLK_AP_WDG_RTC_EB 64 256*8c18feceSCixi Geng #define CLK_AC_WDG_RTC_EB 65 257*8c18feceSCixi Geng #define CLK_AP_TMR0_RTC_EB 66 258*8c18feceSCixi Geng #define CLK_AP_TMR1_RTC_EB 67 259*8c18feceSCixi Geng #define CLK_AP_TMR2_RTC_EB 68 260*8c18feceSCixi Geng #define CLK_DCXO_LC_RTC_EB 69 261*8c18feceSCixi Geng #define CLK_BB_CAL_RTC_EB 70 262*8c18feceSCixi Geng #define CLK_AP_EMMC_RTC_EB 71 263*8c18feceSCixi Geng #define CLK_AP_SDIO0_RTC_EB 72 264*8c18feceSCixi Geng #define CLK_AP_SDIO1_RTC_EB 73 265*8c18feceSCixi Geng #define CLK_AP_SDIO2_RTC_EB 74 266*8c18feceSCixi Geng #define CLK_DSI_CSI_TEST_EB 75 267*8c18feceSCixi Geng #define CLK_DJTAG_TCK_EN 76 268*8c18feceSCixi Geng #define CLK_DPHY_REF_EB 77 269*8c18feceSCixi Geng #define CLK_DMC_REF_EB 78 270*8c18feceSCixi Geng #define CLK_OTG_REF_EB 79 271*8c18feceSCixi Geng #define CLK_TSEN_EB 80 272*8c18feceSCixi Geng #define CLK_TMR_EB 81 273*8c18feceSCixi Geng #define CLK_RC100M_REF_EB 82 274*8c18feceSCixi Geng #define CLK_RC100M_FDK_EB 83 275*8c18feceSCixi Geng #define CLK_DEBOUNCE_EB 84 276*8c18feceSCixi Geng #define CLK_DET_32K_EB 85 277*8c18feceSCixi Geng #define CLK_TOP_CSSYS_EB 86 278*8c18feceSCixi Geng #define CLK_AP_AXI_EN 87 279*8c18feceSCixi Geng #define CLK_SDIO0_2X_EN 88 280*8c18feceSCixi Geng #define CLK_SDIO0_1X_EN 89 281*8c18feceSCixi Geng #define CLK_SDIO1_2X_EN 90 282*8c18feceSCixi Geng #define CLK_SDIO1_1X_EN 91 283*8c18feceSCixi Geng #define CLK_SDIO2_2X_EN 92 284*8c18feceSCixi Geng #define CLK_SDIO2_1X_EN 93 285*8c18feceSCixi Geng #define CLK_EMMC_2X_EN 94 286*8c18feceSCixi Geng #define CLK_EMMC_1X_EN 95 287*8c18feceSCixi Geng #define CLK_PLL_TEST_EN 96 288*8c18feceSCixi Geng #define CLK_CPHY_CFG_EN 97 289*8c18feceSCixi Geng #define CLK_DEBUG_TS_EN 98 290*8c18feceSCixi Geng #define CLK_ACCESS_AUD_EN 99 291*8c18feceSCixi Geng #define CLK_AON_APB_GATE_NUM (CLK_ACCESS_AUD_EN + 1) 292*8c18feceSCixi Geng 293*8c18feceSCixi Geng #define CLK_MM_CPP_EB 0 294*8c18feceSCixi Geng #define CLK_MM_JPG_EB 1 295*8c18feceSCixi Geng #define CLK_MM_DCAM_EB 2 296*8c18feceSCixi Geng #define CLK_MM_ISP_EB 3 297*8c18feceSCixi Geng #define CLK_MM_CSI2_EB 4 298*8c18feceSCixi Geng #define CLK_MM_CSI1_EB 5 299*8c18feceSCixi Geng #define CLK_MM_CSI0_EB 6 300*8c18feceSCixi Geng #define CLK_MM_CKG_EB 7 301*8c18feceSCixi Geng #define CLK_ISP_AHB_EB 8 302*8c18feceSCixi Geng #define CLK_MM_DVFS_EB 9 303*8c18feceSCixi Geng #define CLK_MM_FD_EB 10 304*8c18feceSCixi Geng #define CLK_MM_SENSOR2_EB 11 305*8c18feceSCixi Geng #define CLK_MM_SENSOR1_EB 12 306*8c18feceSCixi Geng #define CLK_MM_SENSOR0_EB 13 307*8c18feceSCixi Geng #define CLK_MM_MIPI_CSI2_EB 14 308*8c18feceSCixi Geng #define CLK_MM_MIPI_CSI1_EB 15 309*8c18feceSCixi Geng #define CLK_MM_MIPI_CSI0_EB 16 310*8c18feceSCixi Geng #define CLK_DCAM_AXI_EB 17 311*8c18feceSCixi Geng #define CLK_ISP_AXI_EB 18 312*8c18feceSCixi Geng #define CLK_MM_CPHY_EB 19 313*8c18feceSCixi Geng #define CLK_MM_GATE_CLK_NUM (CLK_MM_CPHY_EB + 1) 314*8c18feceSCixi Geng 315*8c18feceSCixi Geng #define CLK_SIM0_EB 0 316*8c18feceSCixi Geng #define CLK_IIS0_EB 1 317*8c18feceSCixi Geng #define CLK_IIS1_EB 2 318*8c18feceSCixi Geng #define CLK_IIS2_EB 3 319*8c18feceSCixi Geng #define CLK_APB_REG_EB 4 320*8c18feceSCixi Geng #define CLK_SPI0_EB 5 321*8c18feceSCixi Geng #define CLK_SPI1_EB 6 322*8c18feceSCixi Geng #define CLK_SPI2_EB 7 323*8c18feceSCixi Geng #define CLK_SPI3_EB 8 324*8c18feceSCixi Geng #define CLK_I2C0_EB 9 325*8c18feceSCixi Geng #define CLK_I2C1_EB 10 326*8c18feceSCixi Geng #define CLK_I2C2_EB 11 327*8c18feceSCixi Geng #define CLK_I2C3_EB 12 328*8c18feceSCixi Geng #define CLK_I2C4_EB 13 329*8c18feceSCixi Geng #define CLK_UART0_EB 14 330*8c18feceSCixi Geng #define CLK_UART1_EB 15 331*8c18feceSCixi Geng #define CLK_UART2_EB 16 332*8c18feceSCixi Geng #define CLK_SIM0_32K_EB 17 333*8c18feceSCixi Geng #define CLK_SPI0_LFIN_EB 18 334*8c18feceSCixi Geng #define CLK_SPI1_LFIN_EB 19 335*8c18feceSCixi Geng #define CLK_SPI2_LFIN_EB 20 336*8c18feceSCixi Geng #define CLK_SPI3_LFIN_EB 21 337*8c18feceSCixi Geng #define CLK_SDIO0_EB 22 338*8c18feceSCixi Geng #define CLK_SDIO1_EB 23 339*8c18feceSCixi Geng #define CLK_SDIO2_EB 24 340*8c18feceSCixi Geng #define CLK_EMMC_EB 25 341*8c18feceSCixi Geng #define CLK_SDIO0_32K_EB 26 342*8c18feceSCixi Geng #define CLK_SDIO1_32K_EB 27 343*8c18feceSCixi Geng #define CLK_SDIO2_32K_EB 28 344*8c18feceSCixi Geng #define CLK_EMMC_32K_EB 29 345*8c18feceSCixi Geng #define CLK_AP_APB_GATE_NUM (CLK_EMMC_32K_EB + 1) 346*8c18feceSCixi Geng 347*8c18feceSCixi Geng #define CLK_GPU_CORE_EB 0 348*8c18feceSCixi Geng #define CLK_GPU_CORE 1 349*8c18feceSCixi Geng #define CLK_GPU_MEM_EB 2 350*8c18feceSCixi Geng #define CLK_GPU_MEM 3 351*8c18feceSCixi Geng #define CLK_GPU_SYS_EB 4 352*8c18feceSCixi Geng #define CLK_GPU_SYS 5 353*8c18feceSCixi Geng #define CLK_GPU_CLK_NUM (CLK_GPU_SYS + 1) 354*8c18feceSCixi Geng 355*8c18feceSCixi Geng #define CLK_AUDCP_IIS0_EB 0 356*8c18feceSCixi Geng #define CLK_AUDCP_IIS1_EB 1 357*8c18feceSCixi Geng #define CLK_AUDCP_IIS2_EB 2 358*8c18feceSCixi Geng #define CLK_AUDCP_UART_EB 3 359*8c18feceSCixi Geng #define CLK_AUDCP_DMA_CP_EB 4 360*8c18feceSCixi Geng #define CLK_AUDCP_DMA_AP_EB 5 361*8c18feceSCixi Geng #define CLK_AUDCP_SRC48K_EB 6 362*8c18feceSCixi Geng #define CLK_AUDCP_MCDT_EB 7 363*8c18feceSCixi Geng #define CLK_AUDCP_VBCIFD_EB 8 364*8c18feceSCixi Geng #define CLK_AUDCP_VBC_EB 9 365*8c18feceSCixi Geng #define CLK_AUDCP_SPLK_EB 10 366*8c18feceSCixi Geng #define CLK_AUDCP_ICU_EB 11 367*8c18feceSCixi Geng #define CLK_AUDCP_DMA_AP_ASHB_EB 12 368*8c18feceSCixi Geng #define CLK_AUDCP_DMA_CP_ASHB_EB 13 369*8c18feceSCixi Geng #define CLK_AUDCP_AUD_EB 14 370*8c18feceSCixi Geng #define CLK_AUDCP_VBC_24M_EB 15 371*8c18feceSCixi Geng #define CLK_AUDCP_TMR_26M_EB 16 372*8c18feceSCixi Geng #define CLK_AUDCP_DVFS_ASHB_EB 17 373*8c18feceSCixi Geng #define CLK_AUDCP_AHB_GATE_NUM (CLK_AUDCP_DVFS_ASHB_EB + 1) 374*8c18feceSCixi Geng 375*8c18feceSCixi Geng #define CLK_AUDCP_WDG_EB 0 376*8c18feceSCixi Geng #define CLK_AUDCP_RTC_WDG_EB 1 377*8c18feceSCixi Geng #define CLK_AUDCP_TMR0_EB 2 378*8c18feceSCixi Geng #define CLK_AUDCP_TMR1_EB 3 379*8c18feceSCixi Geng #define CLK_AUDCP_APB_GATE_NUM (CLK_AUDCP_TMR1_EB + 1) 380*8c18feceSCixi Geng 381*8c18feceSCixi Geng #define CLK_ACORE0 0 382*8c18feceSCixi Geng #define CLK_ACORE1 1 383*8c18feceSCixi Geng #define CLK_ACORE2 2 384*8c18feceSCixi Geng #define CLK_ACORE3 3 385*8c18feceSCixi Geng #define CLK_ACORE4 4 386*8c18feceSCixi Geng #define CLK_ACORE5 5 387*8c18feceSCixi Geng #define CLK_PCORE0 6 388*8c18feceSCixi Geng #define CLK_PCORE1 7 389*8c18feceSCixi Geng #define CLK_SCU 8 390*8c18feceSCixi Geng #define CLK_ACE 9 391*8c18feceSCixi Geng #define CLK_PERIPH 10 392*8c18feceSCixi Geng #define CLK_GIC 11 393*8c18feceSCixi Geng #define CLK_ATB 12 394*8c18feceSCixi Geng #define CLK_DEBUG_APB 13 395*8c18feceSCixi Geng #define CLK_APCPU_SEC_NUM (CLK_DEBUG_APB + 1) 396*8c18feceSCixi Geng 397*8c18feceSCixi Geng #endif /* _DT_BINDINGS_CLK_UMS512_H_ */ 398