1cd030a78SIcenowy Zheng /*
2cd030a78SIcenowy Zheng  * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
3cd030a78SIcenowy Zheng  *
4cd030a78SIcenowy Zheng  * This file is dual-licensed: you can use it either under the terms
5cd030a78SIcenowy Zheng  * of the GPL or the X11 license, at your option. Note that this dual
6cd030a78SIcenowy Zheng  * licensing only applies to this file, and not this project as a
7cd030a78SIcenowy Zheng  * whole.
8cd030a78SIcenowy Zheng  *
9cd030a78SIcenowy Zheng  *  a) This file is free software; you can redistribute it and/or
10cd030a78SIcenowy Zheng  *     modify it under the terms of the GNU General Public License as
11cd030a78SIcenowy Zheng  *     published by the Free Software Foundation; either version 2 of the
12cd030a78SIcenowy Zheng  *     License, or (at your option) any later version.
13cd030a78SIcenowy Zheng  *
14cd030a78SIcenowy Zheng  *     This file is distributed in the hope that it will be useful,
15cd030a78SIcenowy Zheng  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
16cd030a78SIcenowy Zheng  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17cd030a78SIcenowy Zheng  *     GNU General Public License for more details.
18cd030a78SIcenowy Zheng  *
19cd030a78SIcenowy Zheng  * Or, alternatively,
20cd030a78SIcenowy Zheng  *
21cd030a78SIcenowy Zheng  *  b) Permission is hereby granted, free of charge, to any person
22cd030a78SIcenowy Zheng  *     obtaining a copy of this software and associated documentation
23cd030a78SIcenowy Zheng  *     files (the "Software"), to deal in the Software without
24cd030a78SIcenowy Zheng  *     restriction, including without limitation the rights to use,
25cd030a78SIcenowy Zheng  *     copy, modify, merge, publish, distribute, sublicense, and/or
26cd030a78SIcenowy Zheng  *     sell copies of the Software, and to permit persons to whom the
27cd030a78SIcenowy Zheng  *     Software is furnished to do so, subject to the following
28cd030a78SIcenowy Zheng  *     conditions:
29cd030a78SIcenowy Zheng  *
30cd030a78SIcenowy Zheng  *     The above copyright notice and this permission notice shall be
31cd030a78SIcenowy Zheng  *     included in all copies or substantial portions of the Software.
32cd030a78SIcenowy Zheng  *
33cd030a78SIcenowy Zheng  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34cd030a78SIcenowy Zheng  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35cd030a78SIcenowy Zheng  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36cd030a78SIcenowy Zheng  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37cd030a78SIcenowy Zheng  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38cd030a78SIcenowy Zheng  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39cd030a78SIcenowy Zheng  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40cd030a78SIcenowy Zheng  *     OTHER DEALINGS IN THE SOFTWARE.
41cd030a78SIcenowy Zheng  */
42cd030a78SIcenowy Zheng 
43cd030a78SIcenowy Zheng #ifndef _DT_BINDINGS_CLK_SUN8I_R40_H_
44cd030a78SIcenowy Zheng #define _DT_BINDINGS_CLK_SUN8I_R40_H_
45cd030a78SIcenowy Zheng 
46d18e8534SJernej Skrabec #define CLK_PLL_VIDEO0		7
47d18e8534SJernej Skrabec 
48d18e8534SJernej Skrabec #define CLK_PLL_VIDEO1		16
49d18e8534SJernej Skrabec 
50cd030a78SIcenowy Zheng #define CLK_CPU			24
51cd030a78SIcenowy Zheng 
52cd030a78SIcenowy Zheng #define CLK_BUS_MIPI_DSI	29
53cd030a78SIcenowy Zheng #define CLK_BUS_CE		30
54cd030a78SIcenowy Zheng #define CLK_BUS_DMA		31
55cd030a78SIcenowy Zheng #define CLK_BUS_MMC0		32
56cd030a78SIcenowy Zheng #define CLK_BUS_MMC1		33
57cd030a78SIcenowy Zheng #define CLK_BUS_MMC2		34
58cd030a78SIcenowy Zheng #define CLK_BUS_MMC3		35
59cd030a78SIcenowy Zheng #define CLK_BUS_NAND		36
60cd030a78SIcenowy Zheng #define CLK_BUS_DRAM		37
61cd030a78SIcenowy Zheng #define CLK_BUS_EMAC		38
62cd030a78SIcenowy Zheng #define CLK_BUS_TS		39
63cd030a78SIcenowy Zheng #define CLK_BUS_HSTIMER		40
64cd030a78SIcenowy Zheng #define CLK_BUS_SPI0		41
65cd030a78SIcenowy Zheng #define CLK_BUS_SPI1		42
66cd030a78SIcenowy Zheng #define CLK_BUS_SPI2		43
67cd030a78SIcenowy Zheng #define CLK_BUS_SPI3		44
68cd030a78SIcenowy Zheng #define CLK_BUS_SATA		45
69cd030a78SIcenowy Zheng #define CLK_BUS_OTG		46
70cd030a78SIcenowy Zheng #define CLK_BUS_EHCI0		47
71cd030a78SIcenowy Zheng #define CLK_BUS_EHCI1		48
72cd030a78SIcenowy Zheng #define CLK_BUS_EHCI2		49
73cd030a78SIcenowy Zheng #define CLK_BUS_OHCI0		50
74cd030a78SIcenowy Zheng #define CLK_BUS_OHCI1		51
75cd030a78SIcenowy Zheng #define CLK_BUS_OHCI2		52
76cd030a78SIcenowy Zheng #define CLK_BUS_VE		53
77cd030a78SIcenowy Zheng #define CLK_BUS_MP		54
78cd030a78SIcenowy Zheng #define CLK_BUS_DEINTERLACE	55
79cd030a78SIcenowy Zheng #define CLK_BUS_CSI0		56
80cd030a78SIcenowy Zheng #define CLK_BUS_CSI1		57
81cd030a78SIcenowy Zheng #define CLK_BUS_HDMI1		58
82cd030a78SIcenowy Zheng #define CLK_BUS_HDMI0		59
83cd030a78SIcenowy Zheng #define CLK_BUS_DE		60
84cd030a78SIcenowy Zheng #define CLK_BUS_TVE0		61
85cd030a78SIcenowy Zheng #define CLK_BUS_TVE1		62
86cd030a78SIcenowy Zheng #define CLK_BUS_TVE_TOP		63
87cd030a78SIcenowy Zheng #define CLK_BUS_GMAC		64
88cd030a78SIcenowy Zheng #define CLK_BUS_GPU		65
89cd030a78SIcenowy Zheng #define CLK_BUS_TVD0		66
90cd030a78SIcenowy Zheng #define CLK_BUS_TVD1		67
91cd030a78SIcenowy Zheng #define CLK_BUS_TVD2		68
92cd030a78SIcenowy Zheng #define CLK_BUS_TVD3		69
93cd030a78SIcenowy Zheng #define CLK_BUS_TVD_TOP		70
94cd030a78SIcenowy Zheng #define CLK_BUS_TCON_LCD0	71
95cd030a78SIcenowy Zheng #define CLK_BUS_TCON_LCD1	72
96cd030a78SIcenowy Zheng #define CLK_BUS_TCON_TV0	73
97cd030a78SIcenowy Zheng #define CLK_BUS_TCON_TV1	74
98cd030a78SIcenowy Zheng #define CLK_BUS_TCON_TOP	75
99cd030a78SIcenowy Zheng #define CLK_BUS_CODEC		76
100cd030a78SIcenowy Zheng #define CLK_BUS_SPDIF		77
101cd030a78SIcenowy Zheng #define CLK_BUS_AC97		78
102cd030a78SIcenowy Zheng #define CLK_BUS_PIO		79
103cd030a78SIcenowy Zheng #define CLK_BUS_IR0		80
104cd030a78SIcenowy Zheng #define CLK_BUS_IR1		81
105cd030a78SIcenowy Zheng #define CLK_BUS_THS		82
106cd030a78SIcenowy Zheng #define CLK_BUS_KEYPAD		83
107cd030a78SIcenowy Zheng #define CLK_BUS_I2S0		84
108cd030a78SIcenowy Zheng #define CLK_BUS_I2S1		85
109cd030a78SIcenowy Zheng #define CLK_BUS_I2S2		86
110cd030a78SIcenowy Zheng #define CLK_BUS_I2C0		87
111cd030a78SIcenowy Zheng #define CLK_BUS_I2C1		88
112cd030a78SIcenowy Zheng #define CLK_BUS_I2C2		89
113cd030a78SIcenowy Zheng #define CLK_BUS_I2C3		90
114cd030a78SIcenowy Zheng #define CLK_BUS_CAN		91
115cd030a78SIcenowy Zheng #define CLK_BUS_SCR		92
116cd030a78SIcenowy Zheng #define CLK_BUS_PS20		93
117cd030a78SIcenowy Zheng #define CLK_BUS_PS21		94
118cd030a78SIcenowy Zheng #define CLK_BUS_I2C4		95
119cd030a78SIcenowy Zheng #define CLK_BUS_UART0		96
120cd030a78SIcenowy Zheng #define CLK_BUS_UART1		97
121cd030a78SIcenowy Zheng #define CLK_BUS_UART2		98
122cd030a78SIcenowy Zheng #define CLK_BUS_UART3		99
123cd030a78SIcenowy Zheng #define CLK_BUS_UART4		100
124cd030a78SIcenowy Zheng #define CLK_BUS_UART5		101
125cd030a78SIcenowy Zheng #define CLK_BUS_UART6		102
126cd030a78SIcenowy Zheng #define CLK_BUS_UART7		103
127cd030a78SIcenowy Zheng #define CLK_BUS_DBG		104
128cd030a78SIcenowy Zheng 
129cd030a78SIcenowy Zheng #define CLK_THS			105
130cd030a78SIcenowy Zheng #define CLK_NAND		106
131cd030a78SIcenowy Zheng #define CLK_MMC0		107
132cd030a78SIcenowy Zheng #define CLK_MMC1		108
133cd030a78SIcenowy Zheng #define CLK_MMC2		109
134cd030a78SIcenowy Zheng #define CLK_MMC3		110
135cd030a78SIcenowy Zheng #define CLK_TS			111
136cd030a78SIcenowy Zheng #define CLK_CE			112
137cd030a78SIcenowy Zheng #define CLK_SPI0		113
138cd030a78SIcenowy Zheng #define CLK_SPI1		114
139cd030a78SIcenowy Zheng #define CLK_SPI2		115
140cd030a78SIcenowy Zheng #define CLK_SPI3		116
141cd030a78SIcenowy Zheng #define CLK_I2S0		117
142cd030a78SIcenowy Zheng #define CLK_I2S1		118
143cd030a78SIcenowy Zheng #define CLK_I2S2		119
144cd030a78SIcenowy Zheng #define CLK_AC97		120
145cd030a78SIcenowy Zheng #define CLK_SPDIF		121
146cd030a78SIcenowy Zheng #define CLK_KEYPAD		122
147cd030a78SIcenowy Zheng #define CLK_SATA		123
148cd030a78SIcenowy Zheng #define CLK_USB_PHY0		124
149cd030a78SIcenowy Zheng #define CLK_USB_PHY1		125
150cd030a78SIcenowy Zheng #define CLK_USB_PHY2		126
151cd030a78SIcenowy Zheng #define CLK_USB_OHCI0		127
152cd030a78SIcenowy Zheng #define CLK_USB_OHCI1		128
153cd030a78SIcenowy Zheng #define CLK_USB_OHCI2		129
154cd030a78SIcenowy Zheng #define CLK_IR0			130
155cd030a78SIcenowy Zheng #define CLK_IR1			131
156cd030a78SIcenowy Zheng 
157cd030a78SIcenowy Zheng #define CLK_DRAM_VE		133
158cd030a78SIcenowy Zheng #define CLK_DRAM_CSI0		134
159cd030a78SIcenowy Zheng #define CLK_DRAM_CSI1		135
160cd030a78SIcenowy Zheng #define CLK_DRAM_TS		136
161cd030a78SIcenowy Zheng #define CLK_DRAM_TVD		137
162cd030a78SIcenowy Zheng #define CLK_DRAM_MP		138
163cd030a78SIcenowy Zheng #define CLK_DRAM_DEINTERLACE	139
164cd030a78SIcenowy Zheng #define CLK_DE			140
165cd030a78SIcenowy Zheng #define CLK_MP			141
166cd030a78SIcenowy Zheng #define CLK_TCON_LCD0		142
167cd030a78SIcenowy Zheng #define CLK_TCON_LCD1		143
168cd030a78SIcenowy Zheng #define CLK_TCON_TV0		144
169cd030a78SIcenowy Zheng #define CLK_TCON_TV1		145
170cd030a78SIcenowy Zheng #define CLK_DEINTERLACE		146
171cd030a78SIcenowy Zheng #define CLK_CSI1_MCLK		147
172cd030a78SIcenowy Zheng #define CLK_CSI_SCLK		148
173cd030a78SIcenowy Zheng #define CLK_CSI0_MCLK		149
174cd030a78SIcenowy Zheng #define CLK_VE			150
175cd030a78SIcenowy Zheng #define CLK_CODEC		151
176cd030a78SIcenowy Zheng #define CLK_AVS			152
177cd030a78SIcenowy Zheng #define CLK_HDMI		153
178cd030a78SIcenowy Zheng #define CLK_HDMI_SLOW		154
179*b406cadbSChen-Yu Tsai #define CLK_MBUS		155
180cd030a78SIcenowy Zheng #define CLK_DSI_DPHY		156
181cd030a78SIcenowy Zheng #define CLK_TVE0		157
182cd030a78SIcenowy Zheng #define CLK_TVE1		158
183cd030a78SIcenowy Zheng #define CLK_TVD0		159
184cd030a78SIcenowy Zheng #define CLK_TVD1		160
185cd030a78SIcenowy Zheng #define CLK_TVD2		161
186cd030a78SIcenowy Zheng #define CLK_TVD3		162
187cd030a78SIcenowy Zheng #define CLK_GPU			163
188cd030a78SIcenowy Zheng #define CLK_OUTA		164
189cd030a78SIcenowy Zheng #define CLK_OUTB		165
190cd030a78SIcenowy Zheng 
191cd030a78SIcenowy Zheng #endif /* _DT_BINDINGS_CLK_SUN8I_R40_H_ */
192