163944891SThierry Reding /* SPDX-License-Identifier: GPL-2.0 */ 240efe139SSameer Pujar /* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */ 363944891SThierry Reding 463944891SThierry Reding #ifndef DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H 563944891SThierry Reding #define DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H 663944891SThierry Reding 7fc5e0e37SMikko Perttunen /** 8fc5e0e37SMikko Perttunen * @file 9fc5e0e37SMikko Perttunen * @defgroup bpmp_clock_ids Clock ID's 10fc5e0e37SMikko Perttunen * @{ 11fc5e0e37SMikko Perttunen */ 12*41155b6fSJon Hunter /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON */ 13*41155b6fSJon Hunter #define TEGRA234_CLK_ACTMON 1U 14*41155b6fSJon Hunter /** @brief output of gate CLK_ENB_ADSP */ 15*41155b6fSJon Hunter #define TEGRA234_CLK_ADSP 2U 16*41155b6fSJon Hunter /** @brief output of gate CLK_ENB_ADSPNEON */ 17*41155b6fSJon Hunter #define TEGRA234_CLK_ADSPNEON 3U 1840efe139SSameer Pujar /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AHUB */ 1940efe139SSameer Pujar #define TEGRA234_CLK_AHUB 4U 2040efe139SSameer Pujar /** @brief output of gate CLK_ENB_APB2APE */ 2140efe139SSameer Pujar #define TEGRA234_CLK_APB2APE 5U 2240efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_APE */ 2340efe139SSameer Pujar #define TEGRA234_CLK_APE 6U 2440efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK */ 2540efe139SSameer Pujar #define TEGRA234_CLK_AUD_MCLK 7U 26*41155b6fSJon Hunter /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB */ 27*41155b6fSJon Hunter #define TEGRA234_CLK_AXI_CBB 8U 28*41155b6fSJon Hunter /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN1 */ 29*41155b6fSJon Hunter #define TEGRA234_CLK_CAN1 9U 30*41155b6fSJon Hunter /** @brief output of gate CLK_ENB_CAN1_HOST */ 31*41155b6fSJon Hunter #define TEGRA234_CLK_CAN1_HOST 10U 32*41155b6fSJon Hunter /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN2 */ 33*41155b6fSJon Hunter #define TEGRA234_CLK_CAN2 11U 34*41155b6fSJon Hunter /** @brief output of gate CLK_ENB_CAN2_HOST */ 35*41155b6fSJon Hunter #define TEGRA234_CLK_CAN2_HOST 12U 36*41155b6fSJon Hunter /** @brief output of divider CLK_RST_CONTROLLER_CLK_M_DIVIDE */ 37*41155b6fSJon Hunter #define TEGRA234_CLK_CLK_M 14U 3840efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1 */ 3940efe139SSameer Pujar #define TEGRA234_CLK_DMIC1 15U 4040efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2 */ 4140efe139SSameer Pujar #define TEGRA234_CLK_DMIC2 16U 4240efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3 */ 4340efe139SSameer Pujar #define TEGRA234_CLK_DMIC3 17U 4440efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4 */ 4540efe139SSameer Pujar #define TEGRA234_CLK_DMIC4 18U 46*41155b6fSJon Hunter /** @brief output of gate CLK_ENB_DPAUX */ 47*41155b6fSJon Hunter #define TEGRA234_CLK_DPAUX 19U 48*41155b6fSJon Hunter /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG1 */ 49*41155b6fSJon Hunter #define TEGRA234_CLK_NVJPG1 20U 50*41155b6fSJon Hunter /** 51*41155b6fSJon Hunter * @brief output of mux controlled by CLK_RST_CONTROLLER_ACLK_BURST_POLICY 52*41155b6fSJon Hunter * divided by the divider controlled by ACLK_CLK_DIVISOR in 53*41155b6fSJon Hunter * CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER 54*41155b6fSJon Hunter */ 55*41155b6fSJon Hunter #define TEGRA234_CLK_ACLK 21U 56*41155b6fSJon Hunter /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT switch divider output */ 57*41155b6fSJon Hunter #define TEGRA234_CLK_MSS_ENCRYPT 22U 58*41155b6fSJon Hunter /** @brief clock recovered from EAVB input */ 59*41155b6fSJon Hunter #define TEGRA234_CLK_EQOS_RX_INPUT 23U 60*41155b6fSJon Hunter /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB switch divider output */ 61*41155b6fSJon Hunter #define TEGRA234_CLK_AON_APB 25U 62*41155b6fSJon Hunter /** @brief CLK_RST_CONTROLLER_AON_NIC_RATE divider output */ 63*41155b6fSJon Hunter #define TEGRA234_CLK_AON_NIC 26U 64*41155b6fSJon Hunter /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC switch divider output */ 65*41155b6fSJon Hunter #define TEGRA234_CLK_AON_CPU_NIC 27U 66*41155b6fSJon Hunter /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLA1_BASE for use by audio clocks */ 67*41155b6fSJon Hunter #define TEGRA234_CLK_PLLA1 28U 6840efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1 */ 6940efe139SSameer Pujar #define TEGRA234_CLK_DSPK1 29U 7040efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2 */ 7140efe139SSameer Pujar #define TEGRA234_CLK_DSPK2 30U 72c3859c14SThierry Reding /** 73c3859c14SThierry Reding * @brief controls the EMC clock frequency. 74c3859c14SThierry Reding * @details Doing a clk_set_rate on this clock will select the 75c3859c14SThierry Reding * appropriate clock source, program the source rate and execute a 76c3859c14SThierry Reding * specific sequence to switch to the new clock source for both memory 77c3859c14SThierry Reding * controllers. This can be used to control the balance between memory 78c3859c14SThierry Reding * throughput and memory controller power. 79c3859c14SThierry Reding */ 80c3859c14SThierry Reding #define TEGRA234_CLK_EMC 31U 81*41155b6fSJon Hunter /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_AXI_CLK_0 divider gated output */ 82*41155b6fSJon Hunter #define TEGRA234_CLK_EQOS_AXI 32U 83*41155b6fSJon Hunter /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0 divider gated output */ 84*41155b6fSJon Hunter #define TEGRA234_CLK_EQOS_PTP_REF 33U 85*41155b6fSJon Hunter /** @brief output of gate CLK_ENB_EQOS_RX */ 86*41155b6fSJon Hunter #define TEGRA234_CLK_EQOS_RX 34U 87*41155b6fSJon Hunter /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK divider gated output */ 88*41155b6fSJon Hunter #define TEGRA234_CLK_EQOS_TX 35U 89*41155b6fSJon Hunter /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1 */ 90*41155b6fSJon Hunter #define TEGRA234_CLK_EXTPERIPH1 36U 91*41155b6fSJon Hunter /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2 */ 92*41155b6fSJon Hunter #define TEGRA234_CLK_EXTPERIPH2 37U 93*41155b6fSJon Hunter /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3 */ 94*41155b6fSJon Hunter #define TEGRA234_CLK_EXTPERIPH3 38U 95*41155b6fSJon Hunter /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4 */ 96*41155b6fSJon Hunter #define TEGRA234_CLK_EXTPERIPH4 39U 9763944891SThierry Reding /** @brief output of gate CLK_ENB_FUSE */ 98fc5e0e37SMikko Perttunen #define TEGRA234_CLK_FUSE 40U 99*41155b6fSJon Hunter /** @brief output of GPU GPC0 clkGen (in 1x mode same rate as GPC0 MUX2 out) */ 100*41155b6fSJon Hunter #define TEGRA234_CLK_GPC0CLK 41U 101*41155b6fSJon Hunter /** @brief TODO */ 102*41155b6fSJon Hunter #define TEGRA234_CLK_GPU_PWR 42U 103*41155b6fSJon Hunter /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X */ 104*41155b6fSJon Hunter /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X */ 105*41155b6fSJon Hunter #define TEGRA234_CLK_HOST1X 46U 106*41155b6fSJon Hunter /** @brief xusb_hs_hsicp_clk */ 107*41155b6fSJon Hunter #define TEGRA234_CLK_XUSB_HS_HSICP 47U 108bb747becSAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C1 */ 109bb747becSAkhil R #define TEGRA234_CLK_I2C1 48U 110bb747becSAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C2 */ 111bb747becSAkhil R #define TEGRA234_CLK_I2C2 49U 112bb747becSAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C3 */ 113bb747becSAkhil R #define TEGRA234_CLK_I2C3 50U 114bb747becSAkhil R /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C4 */ 115bb747becSAkhil R #define TEGRA234_CLK_I2C4 51U 116bb747becSAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */ 117bb747becSAkhil R #define TEGRA234_CLK_I2C6 52U 118bb747becSAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C7 */ 119bb747becSAkhil R #define TEGRA234_CLK_I2C7 53U 120bb747becSAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C8 */ 121bb747becSAkhil R #define TEGRA234_CLK_I2C8 54U 122bb747becSAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C9 */ 123bb747becSAkhil R #define TEGRA234_CLK_I2C9 55U 12440efe139SSameer Pujar /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S1 */ 12540efe139SSameer Pujar #define TEGRA234_CLK_I2S1 56U 12640efe139SSameer Pujar /** @brief clock recovered from I2S1 input */ 12740efe139SSameer Pujar #define TEGRA234_CLK_I2S1_SYNC_INPUT 57U 12840efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S2 */ 12940efe139SSameer Pujar #define TEGRA234_CLK_I2S2 58U 13040efe139SSameer Pujar /** @brief clock recovered from I2S2 input */ 13140efe139SSameer Pujar #define TEGRA234_CLK_I2S2_SYNC_INPUT 59U 13240efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S3 */ 13340efe139SSameer Pujar #define TEGRA234_CLK_I2S3 60U 13440efe139SSameer Pujar /** @brief clock recovered from I2S3 input */ 13540efe139SSameer Pujar #define TEGRA234_CLK_I2S3_SYNC_INPUT 61U 13640efe139SSameer Pujar /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S4 */ 13740efe139SSameer Pujar #define TEGRA234_CLK_I2S4 62U 13840efe139SSameer Pujar /** @brief clock recovered from I2S4 input */ 13940efe139SSameer Pujar #define TEGRA234_CLK_I2S4_SYNC_INPUT 63U 14040efe139SSameer Pujar /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S5 */ 14140efe139SSameer Pujar #define TEGRA234_CLK_I2S5 64U 14240efe139SSameer Pujar /** @brief clock recovered from I2S5 input */ 14340efe139SSameer Pujar #define TEGRA234_CLK_I2S5_SYNC_INPUT 65U 14440efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S6 */ 14540efe139SSameer Pujar #define TEGRA234_CLK_I2S6 66U 14640efe139SSameer Pujar /** @brief clock recovered from I2S6 input */ 14740efe139SSameer Pujar #define TEGRA234_CLK_I2S6_SYNC_INPUT 67U 148*41155b6fSJon Hunter /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_ISP */ 149*41155b6fSJon Hunter #define TEGRA234_CLK_ISP 69U 150*41155b6fSJon Hunter /** @brief Monitored branch of EQOS_RX clock */ 151*41155b6fSJon Hunter #define TEGRA234_CLK_EQOS_RX_M 70U 152*41155b6fSJon Hunter /** @brief CLK_RST_CONTROLLER_MAUDCLK_OUT_SWITCH_DIVIDER switch divider output (maudclk) */ 153*41155b6fSJon Hunter #define TEGRA234_CLK_MAUD 71U 154*41155b6fSJon Hunter /** @brief output of gate CLK_ENB_MIPI_CAL */ 155*41155b6fSJon Hunter #define TEGRA234_CLK_MIPI_CAL 72U 156*41155b6fSJon Hunter /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED */ 157*41155b6fSJon Hunter #define TEGRA234_CLK_MPHY_CORE_PLL_FIXED 73U 158*41155b6fSJon Hunter /** @brief output of gate CLK_ENB_MPHY_L0_RX_ANA */ 159*41155b6fSJon Hunter #define TEGRA234_CLK_MPHY_L0_RX_ANA 74U 160*41155b6fSJon Hunter /** @brief output of gate CLK_ENB_MPHY_L0_RX_LS_BIT */ 161*41155b6fSJon Hunter #define TEGRA234_CLK_MPHY_L0_RX_LS_BIT 75U 162*41155b6fSJon Hunter /** @brief output of gate CLK_ENB_MPHY_L0_RX_SYMB */ 163*41155b6fSJon Hunter #define TEGRA234_CLK_MPHY_L0_RX_SYMB 76U 164*41155b6fSJon Hunter /** @brief output of gate CLK_ENB_MPHY_L0_TX_LS_3XBIT */ 165*41155b6fSJon Hunter #define TEGRA234_CLK_MPHY_L0_TX_LS_3XBIT 77U 166*41155b6fSJon Hunter /** @brief output of gate CLK_ENB_MPHY_L0_TX_SYMB */ 167*41155b6fSJon Hunter #define TEGRA234_CLK_MPHY_L0_TX_SYMB 78U 168*41155b6fSJon Hunter /** @brief output of gate CLK_ENB_MPHY_L1_RX_ANA */ 169*41155b6fSJon Hunter #define TEGRA234_CLK_MPHY_L1_RX_ANA 79U 170*41155b6fSJon Hunter /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF */ 171*41155b6fSJon Hunter #define TEGRA234_CLK_MPHY_TX_1MHZ_REF 80U 172*41155b6fSJon Hunter /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI */ 173*41155b6fSJon Hunter #define TEGRA234_CLK_NVCSI 81U 174*41155b6fSJon Hunter /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP */ 175*41155b6fSJon Hunter #define TEGRA234_CLK_NVCSILP 82U 1760e2b014eSMikko Perttunen /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC */ 1770e2b014eSMikko Perttunen #define TEGRA234_CLK_NVDEC 83U 178*41155b6fSJon Hunter /** @brief CLK_RST_CONTROLLER_HUBCLK_OUT_SWITCH_DIVIDER switch divider output (hubclk) */ 179*41155b6fSJon Hunter #define TEGRA234_CLK_HUB 84U 180*41155b6fSJon Hunter /** @brief CLK_RST_CONTROLLER_DISPCLK_SWITCH_DIVIDER switch divider output (dispclk) */ 181*41155b6fSJon Hunter #define TEGRA234_CLK_DISP 85U 182*41155b6fSJon Hunter /** @brief RG_CLK_CTRL__0_DIV divider output (nvdisplay_p0_clk) */ 183*41155b6fSJon Hunter #define TEGRA234_CLK_NVDISPLAY_P0 86U 184*41155b6fSJon Hunter /** @brief RG_CLK_CTRL__1_DIV divider output (nvdisplay_p1_clk) */ 185*41155b6fSJon Hunter #define TEGRA234_CLK_NVDISPLAY_P1 87U 186*41155b6fSJon Hunter /** @brief DSC_CLK (DISPCLK ÷ 3) */ 187*41155b6fSJon Hunter #define TEGRA234_CLK_DSC 88U 188*41155b6fSJon Hunter /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVENC */ 189*41155b6fSJon Hunter #define TEGRA234_CLK_NVENC 89U 190*41155b6fSJon Hunter /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG */ 191*41155b6fSJon Hunter #define TEGRA234_CLK_NVJPG 90U 192*41155b6fSJon Hunter /** @brief input from Tegra's XTAL_IN */ 193*41155b6fSJon Hunter #define TEGRA234_CLK_OSC 91U 194*41155b6fSJon Hunter /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH switch divider output */ 195*41155b6fSJon Hunter #define TEGRA234_CLK_AON_TOUCH 92U 19640efe139SSameer Pujar /** PLL controlled by CLK_RST_CONTROLLER_PLLA_BASE for use by audio clocks */ 19740efe139SSameer Pujar #define TEGRA234_CLK_PLLA 93U 198*41155b6fSJon Hunter /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLAON_BASE for use by IP blocks in the AON domain */ 199*41155b6fSJon Hunter #define TEGRA234_CLK_PLLAON 94U 200*41155b6fSJon Hunter /** Fixed 100MHz PLL for PCIe, SATA and superspeed USB */ 201*41155b6fSJon Hunter #define TEGRA234_CLK_PLLE 100U 202*41155b6fSJon Hunter /** @brief PLLP vco output */ 203*41155b6fSJon Hunter #define TEGRA234_CLK_PLLP 101U 204bb747becSAkhil R /** @brief PLLP clk output */ 205bb747becSAkhil R #define TEGRA234_CLK_PLLP_OUT0 102U 206*41155b6fSJon Hunter /** Fixed frequency 960MHz PLL for USB and EAVB */ 207*41155b6fSJon Hunter #define TEGRA234_CLK_UTMIP_PLL 103U 20840efe139SSameer Pujar /** @brief output of the divider CLK_RST_CONTROLLER_PLLA_OUT */ 20940efe139SSameer Pujar #define TEGRA234_CLK_PLLA_OUT0 104U 21038eb21a5SAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM1 */ 21138eb21a5SAkhil R #define TEGRA234_CLK_PWM1 105U 21238eb21a5SAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM2 */ 21338eb21a5SAkhil R #define TEGRA234_CLK_PWM2 106U 21438eb21a5SAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM3 */ 21538eb21a5SAkhil R #define TEGRA234_CLK_PWM3 107U 21638eb21a5SAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM4 */ 21738eb21a5SAkhil R #define TEGRA234_CLK_PWM4 108U 21838eb21a5SAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM5 */ 21938eb21a5SAkhil R #define TEGRA234_CLK_PWM5 109U 22038eb21a5SAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM6 */ 22138eb21a5SAkhil R #define TEGRA234_CLK_PWM6 110U 22238eb21a5SAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM7 */ 22338eb21a5SAkhil R #define TEGRA234_CLK_PWM7 111U 22438eb21a5SAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM8 */ 22538eb21a5SAkhil R #define TEGRA234_CLK_PWM8 112U 226*41155b6fSJon Hunter /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC output */ 227*41155b6fSJon Hunter #define TEGRA234_CLK_RCE_CPU_NIC 113U 228*41155b6fSJon Hunter /** @brief CLK_RST_CONTROLLER_RCE_NIC_RATE divider output */ 229*41155b6fSJon Hunter #define TEGRA234_CLK_RCE_NIC 114U 230*41155b6fSJon Hunter /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW switch divider output */ 231*41155b6fSJon Hunter #define TEGRA234_CLK_AON_I2C_SLOW 117U 232*41155b6fSJon Hunter /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC */ 233*41155b6fSJon Hunter #define TEGRA234_CLK_SCE_CPU_NIC 118U 234*41155b6fSJon Hunter /** @brief output of divider CLK_RST_CONTROLLER_SCE_NIC_RATE */ 235*41155b6fSJon Hunter #define TEGRA234_CLK_SCE_NIC 119U 236*41155b6fSJon Hunter /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1 */ 237*41155b6fSJon Hunter #define TEGRA234_CLK_SDMMC1 120U 238*41155b6fSJon Hunter /** @brief Logical clk for setting the UPHY PLL3 rate */ 239*41155b6fSJon Hunter #define TEGRA234_CLK_UPHY_PLL3 121U 24063944891SThierry Reding /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */ 241fc5e0e37SMikko Perttunen #define TEGRA234_CLK_SDMMC4 123U 242*41155b6fSJon Hunter /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SE switch divider gated output */ 243*41155b6fSJon Hunter #define TEGRA234_CLK_SE 124U 244*41155b6fSJon Hunter /** @brief VPLL select for sor0_ref clk driven by disp_2clk_sor0_head_sel signal */ 245*41155b6fSJon Hunter #define TEGRA234_CLK_SOR0_PLL_REF 125U 246*41155b6fSJon Hunter /** @brief Output of mux controlled by disp_2clk_sor0_pll_ref_clk_safe signal (sor0_ref_clk) */ 247*41155b6fSJon Hunter #define TEGRA234_CLK_SOR0_REF 126U 248*41155b6fSJon Hunter /** @brief VPLL select for sor1_ref clk driven by disp_2clk_sor0_head_sel signal */ 249*41155b6fSJon Hunter #define TEGRA234_CLK_SOR1_PLL_REF 127U 250*41155b6fSJon Hunter /** @brief SOR_PLL_REF_CLK_CTRL__0_DIV divider output */ 251*41155b6fSJon Hunter #define TEGRA234_CLK_PRE_SOR0_REF 128U 252*41155b6fSJon Hunter /** @brief Output of mux controlled by disp_2clk_sor1_pll_ref_clk_safe signal (sor1_ref_clk) */ 253*41155b6fSJon Hunter #define TEGRA234_CLK_SOR1_REF 129U 254*41155b6fSJon Hunter /** @brief SOR_PLL_REF_CLK_CTRL__1_DIV divider output */ 255*41155b6fSJon Hunter #define TEGRA234_CLK_PRE_SOR1_REF 130U 256*41155b6fSJon Hunter /** @brief output of gate CLK_ENB_SOR_SAFE */ 257*41155b6fSJon Hunter #define TEGRA234_CLK_SOR_SAFE 131U 258*41155b6fSJon Hunter /** @brief SOR_CLK_CTRL__0_DIV divider output */ 259*41155b6fSJon Hunter #define TEGRA234_CLK_SOR0_DIV 132U 260*41155b6fSJon Hunter /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5 */ 261*41155b6fSJon Hunter #define TEGRA234_CLK_DMIC5 134U 262*41155b6fSJon Hunter /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI1 */ 263*41155b6fSJon Hunter #define TEGRA234_CLK_SPI1 135U 264*41155b6fSJon Hunter /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI2 */ 265*41155b6fSJon Hunter #define TEGRA234_CLK_SPI2 136U 266*41155b6fSJon Hunter /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI3 */ 267*41155b6fSJon Hunter #define TEGRA234_CLK_SPI3 137U 268*41155b6fSJon Hunter /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW */ 269*41155b6fSJon Hunter #define TEGRA234_CLK_I2C_SLOW 138U 27040efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1 */ 27140efe139SSameer Pujar #define TEGRA234_CLK_SYNC_DMIC1 139U 27240efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2 */ 27340efe139SSameer Pujar #define TEGRA234_CLK_SYNC_DMIC2 140U 27440efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3 */ 27540efe139SSameer Pujar #define TEGRA234_CLK_SYNC_DMIC3 141U 27640efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4 */ 27740efe139SSameer Pujar #define TEGRA234_CLK_SYNC_DMIC4 142U 27840efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1 */ 27940efe139SSameer Pujar #define TEGRA234_CLK_SYNC_DSPK1 143U 28040efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2 */ 28140efe139SSameer Pujar #define TEGRA234_CLK_SYNC_DSPK2 144U 28240efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1 */ 28340efe139SSameer Pujar #define TEGRA234_CLK_SYNC_I2S1 145U 28440efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2 */ 28540efe139SSameer Pujar #define TEGRA234_CLK_SYNC_I2S2 146U 28640efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3 */ 28740efe139SSameer Pujar #define TEGRA234_CLK_SYNC_I2S3 147U 28840efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4 */ 28940efe139SSameer Pujar #define TEGRA234_CLK_SYNC_I2S4 148U 29040efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5 */ 29140efe139SSameer Pujar #define TEGRA234_CLK_SYNC_I2S5 149U 29240efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6 */ 29340efe139SSameer Pujar #define TEGRA234_CLK_SYNC_I2S6 150U 294*41155b6fSJon Hunter /** @brief controls MPHY_FORCE_LS_MODE upon enable & disable */ 295*41155b6fSJon Hunter #define TEGRA234_CLK_MPHY_FORCE_LS_MODE 151U 296*41155b6fSJon Hunter /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TACH0 */ 297*41155b6fSJon Hunter #define TEGRA234_CLK_TACH0 152U 298*41155b6fSJon Hunter /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSEC */ 299*41155b6fSJon Hunter #define TEGRA234_CLK_TSEC 153U 3000e2b014eSMikko Perttunen /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PKA */ 3010e2b014eSMikko Perttunen #define TEGRA234_CLK_TSEC_PKA 154U 30263944891SThierry Reding /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */ 303fc5e0e37SMikko Perttunen #define TEGRA234_CLK_UARTA 155U 304*41155b6fSJon Hunter /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTB */ 305*41155b6fSJon Hunter #define TEGRA234_CLK_UARTB 156U 306*41155b6fSJon Hunter /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTC */ 307*41155b6fSJon Hunter #define TEGRA234_CLK_UARTC 157U 308*41155b6fSJon Hunter /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTD */ 309*41155b6fSJon Hunter #define TEGRA234_CLK_UARTD 158U 310*41155b6fSJon Hunter /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTE */ 311*41155b6fSJon Hunter #define TEGRA234_CLK_UARTE 159U 312*41155b6fSJon Hunter /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTF */ 313*41155b6fSJon Hunter #define TEGRA234_CLK_UARTF 160U 314d06a171eSVidya Sagar /** @brief output of gate CLK_ENB_PEX1_CORE_6 */ 315d06a171eSVidya Sagar #define TEGRA234_CLK_PEX1_C6_CORE 161U 316*41155b6fSJon Hunter /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL */ 317*41155b6fSJon Hunter #define TEGRA234_CLK_UART_FST_MIPI_CAL 162U 318*41155b6fSJon Hunter /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF */ 319*41155b6fSJon Hunter #define TEGRA234_CLK_UFSDEV_REF 163U 320*41155b6fSJon Hunter /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS */ 321*41155b6fSJon Hunter #define TEGRA234_CLK_UFSHC 164U 322*41155b6fSJon Hunter /** @brief output of gate CLK_ENB_USB2_TRK */ 323*41155b6fSJon Hunter #define TEGRA234_CLK_USB2_TRK 165U 324*41155b6fSJon Hunter /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VI */ 325*41155b6fSJon Hunter #define TEGRA234_CLK_VI 166U 32663a6ef23SMikko Perttunen /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VIC */ 32763a6ef23SMikko Perttunen #define TEGRA234_CLK_VIC 167U 328*41155b6fSJon Hunter /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_CSITE switch divider output */ 329*41155b6fSJon Hunter #define TEGRA234_CLK_CSITE 168U 330*41155b6fSJon Hunter /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_IST switch divider output */ 331*41155b6fSJon Hunter #define TEGRA234_CLK_IST 169U 332*41155b6fSJon Hunter /** @brief output of mux controlled by CLK_RST_CONTROLLER_IST_JTAG_REG_CLK_SEL */ 333*41155b6fSJon Hunter #define TEGRA234_CLK_JTAG_INTFC_PRE_CG 170U 334d06a171eSVidya Sagar /** @brief output of gate CLK_ENB_PEX2_CORE_7 */ 335d06a171eSVidya Sagar #define TEGRA234_CLK_PEX2_C7_CORE 171U 336d06a171eSVidya Sagar /** @brief output of gate CLK_ENB_PEX2_CORE_8 */ 337d06a171eSVidya Sagar #define TEGRA234_CLK_PEX2_C8_CORE 172U 338d06a171eSVidya Sagar /** @brief output of gate CLK_ENB_PEX2_CORE_9 */ 339d06a171eSVidya Sagar #define TEGRA234_CLK_PEX2_C9_CORE 173U 340*41155b6fSJon Hunter /** @brief dla0_falcon_clk */ 341*41155b6fSJon Hunter #define TEGRA234_CLK_DLA0_FALCON 174U 342*41155b6fSJon Hunter /** @brief dla0_core_clk */ 343*41155b6fSJon Hunter #define TEGRA234_CLK_DLA0_CORE 175U 344*41155b6fSJon Hunter /** @brief dla1_falcon_clk */ 345*41155b6fSJon Hunter #define TEGRA234_CLK_DLA1_FALCON 176U 346*41155b6fSJon Hunter /** @brief dla1_core_clk */ 347*41155b6fSJon Hunter #define TEGRA234_CLK_DLA1_CORE 177U 348*41155b6fSJon Hunter /** @brief Output of mux controlled by disp_2clk_sor0_clk_safe signal (sor0_clk) */ 349*41155b6fSJon Hunter #define TEGRA234_CLK_SOR0 178U 350*41155b6fSJon Hunter /** @brief Output of mux controlled by disp_2clk_sor1_clk_safe signal (sor1_clk) */ 351*41155b6fSJon Hunter #define TEGRA234_CLK_SOR1 179U 352*41155b6fSJon Hunter /** @brief DP macro feedback clock (same as LINKA_SYM CLKOUT) */ 353*41155b6fSJon Hunter #define TEGRA234_CLK_SOR_PAD_INPUT 180U 354*41155b6fSJon Hunter /** @brief Output of mux controlled by disp_2clk_h0_dsi_sel signal in sf0_clk path */ 355*41155b6fSJon Hunter #define TEGRA234_CLK_PRE_SF0 181U 356*41155b6fSJon Hunter /** @brief Output of mux controlled by disp_2clk_sf0_clk_safe signal (sf0_clk) */ 357*41155b6fSJon Hunter #define TEGRA234_CLK_SF0 182U 358*41155b6fSJon Hunter /** @brief Output of mux controlled by disp_2clk_sf1_clk_safe signal (sf1_clk) */ 359*41155b6fSJon Hunter #define TEGRA234_CLK_SF1 183U 360*41155b6fSJon Hunter /** @brief CLKOUT_AB output from DSI BRICK A (dsi_clkout_ab) */ 361*41155b6fSJon Hunter #define TEGRA234_CLK_DSI_PAD_INPUT 184U 362d06a171eSVidya Sagar /** @brief output of gate CLK_ENB_PEX2_CORE_10 */ 363d06a171eSVidya Sagar #define TEGRA234_CLK_PEX2_C10_CORE 187U 364*41155b6fSJon Hunter /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_UARTI switch divider output (uarti_r_clk) */ 365*41155b6fSJon Hunter #define TEGRA234_CLK_UARTI 188U 366*41155b6fSJon Hunter /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_UARTJ switch divider output (uartj_r_clk) */ 367*41155b6fSJon Hunter #define TEGRA234_CLK_UARTJ 189U 368*41155b6fSJon Hunter /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_UARTH switch divider output */ 369*41155b6fSJon Hunter #define TEGRA234_CLK_UARTH 190U 370*41155b6fSJon Hunter /** @brief ungated version of fuse clk */ 371*41155b6fSJon Hunter #define TEGRA234_CLK_FUSE_SERIAL 191U 372*41155b6fSJon Hunter /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0 switch divider output (qspi0_2x_pm_clk) */ 37371f69ffaSAshish Singhal #define TEGRA234_CLK_QSPI0_2X_PM 192U 374*41155b6fSJon Hunter /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1 switch divider output (qspi1_2x_pm_clk) */ 37571f69ffaSAshish Singhal #define TEGRA234_CLK_QSPI1_2X_PM 193U 376*41155b6fSJon Hunter /** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0 (qspi0_pm_clk) */ 37771f69ffaSAshish Singhal #define TEGRA234_CLK_QSPI0_PM 194U 378*41155b6fSJon Hunter /** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1 (qspi1_pm_clk) */ 37971f69ffaSAshish Singhal #define TEGRA234_CLK_QSPI1_PM 195U 380*41155b6fSJon Hunter /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_VI_CONST switch divider output */ 381*41155b6fSJon Hunter #define TEGRA234_CLK_VI_CONST 196U 382*41155b6fSJon Hunter /** @brief NAFLL clock source for BPMP */ 383*41155b6fSJon Hunter #define TEGRA234_CLK_NAFLL_BPMP 197U 384*41155b6fSJon Hunter /** @brief NAFLL clock source for SCE */ 385*41155b6fSJon Hunter #define TEGRA234_CLK_NAFLL_SCE 198U 386*41155b6fSJon Hunter /** @brief NAFLL clock source for NVDEC */ 387*41155b6fSJon Hunter #define TEGRA234_CLK_NAFLL_NVDEC 199U 388*41155b6fSJon Hunter /** @brief NAFLL clock source for NVJPG */ 389*41155b6fSJon Hunter #define TEGRA234_CLK_NAFLL_NVJPG 200U 390*41155b6fSJon Hunter /** @brief NAFLL clock source for TSEC */ 391*41155b6fSJon Hunter #define TEGRA234_CLK_NAFLL_TSEC 201U 392*41155b6fSJon Hunter /** @brief NAFLL clock source for VI */ 393*41155b6fSJon Hunter #define TEGRA234_CLK_NAFLL_VI 203U 394*41155b6fSJon Hunter /** @brief NAFLL clock source for SE */ 395*41155b6fSJon Hunter #define TEGRA234_CLK_NAFLL_SE 204U 396*41155b6fSJon Hunter /** @brief NAFLL clock source for NVENC */ 397*41155b6fSJon Hunter #define TEGRA234_CLK_NAFLL_NVENC 205U 398*41155b6fSJon Hunter /** @brief NAFLL clock source for ISP */ 399*41155b6fSJon Hunter #define TEGRA234_CLK_NAFLL_ISP 206U 400*41155b6fSJon Hunter /** @brief NAFLL clock source for VIC */ 401*41155b6fSJon Hunter #define TEGRA234_CLK_NAFLL_VIC 207U 402*41155b6fSJon Hunter /** @brief NAFLL clock source for AXICBB */ 403*41155b6fSJon Hunter #define TEGRA234_CLK_NAFLL_AXICBB 209U 404*41155b6fSJon Hunter /** @brief NAFLL clock source for NVJPG1 */ 405*41155b6fSJon Hunter #define TEGRA234_CLK_NAFLL_NVJPG1 210U 406*41155b6fSJon Hunter /** @brief NAFLL clock source for PVA core */ 407*41155b6fSJon Hunter #define TEGRA234_CLK_NAFLL_PVA0_CORE 211U 408*41155b6fSJon Hunter /** @brief NAFLL clock source for PVA VPS */ 409*41155b6fSJon Hunter #define TEGRA234_CLK_NAFLL_PVA0_VPS 212U 410*41155b6fSJon Hunter /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0 switch divider output (dbgapb_clk) */ 411*41155b6fSJon Hunter #define TEGRA234_CLK_DBGAPB 213U 412*41155b6fSJon Hunter /** @brief NAFLL clock source for RCE */ 413*41155b6fSJon Hunter #define TEGRA234_CLK_NAFLL_RCE 214U 414*41155b6fSJon Hunter /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_LA switch divider output (la_r_clk) */ 415*41155b6fSJon Hunter #define TEGRA234_CLK_LA 215U 416*41155b6fSJon Hunter /** @brief output of the divider CLK_RST_CONTROLLER_PLLP_OUTD */ 417*41155b6fSJon Hunter #define TEGRA234_CLK_PLLP_OUT_JTAG 216U 418*41155b6fSJon Hunter /** @brief AXI_CBB branch sharing gate control with SDMMC4 */ 419*41155b6fSJon Hunter #define TEGRA234_CLK_SDMMC4_AXICIF 217U 420fc5e0e37SMikko Perttunen /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM switch divider output */ 421fc5e0e37SMikko Perttunen #define TEGRA234_CLK_SDMMC_LEGACY_TM 219U 422d06a171eSVidya Sagar /** @brief output of gate CLK_ENB_PEX0_CORE_0 */ 423d06a171eSVidya Sagar #define TEGRA234_CLK_PEX0_C0_CORE 220U 424d06a171eSVidya Sagar /** @brief output of gate CLK_ENB_PEX0_CORE_1 */ 425d06a171eSVidya Sagar #define TEGRA234_CLK_PEX0_C1_CORE 221U 426d06a171eSVidya Sagar /** @brief output of gate CLK_ENB_PEX0_CORE_2 */ 427d06a171eSVidya Sagar #define TEGRA234_CLK_PEX0_C2_CORE 222U 428d06a171eSVidya Sagar /** @brief output of gate CLK_ENB_PEX0_CORE_3 */ 429d06a171eSVidya Sagar #define TEGRA234_CLK_PEX0_C3_CORE 223U 430d06a171eSVidya Sagar /** @brief output of gate CLK_ENB_PEX0_CORE_4 */ 431d06a171eSVidya Sagar #define TEGRA234_CLK_PEX0_C4_CORE 224U 432d06a171eSVidya Sagar /** @brief output of gate CLK_ENB_PEX1_CORE_5 */ 433d06a171eSVidya Sagar #define TEGRA234_CLK_PEX1_C5_CORE 225U 434*41155b6fSJon Hunter /** @brief Monitored branch of PEX0_C0_CORE clock */ 435*41155b6fSJon Hunter #define TEGRA234_CLK_PEX0_C0_CORE_M 229U 436*41155b6fSJon Hunter /** @brief Monitored branch of PEX0_C1_CORE clock */ 437*41155b6fSJon Hunter #define TEGRA234_CLK_PEX0_C1_CORE_M 230U 438*41155b6fSJon Hunter /** @brief Monitored branch of PEX0_C2_CORE clock */ 439*41155b6fSJon Hunter #define TEGRA234_CLK_PEX0_C2_CORE_M 231U 440*41155b6fSJon Hunter /** @brief Monitored branch of PEX0_C3_CORE clock */ 441*41155b6fSJon Hunter #define TEGRA234_CLK_PEX0_C3_CORE_M 232U 442*41155b6fSJon Hunter /** @brief Monitored branch of PEX0_C4_CORE clock */ 443*41155b6fSJon Hunter #define TEGRA234_CLK_PEX0_C4_CORE_M 233U 444*41155b6fSJon Hunter /** @brief Monitored branch of PEX1_C5_CORE clock */ 445*41155b6fSJon Hunter #define TEGRA234_CLK_PEX1_C5_CORE_M 234U 446*41155b6fSJon Hunter /** @brief Monitored branch of PEX1_C6_CORE clock */ 447*41155b6fSJon Hunter #define TEGRA234_CLK_PEX1_C6_CORE_M 235U 448*41155b6fSJon Hunter /** @brief output of GPU GPC1 clkGen (in 1x mode same rate as GPC1 MUX2 out) */ 449*41155b6fSJon Hunter #define TEGRA234_CLK_GPC1CLK 236U 450fc5e0e37SMikko Perttunen /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */ 451fc5e0e37SMikko Perttunen #define TEGRA234_CLK_PLLC4 237U 452*41155b6fSJon Hunter /** @brief PLLC4 VCO followed by DIV3 path */ 453*41155b6fSJon Hunter #define TEGRA234_CLK_PLLC4_OUT1 239U 454*41155b6fSJon Hunter /** @brief PLLC4 VCO followed by DIV5 path */ 455*41155b6fSJon Hunter #define TEGRA234_CLK_PLLC4_OUT2 240U 456*41155b6fSJon Hunter /** @brief output of the mux controlled by PLLC4_CLK_SEL */ 457*41155b6fSJon Hunter #define TEGRA234_CLK_PLLC4_MUXED 241U 458*41155b6fSJon Hunter /** @brief PLLC4 VCO followed by DIV2 path */ 459*41155b6fSJon Hunter #define TEGRA234_CLK_PLLC4_VCO_DIV2 242U 460*41155b6fSJon Hunter /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLNVHS_BASE */ 461*41155b6fSJon Hunter #define TEGRA234_CLK_PLLNVHS 243U 462*41155b6fSJon Hunter /** @brief Monitored branch of PEX2_C7_CORE clock */ 463*41155b6fSJon Hunter #define TEGRA234_CLK_PEX2_C7_CORE_M 244U 464*41155b6fSJon Hunter /** @brief Monitored branch of PEX2_C8_CORE clock */ 465*41155b6fSJon Hunter #define TEGRA234_CLK_PEX2_C8_CORE_M 245U 466*41155b6fSJon Hunter /** @brief Monitored branch of PEX2_C9_CORE clock */ 467*41155b6fSJon Hunter #define TEGRA234_CLK_PEX2_C9_CORE_M 246U 468*41155b6fSJon Hunter /** @brief Monitored branch of PEX2_C10_CORE clock */ 469*41155b6fSJon Hunter #define TEGRA234_CLK_PEX2_C10_CORE_M 247U 470b0aedf34SThierry Reding /** @brief RX clock recovered from MGBE0 lane input */ 471b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE0_RX_INPUT 248U 472b0aedf34SThierry Reding /** @brief RX clock recovered from MGBE1 lane input */ 473b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE1_RX_INPUT 249U 474b0aedf34SThierry Reding /** @brief RX clock recovered from MGBE2 lane input */ 475b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE2_RX_INPUT 250U 476b0aedf34SThierry Reding /** @brief RX clock recovered from MGBE3 lane input */ 477b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE3_RX_INPUT 251U 478*41155b6fSJon Hunter /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP switch divider output */ 479*41155b6fSJon Hunter #define TEGRA234_CLK_PEX_SATA_USB_RX_BYP 254U 480*41155b6fSJon Hunter /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT switch divider output */ 481*41155b6fSJon Hunter #define TEGRA234_CLK_PEX_USB_PAD_PLL0_MGMT 255U 482*41155b6fSJon Hunter /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT switch divider output */ 483*41155b6fSJon Hunter #define TEGRA234_CLK_PEX_USB_PAD_PLL1_MGMT 256U 484*41155b6fSJon Hunter /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL2_MGMT switch divider output */ 485*41155b6fSJon Hunter #define TEGRA234_CLK_PEX_USB_PAD_PLL2_MGMT 257U 486*41155b6fSJon Hunter /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL3_MGMT switch divider output */ 487*41155b6fSJon Hunter #define TEGRA234_CLK_PEX_USB_PAD_PLL3_MGMT 258U 488*41155b6fSJon Hunter /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_RX_BYP switch divider output */ 489*41155b6fSJon Hunter #define TEGRA234_CLK_NVHS_RX_BYP_REF 263U 490*41155b6fSJon Hunter /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_PLL0_MGMT switch divider output */ 491*41155b6fSJon Hunter #define TEGRA234_CLK_NVHS_PLL0_MGMT 264U 492*41155b6fSJon Hunter /** @brief xusb_core_dev_clk */ 493*41155b6fSJon Hunter #define TEGRA234_CLK_XUSB_CORE_DEV 265U 494*41155b6fSJon Hunter /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST switch divider output */ 495*41155b6fSJon Hunter #define TEGRA234_CLK_XUSB_CORE_MUX 266U 496*41155b6fSJon Hunter /** @brief xusb_core_host_clk */ 497*41155b6fSJon Hunter #define TEGRA234_CLK_XUSB_CORE_HOST 267U 498*41155b6fSJon Hunter /** @brief xusb_core_superspeed_clk */ 499*41155b6fSJon Hunter #define TEGRA234_CLK_XUSB_CORE_SS 268U 500*41155b6fSJon Hunter /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON switch divider output */ 501*41155b6fSJon Hunter #define TEGRA234_CLK_XUSB_FALCON 269U 502*41155b6fSJon Hunter /** @brief xusb_falcon_host_clk */ 503*41155b6fSJon Hunter #define TEGRA234_CLK_XUSB_FALCON_HOST 270U 504*41155b6fSJon Hunter /** @brief xusb_falcon_superspeed_clk */ 505*41155b6fSJon Hunter #define TEGRA234_CLK_XUSB_FALCON_SS 271U 506*41155b6fSJon Hunter /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS switch divider output */ 507*41155b6fSJon Hunter #define TEGRA234_CLK_XUSB_FS 272U 508*41155b6fSJon Hunter /** @brief xusb_fs_host_clk */ 509*41155b6fSJon Hunter #define TEGRA234_CLK_XUSB_FS_HOST 273U 510*41155b6fSJon Hunter /** @brief xusb_fs_dev_clk */ 511*41155b6fSJon Hunter #define TEGRA234_CLK_XUSB_FS_DEV 274U 512*41155b6fSJon Hunter /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS switch divider output */ 513*41155b6fSJon Hunter #define TEGRA234_CLK_XUSB_SS 275U 514*41155b6fSJon Hunter /** @brief xusb_ss_dev_clk */ 515*41155b6fSJon Hunter #define TEGRA234_CLK_XUSB_SS_DEV 276U 516*41155b6fSJon Hunter /** @brief xusb_ss_superspeed_clk */ 517*41155b6fSJon Hunter #define TEGRA234_CLK_XUSB_SS_SUPERSPEED 277U 518*41155b6fSJon Hunter /** @brief NAFLL clock source for CPU cluster 0 */ 519*41155b6fSJon Hunter #define TEGRA234_CLK_NAFLL_CLUSTER0 280U /* TODO: remove */ 520*41155b6fSJon Hunter #define TEGRA234_CLK_NAFLL_CLUSTER0_CORE 280U 521*41155b6fSJon Hunter /** @brief NAFLL clock source for CPU cluster 1 */ 522*41155b6fSJon Hunter #define TEGRA234_CLK_NAFLL_CLUSTER1 281U /* TODO: remove */ 523*41155b6fSJon Hunter #define TEGRA234_CLK_NAFLL_CLUSTER1_CORE 281U 524*41155b6fSJon Hunter /** @brief NAFLL clock source for CPU cluster 2 */ 525*41155b6fSJon Hunter #define TEGRA234_CLK_NAFLL_CLUSTER2 282U /* TODO: remove */ 526*41155b6fSJon Hunter #define TEGRA234_CLK_NAFLL_CLUSTER2_CORE 282U 527*41155b6fSJon Hunter /** @brief CLK_RST_CONTROLLER_CAN1_CORE_RATE divider output */ 528*41155b6fSJon Hunter #define TEGRA234_CLK_CAN1_CORE 284U 529*41155b6fSJon Hunter /** @brief CLK_RST_CONTROLLER_CAN2_CORE_RATE divider outputt */ 530*41155b6fSJon Hunter #define TEGRA234_CLK_CAN2_CORE 285U 531*41155b6fSJon Hunter /** @brief CLK_RST_CONTROLLER_PLLA1_OUT1 switch divider output */ 532*41155b6fSJon Hunter #define TEGRA234_CLK_PLLA1_OUT1 286U 533*41155b6fSJon Hunter /** @brief NVHS PLL hardware power sequencer (overrides 'manual' programming of PLL) */ 534*41155b6fSJon Hunter #define TEGRA234_CLK_PLLNVHS_HPS 287U 535*41155b6fSJon Hunter /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLREFE_BASE */ 536*41155b6fSJon Hunter #define TEGRA234_CLK_PLLREFE_VCOOUT 288U 537fc5e0e37SMikko Perttunen /** @brief 32K input clock provided by PMIC */ 538fc5e0e37SMikko Perttunen #define TEGRA234_CLK_CLK_32K 289U 539*41155b6fSJon Hunter /** @brief Fixed 48MHz clock divided down from utmipll */ 540*41155b6fSJon Hunter #define TEGRA234_CLK_UTMIPLL_CLKOUT48 291U 541*41155b6fSJon Hunter /** @brief Fixed 480MHz clock divided down from utmipll */ 542*41155b6fSJon Hunter #define TEGRA234_CLK_UTMIPLL_CLKOUT480 292U 543*41155b6fSJon Hunter /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLNVCSI_BASE */ 544*41155b6fSJon Hunter #define TEGRA234_CLK_PLLNVCSI 294U 545*41155b6fSJon Hunter /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_CPU_AXI switch divider output */ 546*41155b6fSJon Hunter #define TEGRA234_CLK_PVA0_CPU_AXI 295U 547*41155b6fSJon Hunter /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_VPS switch divider output */ 548*41155b6fSJon Hunter #define TEGRA234_CLK_PVA0_VPS 297U 549*41155b6fSJon Hunter /** @brief DLA0_CORE_NAFLL */ 550*41155b6fSJon Hunter #define TEGRA234_CLK_NAFLL_DLA0_CORE 299U 551*41155b6fSJon Hunter /** @brief DLA0_FALCON_NAFLL */ 552*41155b6fSJon Hunter #define TEGRA234_CLK_NAFLL_DLA0_FALCON 300U 553*41155b6fSJon Hunter /** @brief DLA1_CORE_NAFLL */ 554*41155b6fSJon Hunter #define TEGRA234_CLK_NAFLL_DLA1_CORE 301U 555*41155b6fSJon Hunter /** @brief DLA1_FALCON_NAFLL */ 556*41155b6fSJon Hunter #define TEGRA234_CLK_NAFLL_DLA1_FALCON 302U 557*41155b6fSJon Hunter /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL */ 558*41155b6fSJon Hunter #define TEGRA234_CLK_AON_UART_FST_MIPI_CAL 303U 559*41155b6fSJon Hunter /** @brief GPU system clock */ 560*41155b6fSJon Hunter #define TEGRA234_CLK_GPUSYS 304U 561*41155b6fSJon Hunter /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C5 */ 562*41155b6fSJon Hunter #define TEGRA234_CLK_I2C5 305U 563*41155b6fSJon Hunter /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SE switch divider free running clk */ 564*41155b6fSJon Hunter #define TEGRA234_CLK_FR_SE 306U 565*41155b6fSJon Hunter /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC switch divider output */ 566*41155b6fSJon Hunter #define TEGRA234_CLK_BPMP_CPU_NIC 307U 567*41155b6fSJon Hunter /** @brief output of gate CLK_ENB_BPMP_CPU */ 568*41155b6fSJon Hunter #define TEGRA234_CLK_BPMP_CPU 308U 569*41155b6fSJon Hunter /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_TSC switch divider output */ 570*41155b6fSJon Hunter #define TEGRA234_CLK_TSC 309U 571*41155b6fSJon Hunter /** @brief output of mem pll A sync mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EMC */ 572*41155b6fSJon Hunter #define TEGRA234_CLK_EMCSA_MPLL 310U 573*41155b6fSJon Hunter /** @brief output of mem pll B sync mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB */ 574*41155b6fSJon Hunter #define TEGRA234_CLK_EMCSB_MPLL 311U 575*41155b6fSJon Hunter /** @brief output of mem pll C sync mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC */ 576*41155b6fSJon Hunter #define TEGRA234_CLK_EMCSC_MPLL 312U 577*41155b6fSJon Hunter /** @brief output of mem pll D sync mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD */ 578*41155b6fSJon Hunter #define TEGRA234_CLK_EMCSD_MPLL 313U 579*41155b6fSJon Hunter /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC_BASE */ 580*41155b6fSJon Hunter #define TEGRA234_CLK_PLLC 314U 581*41155b6fSJon Hunter /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC2_BASE */ 582*41155b6fSJon Hunter #define TEGRA234_CLK_PLLC2 315U 583*41155b6fSJon Hunter /** @brief CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER skip divider output */ 584*41155b6fSJon Hunter #define TEGRA234_CLK_TSC_REF 317U 585*41155b6fSJon Hunter /** @brief Dummy clock to ensure minimum SoC voltage for fuse burning */ 586*41155b6fSJon Hunter #define TEGRA234_CLK_FUSE_BURN 318U 587*41155b6fSJon Hunter /** @brief GBE PLL */ 588*41155b6fSJon Hunter #define TEGRA234_CLK_PLLGBE 319U 589*41155b6fSJon Hunter /** @brief GBE PLL hardware power sequencer */ 590*41155b6fSJon Hunter #define TEGRA234_CLK_PLLGBE_HPS 320U 591*41155b6fSJon Hunter /** @brief output of EMC CDB side A fixed (DIV4) divider */ 592*41155b6fSJon Hunter #define TEGRA234_CLK_EMCSA_EMC 321U 593*41155b6fSJon Hunter /** @brief output of EMC CDB side B fixed (DIV4) divider */ 594*41155b6fSJon Hunter #define TEGRA234_CLK_EMCSB_EMC 322U 595*41155b6fSJon Hunter /** @brief output of EMC CDB side C fixed (DIV4) divider */ 596*41155b6fSJon Hunter #define TEGRA234_CLK_EMCSC_EMC 323U 597*41155b6fSJon Hunter /** @brief output of EMC CDB side D fixed (DIV4) divider */ 598*41155b6fSJon Hunter #define TEGRA234_CLK_EMCSD_EMC 324U 599*41155b6fSJon Hunter /** @brief PLLE hardware power sequencer (overrides 'manual' programming of PLL) */ 600*41155b6fSJon Hunter #define TEGRA234_CLK_PLLE_HPS 326U 601*41155b6fSJon Hunter /** @brief CLK_ENB_PLLREFE_OUT gate output */ 602*41155b6fSJon Hunter #define TEGRA234_CLK_PLLREFE_VCOOUT_GATED 327U 603*41155b6fSJon Hunter /** @brief TEGRA234_CLK_SOR_SAFE clk source (PLLP_OUT0 divided by 17) */ 604*41155b6fSJon Hunter #define TEGRA234_CLK_PLLP_DIV17 328U 605*41155b6fSJon Hunter /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM switch divider output */ 606*41155b6fSJon Hunter #define TEGRA234_CLK_SOC_THERM 329U 607*41155b6fSJon Hunter /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_TSENSE switch divider output */ 608*41155b6fSJon Hunter #define TEGRA234_CLK_TSENSE 330U 609*41155b6fSJon Hunter /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SEU1 switch divider free running clk */ 610*41155b6fSJon Hunter #define TEGRA234_CLK_FR_SEU1 331U 611*41155b6fSJon Hunter /** @brief NAFLL clock source for OFA */ 612*41155b6fSJon Hunter #define TEGRA234_CLK_NAFLL_OFA 333U 613*41155b6fSJon Hunter /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_OFA switch divider output */ 614*41155b6fSJon Hunter #define TEGRA234_CLK_OFA 334U 615*41155b6fSJon Hunter /** @brief NAFLL clock source for SEU1 */ 616*41155b6fSJon Hunter #define TEGRA234_CLK_NAFLL_SEU1 335U 617*41155b6fSJon Hunter /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SEU1 switch divider gated output */ 618*41155b6fSJon Hunter #define TEGRA234_CLK_SEU1 336U 619*41155b6fSJon Hunter /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI4 */ 620*41155b6fSJon Hunter #define TEGRA234_CLK_SPI4 337U 621*41155b6fSJon Hunter /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI5 */ 622*41155b6fSJon Hunter #define TEGRA234_CLK_SPI5 338U 623*41155b6fSJon Hunter /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DCE_CPU_NIC */ 624*41155b6fSJon Hunter #define TEGRA234_CLK_DCE_CPU_NIC 339U 625*41155b6fSJon Hunter /** @brief output of divider CLK_RST_CONTROLLER_DCE_NIC_RATE */ 626*41155b6fSJon Hunter #define TEGRA234_CLK_DCE_NIC 340U 627*41155b6fSJon Hunter /** @brief NAFLL clock source for DCE */ 628*41155b6fSJon Hunter #define TEGRA234_CLK_NAFLL_DCE 341U 629*41155b6fSJon Hunter /** @brief Monitored branch of MPHY_L0_RX_ANA clock */ 630*41155b6fSJon Hunter #define TEGRA234_CLK_MPHY_L0_RX_ANA_M 342U 631*41155b6fSJon Hunter /** @brief Monitored branch of MPHY_L1_RX_ANA clock */ 632*41155b6fSJon Hunter #define TEGRA234_CLK_MPHY_L1_RX_ANA_M 343U 633*41155b6fSJon Hunter /** @brief ungated version of TX symbol clock after fixed 1/2 divider */ 634*41155b6fSJon Hunter #define TEGRA234_CLK_MPHY_L0_TX_PRE_SYMB 344U 635*41155b6fSJon Hunter /** @brief output of divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB */ 636*41155b6fSJon Hunter #define TEGRA234_CLK_MPHY_L0_TX_LS_SYMB_DIV 345U 637*41155b6fSJon Hunter /** @brief output of gate CLK_ENB_MPHY_L0_TX_2X_SYMB */ 638*41155b6fSJon Hunter #define TEGRA234_CLK_MPHY_L0_TX_2X_SYMB 346U 639*41155b6fSJon Hunter /** @brief output of SW_MPHY_L0_TX_HS_SYMB divider in CLK_RST_CONTROLLER_MPHY_L0_TX_CLK_CTRL_0 */ 640*41155b6fSJon Hunter #define TEGRA234_CLK_MPHY_L0_TX_HS_SYMB_DIV 347U 641*41155b6fSJon Hunter /** @brief output of SW_MPHY_L0_TX_LS_3XBIT divider in CLK_RST_CONTROLLER_MPHY_L0_TX_CLK_CTRL_0 */ 642*41155b6fSJon Hunter #define TEGRA234_CLK_MPHY_L0_TX_LS_3XBIT_DIV 348U 643*41155b6fSJon Hunter /** @brief LS/HS divider mux SW_MPHY_L0_TX_LS_HS_SEL in CLK_RST_CONTROLLER_MPHY_L0_TX_CLK_CTRL_0 */ 644*41155b6fSJon Hunter #define TEGRA234_CLK_MPHY_L0_TX_MUX_SYMB_DIV 349U 645*41155b6fSJon Hunter /** @brief Monitored branch of MPHY_L0_TX_SYMB clock */ 646*41155b6fSJon Hunter #define TEGRA234_CLK_MPHY_L0_TX_SYMB_M 350U 647*41155b6fSJon Hunter /** @brief output of divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB */ 648*41155b6fSJon Hunter #define TEGRA234_CLK_MPHY_L0_RX_LS_SYMB_DIV 351U 649*41155b6fSJon Hunter /** @brief output of SW_MPHY_L0_RX_HS_SYMB divider in CLK_RST_CONTROLLER_MPHY_L0_RX_CLK_CTRL_0 */ 650*41155b6fSJon Hunter #define TEGRA234_CLK_MPHY_L0_RX_HS_SYMB_DIV 352U 651*41155b6fSJon Hunter /** @brief output of SW_MPHY_L0_RX_LS_BIT divider in CLK_RST_CONTROLLER_MPHY_L0_RX_CLK_CTRL_0 */ 652*41155b6fSJon Hunter #define TEGRA234_CLK_MPHY_L0_RX_LS_BIT_DIV 353U 653*41155b6fSJon Hunter /** @brief LS/HS divider mux SW_MPHY_L0_RX_LS_HS_SEL in CLK_RST_CONTROLLER_MPHY_L0_RX_CLK_CTRL_0 */ 654*41155b6fSJon Hunter #define TEGRA234_CLK_MPHY_L0_RX_MUX_SYMB_DIV 354U 655*41155b6fSJon Hunter /** @brief Monitored branch of MPHY_L0_RX_SYMB clock */ 656*41155b6fSJon Hunter #define TEGRA234_CLK_MPHY_L0_RX_SYMB_M 355U 657b0aedf34SThierry Reding /** @brief Monitored branch of MBGE0 RX input clock */ 658b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE0_RX_INPUT_M 357U 659b0aedf34SThierry Reding /** @brief Monitored branch of MBGE1 RX input clock */ 660b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE1_RX_INPUT_M 358U 661b0aedf34SThierry Reding /** @brief Monitored branch of MBGE2 RX input clock */ 662b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE2_RX_INPUT_M 359U 663b0aedf34SThierry Reding /** @brief Monitored branch of MBGE3 RX input clock */ 664b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE3_RX_INPUT_M 360U 665b0aedf34SThierry Reding /** @brief Monitored branch of MGBE0 RX PCS mux output */ 666b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE0_RX_PCS_M 361U 667b0aedf34SThierry Reding /** @brief Monitored branch of MGBE1 RX PCS mux output */ 668b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE1_RX_PCS_M 362U 669b0aedf34SThierry Reding /** @brief Monitored branch of MGBE2 RX PCS mux output */ 670b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE2_RX_PCS_M 363U 671b0aedf34SThierry Reding /** @brief Monitored branch of MGBE3 RX PCS mux output */ 672b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE3_RX_PCS_M 364U 673*41155b6fSJon Hunter /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TACH1 */ 674*41155b6fSJon Hunter #define TEGRA234_CLK_TACH1 365U 675*41155b6fSJon Hunter /** @brief GBE_UPHY_MGBES_APP_CLK switch divider gated output */ 676*41155b6fSJon Hunter #define TEGRA234_CLK_MGBES_APP 366U 677*41155b6fSJon Hunter /** @brief Logical clk for setting GBE UPHY PLL2 TX_REF rate */ 678*41155b6fSJon Hunter #define TEGRA234_CLK_UPHY_GBE_PLL2_TX_REF 367U 679*41155b6fSJon Hunter /** @brief Logical clk for setting GBE UPHY PLL2 XDIG rate */ 680*41155b6fSJon Hunter #define TEGRA234_CLK_UPHY_GBE_PLL2_XDIG 368U 681b0aedf34SThierry Reding /** @brief RX PCS clock recovered from MGBE0 lane input */ 682b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE0_RX_PCS_INPUT 369U 683b0aedf34SThierry Reding /** @brief RX PCS clock recovered from MGBE1 lane input */ 684b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE1_RX_PCS_INPUT 370U 685b0aedf34SThierry Reding /** @brief RX PCS clock recovered from MGBE2 lane input */ 686b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE2_RX_PCS_INPUT 371U 687b0aedf34SThierry Reding /** @brief RX PCS clock recovered from MGBE3 lane input */ 688b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE3_RX_PCS_INPUT 372U 689b0aedf34SThierry Reding /** @brief output of mux controlled by GBE_UPHY_MGBE0_RX_PCS_CLK_SRC_SEL */ 690b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE0_RX_PCS 373U 691b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE0_TX_CLK divider gated output */ 692b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE0_TX 374U 693b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE0_TX_PCS_CLK divider gated output */ 694b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE0_TX_PCS 375U 695b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE0_MAC_CLK divider output */ 696b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE0_MAC_DIVIDER 376U 697b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE0_MAC_CLK gate output */ 698b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE0_MAC 377U 699b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE0_MACSEC_CLK gate output */ 700b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE0_MACSEC 378U 701b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE0_EEE_PCS_CLK gate output */ 702b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE0_EEE_PCS 379U 703b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE0_APP_CLK gate output */ 704b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE0_APP 380U 705b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE0_PTP_REF_CLK divider gated output */ 706b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE0_PTP_REF 381U 707b0aedf34SThierry Reding /** @brief output of mux controlled by GBE_UPHY_MGBE1_RX_PCS_CLK_SRC_SEL */ 708b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE1_RX_PCS 382U 709b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE1_TX_CLK divider gated output */ 710b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE1_TX 383U 711b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE1_TX_PCS_CLK divider gated output */ 712b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE1_TX_PCS 384U 713b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE1_MAC_CLK divider output */ 714b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE1_MAC_DIVIDER 385U 715b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE1_MAC_CLK gate output */ 716b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE1_MAC 386U 717*41155b6fSJon Hunter /** @brief GBE_UPHY_MGBE1_MACSEC_CLK gate output */ 718*41155b6fSJon Hunter #define TEGRA234_CLK_MGBE1_MACSEC 387U 719b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE1_EEE_PCS_CLK gate output */ 720b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE1_EEE_PCS 388U 721b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE1_APP_CLK gate output */ 722b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE1_APP 389U 723b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE1_PTP_REF_CLK divider gated output */ 724b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE1_PTP_REF 390U 725b0aedf34SThierry Reding /** @brief output of mux controlled by GBE_UPHY_MGBE2_RX_PCS_CLK_SRC_SEL */ 726b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE2_RX_PCS 391U 727b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE2_TX_CLK divider gated output */ 728b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE2_TX 392U 729b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE2_TX_PCS_CLK divider gated output */ 730b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE2_TX_PCS 393U 731b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE2_MAC_CLK divider output */ 732b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE2_MAC_DIVIDER 394U 733b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE2_MAC_CLK gate output */ 734b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE2_MAC 395U 735*41155b6fSJon Hunter /** @brief GBE_UPHY_MGBE2_MACSEC_CLK gate output */ 736*41155b6fSJon Hunter #define TEGRA234_CLK_MGBE2_MACSEC 396U 737b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE2_EEE_PCS_CLK gate output */ 738b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE2_EEE_PCS 397U 739b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE2_APP_CLK gate output */ 740b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE2_APP 398U 741b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE2_PTP_REF_CLK divider gated output */ 742b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE2_PTP_REF 399U 743b0aedf34SThierry Reding /** @brief output of mux controlled by GBE_UPHY_MGBE3_RX_PCS_CLK_SRC_SEL */ 744b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE3_RX_PCS 400U 745b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE3_TX_CLK divider gated output */ 746b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE3_TX 401U 747b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE3_TX_PCS_CLK divider gated output */ 748b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE3_TX_PCS 402U 749b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE3_MAC_CLK divider output */ 750b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE3_MAC_DIVIDER 403U 751b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE3_MAC_CLK gate output */ 752b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE3_MAC 404U 753b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE3_MACSEC_CLK gate output */ 754b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE3_MACSEC 405U 755b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE3_EEE_PCS_CLK gate output */ 756b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE3_EEE_PCS 406U 757b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE3_APP_CLK gate output */ 758b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE3_APP 407U 759b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE3_PTP_REF_CLK divider gated output */ 760b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE3_PTP_REF 408U 761*41155b6fSJon Hunter /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_GBE_RX_BYP switch divider output */ 762*41155b6fSJon Hunter #define TEGRA234_CLK_GBE_RX_BYP_REF 409U 763*41155b6fSJon Hunter /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_GBE_PLL0_MGMT switch divider output */ 764*41155b6fSJon Hunter #define TEGRA234_CLK_GBE_PLL0_MGMT 410U 765*41155b6fSJon Hunter /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_GBE_PLL1_MGMT switch divider output */ 766*41155b6fSJon Hunter #define TEGRA234_CLK_GBE_PLL1_MGMT 411U 767*41155b6fSJon Hunter /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_GBE_PLL2_MGMT switch divider output */ 768*41155b6fSJon Hunter #define TEGRA234_CLK_GBE_PLL2_MGMT 412U 769*41155b6fSJon Hunter /** @brief output of gate CLK_ENB_EQOS_MACSEC_RX */ 770*41155b6fSJon Hunter #define TEGRA234_CLK_EQOS_MACSEC_RX 413U 771*41155b6fSJon Hunter /** @brief output of gate CLK_ENB_EQOS_MACSEC_TX */ 772*41155b6fSJon Hunter #define TEGRA234_CLK_EQOS_MACSEC_TX 414U 773*41155b6fSJon Hunter /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK divider ungated output */ 774*41155b6fSJon Hunter #define TEGRA234_CLK_EQOS_TX_DIVIDER 415U 775*41155b6fSJon Hunter /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_PLL1_MGMT switch divider output */ 776*41155b6fSJon Hunter #define TEGRA234_CLK_NVHS_PLL1_MGMT 416U 777*41155b6fSJon Hunter /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EMCHUB mux output */ 778*41155b6fSJon Hunter #define TEGRA234_CLK_EMCHUB 417U 779*41155b6fSJon Hunter /** @brief clock recovered from I2S7 input */ 780*41155b6fSJon Hunter #define TEGRA234_CLK_I2S7_SYNC_INPUT 418U 781*41155b6fSJon Hunter /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S7 */ 782*41155b6fSJon Hunter #define TEGRA234_CLK_SYNC_I2S7 419U 783*41155b6fSJon Hunter /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S7 */ 784*41155b6fSJon Hunter #define TEGRA234_CLK_I2S7 420U 785*41155b6fSJon Hunter /** @brief Monitored output of I2S7 pad macro mux */ 786*41155b6fSJon Hunter #define TEGRA234_CLK_I2S7_PAD_M 421U 787*41155b6fSJon Hunter /** @brief clock recovered from I2S8 input */ 788*41155b6fSJon Hunter #define TEGRA234_CLK_I2S8_SYNC_INPUT 422U 789*41155b6fSJon Hunter /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S8 */ 790*41155b6fSJon Hunter #define TEGRA234_CLK_SYNC_I2S8 423U 791*41155b6fSJon Hunter /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S8 */ 792*41155b6fSJon Hunter #define TEGRA234_CLK_I2S8 424U 793*41155b6fSJon Hunter /** @brief Monitored output of I2S8 pad macro mux */ 794*41155b6fSJon Hunter #define TEGRA234_CLK_I2S8_PAD_M 425U 795*41155b6fSJon Hunter /** @brief NAFLL clock source for GPU GPC0 */ 796*41155b6fSJon Hunter #define TEGRA234_CLK_NAFLL_GPC0 426U 797*41155b6fSJon Hunter /** @brief NAFLL clock source for GPU GPC1 */ 798*41155b6fSJon Hunter #define TEGRA234_CLK_NAFLL_GPC1 427U 799*41155b6fSJon Hunter /** @brief NAFLL clock source for GPU SYSCLK */ 800*41155b6fSJon Hunter #define TEGRA234_CLK_NAFLL_GPUSYS 428U 801*41155b6fSJon Hunter /** @brief NAFLL clock source for CPU cluster 0 DSUCLK */ 802*41155b6fSJon Hunter #define TEGRA234_CLK_NAFLL_DSU0 429U /* TODO: remove */ 803*41155b6fSJon Hunter #define TEGRA234_CLK_NAFLL_CLUSTER0_DSU 429U 804*41155b6fSJon Hunter /** @brief NAFLL clock source for CPU cluster 1 DSUCLK */ 805*41155b6fSJon Hunter #define TEGRA234_CLK_NAFLL_DSU1 430U /* TODO: remove */ 806*41155b6fSJon Hunter #define TEGRA234_CLK_NAFLL_CLUSTER1_DSU 430U 807*41155b6fSJon Hunter /** @brief NAFLL clock source for CPU cluster 2 DSUCLK */ 808*41155b6fSJon Hunter #define TEGRA234_CLK_NAFLL_DSU2 431U /* TODO: remove */ 809*41155b6fSJon Hunter #define TEGRA234_CLK_NAFLL_CLUSTER2_DSU 431U 810*41155b6fSJon Hunter /** @brief output of gate CLK_ENB_SCE_CPU */ 811*41155b6fSJon Hunter #define TEGRA234_CLK_SCE_CPU 432U 812*41155b6fSJon Hunter /** @brief output of gate CLK_ENB_RCE_CPU */ 813*41155b6fSJon Hunter #define TEGRA234_CLK_RCE_CPU 433U 814*41155b6fSJon Hunter /** @brief output of gate CLK_ENB_DCE_CPU */ 815*41155b6fSJon Hunter #define TEGRA234_CLK_DCE_CPU 434U 816*41155b6fSJon Hunter /** @brief DSIPLL VCO output */ 817*41155b6fSJon Hunter #define TEGRA234_CLK_DSIPLL_VCO 435U 818*41155b6fSJon Hunter /** @brief DSIPLL SYNC_CLKOUTP/N differential output */ 819*41155b6fSJon Hunter #define TEGRA234_CLK_DSIPLL_CLKOUTPN 436U 820*41155b6fSJon Hunter /** @brief DSIPLL SYNC_CLKOUTA output */ 821*41155b6fSJon Hunter #define TEGRA234_CLK_DSIPLL_CLKOUTA 437U 822*41155b6fSJon Hunter /** @brief SPPLL0 VCO output */ 823*41155b6fSJon Hunter #define TEGRA234_CLK_SPPLL0_VCO 438U 824*41155b6fSJon Hunter /** @brief SPPLL0 SYNC_CLKOUTP/N differential output */ 825*41155b6fSJon Hunter #define TEGRA234_CLK_SPPLL0_CLKOUTPN 439U 826*41155b6fSJon Hunter /** @brief SPPLL0 SYNC_CLKOUTA output */ 827*41155b6fSJon Hunter #define TEGRA234_CLK_SPPLL0_CLKOUTA 440U 828*41155b6fSJon Hunter /** @brief SPPLL0 SYNC_CLKOUTB output */ 829*41155b6fSJon Hunter #define TEGRA234_CLK_SPPLL0_CLKOUTB 441U 830*41155b6fSJon Hunter /** @brief SPPLL0 CLKOUT_DIVBY10 output */ 831*41155b6fSJon Hunter #define TEGRA234_CLK_SPPLL0_DIV10 442U 832*41155b6fSJon Hunter /** @brief SPPLL0 CLKOUT_DIVBY25 output */ 833*41155b6fSJon Hunter #define TEGRA234_CLK_SPPLL0_DIV25 443U 834*41155b6fSJon Hunter /** @brief SPPLL0 CLKOUT_DIVBY27P/N differential output */ 835*41155b6fSJon Hunter #define TEGRA234_CLK_SPPLL0_DIV27PN 444U 836*41155b6fSJon Hunter /** @brief SPPLL1 VCO output */ 837*41155b6fSJon Hunter #define TEGRA234_CLK_SPPLL1_VCO 445U 838*41155b6fSJon Hunter /** @brief SPPLL1 SYNC_CLKOUTP/N differential output */ 839*41155b6fSJon Hunter #define TEGRA234_CLK_SPPLL1_CLKOUTPN 446U 840*41155b6fSJon Hunter /** @brief SPPLL1 CLKOUT_DIVBY27P/N differential output */ 841*41155b6fSJon Hunter #define TEGRA234_CLK_SPPLL1_DIV27PN 447U 842*41155b6fSJon Hunter /** @brief VPLL0 reference clock */ 843*41155b6fSJon Hunter #define TEGRA234_CLK_VPLL0_REF 448U 844*41155b6fSJon Hunter /** @brief VPLL0 */ 845*41155b6fSJon Hunter #define TEGRA234_CLK_VPLL0 449U 846*41155b6fSJon Hunter /** @brief VPLL1 */ 847*41155b6fSJon Hunter #define TEGRA234_CLK_VPLL1 450U 848*41155b6fSJon Hunter /** @brief NVDISPLAY_P0_CLK reference select */ 849*41155b6fSJon Hunter #define TEGRA234_CLK_NVDISPLAY_P0_REF 451U 850*41155b6fSJon Hunter /** @brief RG0_PCLK */ 851*41155b6fSJon Hunter #define TEGRA234_CLK_RG0 452U 852*41155b6fSJon Hunter /** @brief RG1_PCLK */ 853*41155b6fSJon Hunter #define TEGRA234_CLK_RG1 453U 854*41155b6fSJon Hunter /** @brief DISPPLL output */ 855*41155b6fSJon Hunter #define TEGRA234_CLK_DISPPLL 454U 856*41155b6fSJon Hunter /** @brief DISPHUBPLL output */ 857*41155b6fSJon Hunter #define TEGRA234_CLK_DISPHUBPLL 455U 858*41155b6fSJon Hunter /** @brief CLK_RST_CONTROLLER_DSI_LP_SWITCH_DIVIDER switch divider output (dsi_lp_clk) */ 859*41155b6fSJon Hunter #define TEGRA234_CLK_DSI_LP 456U 86007d74390SMohan Kumar /** @brief CLK_RST_CONTROLLER_AZA2XBITCLK_OUT_SWITCH_DIVIDER switch divider output (aza_2xbitclk) */ 86107d74390SMohan Kumar #define TEGRA234_CLK_AZA_2XBIT 457U 86207d74390SMohan Kumar /** @brief aza_2xbitclk / 2 (aza_bitclk) */ 86307d74390SMohan Kumar #define TEGRA234_CLK_AZA_BIT 458U 864*41155b6fSJon Hunter /** @brief SWITCH_DSI_CORE_PIXEL_MISC_DSI_CORE_CLK_SRC switch output (dsi_core_clk) */ 865*41155b6fSJon Hunter #define TEGRA234_CLK_DSI_CORE 459U 866*41155b6fSJon Hunter /** @brief Output of mux controlled by pkt_wr_fifo_signal from dsi (dsi_pixel_clk) */ 867*41155b6fSJon Hunter #define TEGRA234_CLK_DSI_PIXEL 460U 868*41155b6fSJon Hunter /** @brief Output of mux controlled by disp_2clk_sor0_dp_sel (pre_sor0_clk) */ 869*41155b6fSJon Hunter #define TEGRA234_CLK_PRE_SOR0 461U 870*41155b6fSJon Hunter /** @brief Output of mux controlled by disp_2clk_sor1_dp_sel (pre_sor1_clk) */ 871*41155b6fSJon Hunter #define TEGRA234_CLK_PRE_SOR1 462U 872*41155b6fSJon Hunter /** @brief CLK_RST_CONTROLLER_LINK_REFCLK_CFG__0 output */ 873*41155b6fSJon Hunter #define TEGRA234_CLK_DP_LINK_REF 463U 874*41155b6fSJon Hunter /** @brief Link clock input from DP macro brick PLL */ 875*41155b6fSJon Hunter #define TEGRA234_CLK_SOR_LINKA_INPUT 464U 876*41155b6fSJon Hunter /** @brief SOR AFIFO clock outut */ 877*41155b6fSJon Hunter #define TEGRA234_CLK_SOR_LINKA_AFIFO 465U 878*41155b6fSJon Hunter /** @brief Monitored branch of linka_afifo_clk */ 879*41155b6fSJon Hunter #define TEGRA234_CLK_SOR_LINKA_AFIFO_M 466U 880*41155b6fSJon Hunter /** @brief Monitored branch of rg0_pclk */ 881*41155b6fSJon Hunter #define TEGRA234_CLK_RG0_M 467U 882*41155b6fSJon Hunter /** @brief Monitored branch of rg1_pclk */ 883*41155b6fSJon Hunter #define TEGRA234_CLK_RG1_M 468U 884*41155b6fSJon Hunter /** @brief Monitored branch of sor0_clk */ 885*41155b6fSJon Hunter #define TEGRA234_CLK_SOR0_M 469U 886*41155b6fSJon Hunter /** @brief Monitored branch of sor1_clk */ 887*41155b6fSJon Hunter #define TEGRA234_CLK_SOR1_M 470U 888*41155b6fSJon Hunter /** @brief EMC PLLHUB output */ 889*41155b6fSJon Hunter #define TEGRA234_CLK_PLLHUB 471U 890*41155b6fSJon Hunter /** @brief output of fixed (DIV2) MC HUB divider */ 891*41155b6fSJon Hunter #define TEGRA234_CLK_MCHUB 472U 892*41155b6fSJon Hunter /** @brief output of divider controlled by EMC side A MC_EMC_SAFE_SAME_FREQ */ 893*41155b6fSJon Hunter #define TEGRA234_CLK_EMCSA_MC 473U 894*41155b6fSJon Hunter /** @brief output of divider controlled by EMC side B MC_EMC_SAFE_SAME_FREQ */ 895*41155b6fSJon Hunter #define TEGRA234_CLK_EMCSB_MC 474U 896*41155b6fSJon Hunter /** @brief output of divider controlled by EMC side C MC_EMC_SAFE_SAME_FREQ */ 897*41155b6fSJon Hunter #define TEGRA234_CLK_EMCSC_MC 475U 898*41155b6fSJon Hunter /** @brief output of divider controlled by EMC side D MC_EMC_SAFE_SAME_FREQ */ 899*41155b6fSJon Hunter #define TEGRA234_CLK_EMCSD_MC 476U 900*41155b6fSJon Hunter 901*41155b6fSJon Hunter /** @} */ 902b0aedf34SThierry Reding 90363944891SThierry Reding #endif 904