1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2023 Meta Platforms, Inc. and affiliates 4 * Copyright (c) 2023 Intel and affiliates 5 */ 6 7 #ifndef __DPLL_H__ 8 #define __DPLL_H__ 9 10 #include <uapi/linux/dpll.h> 11 #include <linux/device.h> 12 #include <linux/netlink.h> 13 #include <linux/netdevice.h> 14 #include <linux/rtnetlink.h> 15 16 struct dpll_device; 17 struct dpll_pin; 18 19 struct dpll_device_ops { 20 int (*mode_get)(const struct dpll_device *dpll, void *dpll_priv, 21 enum dpll_mode *mode, struct netlink_ext_ack *extack); 22 int (*lock_status_get)(const struct dpll_device *dpll, void *dpll_priv, 23 enum dpll_lock_status *status, 24 enum dpll_lock_status_error *status_error, 25 struct netlink_ext_ack *extack); 26 int (*temp_get)(const struct dpll_device *dpll, void *dpll_priv, 27 s32 *temp, struct netlink_ext_ack *extack); 28 }; 29 30 struct dpll_pin_ops { 31 int (*frequency_set)(const struct dpll_pin *pin, void *pin_priv, 32 const struct dpll_device *dpll, void *dpll_priv, 33 const u64 frequency, 34 struct netlink_ext_ack *extack); 35 int (*frequency_get)(const struct dpll_pin *pin, void *pin_priv, 36 const struct dpll_device *dpll, void *dpll_priv, 37 u64 *frequency, struct netlink_ext_ack *extack); 38 int (*direction_set)(const struct dpll_pin *pin, void *pin_priv, 39 const struct dpll_device *dpll, void *dpll_priv, 40 const enum dpll_pin_direction direction, 41 struct netlink_ext_ack *extack); 42 int (*direction_get)(const struct dpll_pin *pin, void *pin_priv, 43 const struct dpll_device *dpll, void *dpll_priv, 44 enum dpll_pin_direction *direction, 45 struct netlink_ext_ack *extack); 46 int (*state_on_pin_get)(const struct dpll_pin *pin, void *pin_priv, 47 const struct dpll_pin *parent_pin, 48 void *parent_pin_priv, 49 enum dpll_pin_state *state, 50 struct netlink_ext_ack *extack); 51 int (*state_on_dpll_get)(const struct dpll_pin *pin, void *pin_priv, 52 const struct dpll_device *dpll, 53 void *dpll_priv, enum dpll_pin_state *state, 54 struct netlink_ext_ack *extack); 55 int (*state_on_pin_set)(const struct dpll_pin *pin, void *pin_priv, 56 const struct dpll_pin *parent_pin, 57 void *parent_pin_priv, 58 const enum dpll_pin_state state, 59 struct netlink_ext_ack *extack); 60 int (*state_on_dpll_set)(const struct dpll_pin *pin, void *pin_priv, 61 const struct dpll_device *dpll, 62 void *dpll_priv, 63 const enum dpll_pin_state state, 64 struct netlink_ext_ack *extack); 65 int (*prio_get)(const struct dpll_pin *pin, void *pin_priv, 66 const struct dpll_device *dpll, void *dpll_priv, 67 u32 *prio, struct netlink_ext_ack *extack); 68 int (*prio_set)(const struct dpll_pin *pin, void *pin_priv, 69 const struct dpll_device *dpll, void *dpll_priv, 70 const u32 prio, struct netlink_ext_ack *extack); 71 int (*phase_offset_get)(const struct dpll_pin *pin, void *pin_priv, 72 const struct dpll_device *dpll, void *dpll_priv, 73 s64 *phase_offset, 74 struct netlink_ext_ack *extack); 75 int (*phase_adjust_get)(const struct dpll_pin *pin, void *pin_priv, 76 const struct dpll_device *dpll, void *dpll_priv, 77 s32 *phase_adjust, 78 struct netlink_ext_ack *extack); 79 int (*phase_adjust_set)(const struct dpll_pin *pin, void *pin_priv, 80 const struct dpll_device *dpll, void *dpll_priv, 81 const s32 phase_adjust, 82 struct netlink_ext_ack *extack); 83 int (*ffo_get)(const struct dpll_pin *pin, void *pin_priv, 84 const struct dpll_device *dpll, void *dpll_priv, 85 s64 *ffo, struct netlink_ext_ack *extack); 86 }; 87 88 struct dpll_pin_frequency { 89 u64 min; 90 u64 max; 91 }; 92 93 #define DPLL_PIN_FREQUENCY_RANGE(_min, _max) \ 94 { \ 95 .min = _min, \ 96 .max = _max, \ 97 } 98 99 #define DPLL_PIN_FREQUENCY(_val) DPLL_PIN_FREQUENCY_RANGE(_val, _val) 100 #define DPLL_PIN_FREQUENCY_1PPS \ 101 DPLL_PIN_FREQUENCY(DPLL_PIN_FREQUENCY_1_HZ) 102 #define DPLL_PIN_FREQUENCY_10MHZ \ 103 DPLL_PIN_FREQUENCY(DPLL_PIN_FREQUENCY_10_MHZ) 104 #define DPLL_PIN_FREQUENCY_IRIG_B \ 105 DPLL_PIN_FREQUENCY(DPLL_PIN_FREQUENCY_10_KHZ) 106 #define DPLL_PIN_FREQUENCY_DCF77 \ 107 DPLL_PIN_FREQUENCY(DPLL_PIN_FREQUENCY_77_5_KHZ) 108 109 struct dpll_pin_phase_adjust_range { 110 s32 min; 111 s32 max; 112 }; 113 114 struct dpll_pin_properties { 115 const char *board_label; 116 const char *panel_label; 117 const char *package_label; 118 enum dpll_pin_type type; 119 unsigned long capabilities; 120 u32 freq_supported_num; 121 struct dpll_pin_frequency *freq_supported; 122 struct dpll_pin_phase_adjust_range phase_range; 123 }; 124 125 #if IS_ENABLED(CONFIG_DPLL) 126 void dpll_netdev_pin_set(struct net_device *dev, struct dpll_pin *dpll_pin); 127 void dpll_netdev_pin_clear(struct net_device *dev); 128 129 size_t dpll_netdev_pin_handle_size(const struct net_device *dev); 130 int dpll_netdev_add_pin_handle(struct sk_buff *msg, 131 const struct net_device *dev); 132 #else 133 static inline void 134 dpll_netdev_pin_set(struct net_device *dev, struct dpll_pin *dpll_pin) { } 135 static inline void dpll_netdev_pin_clear(struct net_device *dev) { } 136 137 static inline size_t dpll_netdev_pin_handle_size(const struct net_device *dev) 138 { 139 return 0; 140 } 141 142 static inline int 143 dpll_netdev_add_pin_handle(struct sk_buff *msg, const struct net_device *dev) 144 { 145 return 0; 146 } 147 #endif 148 149 struct dpll_device * 150 dpll_device_get(u64 clock_id, u32 dev_driver_id, struct module *module); 151 152 void dpll_device_put(struct dpll_device *dpll); 153 154 int dpll_device_register(struct dpll_device *dpll, enum dpll_type type, 155 const struct dpll_device_ops *ops, void *priv); 156 157 void dpll_device_unregister(struct dpll_device *dpll, 158 const struct dpll_device_ops *ops, void *priv); 159 160 struct dpll_pin * 161 dpll_pin_get(u64 clock_id, u32 dev_driver_id, struct module *module, 162 const struct dpll_pin_properties *prop); 163 164 int dpll_pin_register(struct dpll_device *dpll, struct dpll_pin *pin, 165 const struct dpll_pin_ops *ops, void *priv); 166 167 void dpll_pin_unregister(struct dpll_device *dpll, struct dpll_pin *pin, 168 const struct dpll_pin_ops *ops, void *priv); 169 170 void dpll_pin_put(struct dpll_pin *pin); 171 172 int dpll_pin_on_pin_register(struct dpll_pin *parent, struct dpll_pin *pin, 173 const struct dpll_pin_ops *ops, void *priv); 174 175 void dpll_pin_on_pin_unregister(struct dpll_pin *parent, struct dpll_pin *pin, 176 const struct dpll_pin_ops *ops, void *priv); 177 178 int dpll_device_change_ntf(struct dpll_device *dpll); 179 180 int dpll_pin_change_ntf(struct dpll_pin *pin); 181 182 #endif 183