1 /* 2 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. 3 * 4 * Freescale DIU Frame Buffer device driver 5 * 6 * Authors: Hongjun Chen <hong-jun.chen@freescale.com> 7 * Paul Widmer <paul.widmer@freescale.com> 8 * Srikanth Srinivasan <srikanth.srinivasan@freescale.com> 9 * York Sun <yorksun@freescale.com> 10 * 11 * Based on imxfb.c Copyright (C) 2004 S.Hauer, Pengutronix 12 * 13 * This program is free software; you can redistribute it and/or modify it 14 * under the terms of the GNU General Public License as published by the 15 * Free Software Foundation; either version 2 of the License, or (at your 16 * option) any later version. 17 * 18 */ 19 20 #ifndef __FSL_DIU_FB_H__ 21 #define __FSL_DIU_FB_H__ 22 23 /* Arbitrary threshold to determine the allocation method 24 * See mpc8610fb_set_par(), map_video_memory(), and unmap_video_memory() 25 */ 26 #define MEM_ALLOC_THRESHOLD (1024*768*4+32) 27 28 #include <linux/types.h> 29 30 struct mfb_chroma_key { 31 int enable; 32 __u8 red_max; 33 __u8 green_max; 34 __u8 blue_max; 35 __u8 red_min; 36 __u8 green_min; 37 __u8 blue_min; 38 }; 39 40 struct aoi_display_offset { 41 int x_aoi_d; 42 int y_aoi_d; 43 }; 44 45 #define MFB_SET_CHROMA_KEY _IOW('M', 1, struct mfb_chroma_key) 46 #define MFB_SET_BRIGHTNESS _IOW('M', 3, __u8) 47 48 #define MFB_SET_ALPHA 0x80014d00 49 #define MFB_GET_ALPHA 0x40014d00 50 #define MFB_SET_AOID 0x80084d04 51 #define MFB_GET_AOID 0x40084d04 52 #define MFB_SET_PIXFMT 0x80014d08 53 #define MFB_GET_PIXFMT 0x40014d08 54 55 #define FBIOGET_GWINFO 0x46E0 56 #define FBIOPUT_GWINFO 0x46E1 57 58 #ifdef __KERNEL__ 59 #include <linux/spinlock.h> 60 61 /* 62 * These are the fields of area descriptor(in DDR memory) for every plane 63 */ 64 struct diu_ad { 65 /* Word 0(32-bit) in DDR memory */ 66 /* __u16 comp; */ 67 /* __u16 pixel_s:2; */ 68 /* __u16 pallete:1; */ 69 /* __u16 red_c:2; */ 70 /* __u16 green_c:2; */ 71 /* __u16 blue_c:2; */ 72 /* __u16 alpha_c:3; */ 73 /* __u16 byte_f:1; */ 74 /* __u16 res0:3; */ 75 76 __be32 pix_fmt; /* hard coding pixel format */ 77 78 /* Word 1(32-bit) in DDR memory */ 79 __le32 addr; 80 81 /* Word 2(32-bit) in DDR memory */ 82 /* __u32 delta_xs:11; */ 83 /* __u32 res1:1; */ 84 /* __u32 delta_ys:11; */ 85 /* __u32 res2:1; */ 86 /* __u32 g_alpha:8; */ 87 __le32 src_size_g_alpha; 88 89 /* Word 3(32-bit) in DDR memory */ 90 /* __u32 delta_xi:11; */ 91 /* __u32 res3:5; */ 92 /* __u32 delta_yi:11; */ 93 /* __u32 res4:3; */ 94 /* __u32 flip:2; */ 95 __le32 aoi_size; 96 97 /* Word 4(32-bit) in DDR memory */ 98 /*__u32 offset_xi:11; 99 __u32 res5:5; 100 __u32 offset_yi:11; 101 __u32 res6:5; 102 */ 103 __le32 offset_xyi; 104 105 /* Word 5(32-bit) in DDR memory */ 106 /*__u32 offset_xd:11; 107 __u32 res7:5; 108 __u32 offset_yd:11; 109 __u32 res8:5; */ 110 __le32 offset_xyd; 111 112 113 /* Word 6(32-bit) in DDR memory */ 114 __u8 ckmax_r; 115 __u8 ckmax_g; 116 __u8 ckmax_b; 117 __u8 res9; 118 119 /* Word 7(32-bit) in DDR memory */ 120 __u8 ckmin_r; 121 __u8 ckmin_g; 122 __u8 ckmin_b; 123 __u8 res10; 124 /* __u32 res10:8; */ 125 126 /* Word 8(32-bit) in DDR memory */ 127 __le32 next_ad; 128 129 /* Word 9(32-bit) in DDR memory, just for 64-bit aligned */ 130 __u32 paddr; 131 } __attribute__ ((packed)); 132 133 /* DIU register map */ 134 struct diu { 135 __be32 desc[3]; 136 __be32 gamma; 137 __be32 pallete; 138 __be32 cursor; 139 __be32 curs_pos; 140 __be32 diu_mode; 141 __be32 bgnd; 142 __be32 bgnd_wb; 143 __be32 disp_size; 144 __be32 wb_size; 145 __be32 wb_mem_addr; 146 __be32 hsyn_para; 147 __be32 vsyn_para; 148 __be32 syn_pol; 149 __be32 thresholds; 150 __be32 int_status; 151 __be32 int_mask; 152 __be32 colorbar[8]; 153 __be32 filling; 154 __be32 plut; 155 } __attribute__ ((packed)); 156 157 struct diu_hw { 158 struct diu *diu_reg; 159 spinlock_t reg_lock; 160 161 __u32 mode; /* DIU operation mode */ 162 }; 163 164 struct diu_addr { 165 __u8 __iomem *vaddr; /* Virtual address */ 166 dma_addr_t paddr; /* Physical address */ 167 __u32 offset; 168 }; 169 170 struct diu_pool { 171 struct diu_addr ad; 172 struct diu_addr gamma; 173 struct diu_addr pallete; 174 struct diu_addr cursor; 175 }; 176 177 #define FSL_DIU_BASE_OFFSET 0x2C000 /* Offset of DIU */ 178 #define INT_LCDC 64 /* DIU interrupt number */ 179 180 #define FSL_AOI_NUM 6 /* 5 AOIs and one dummy AOI */ 181 /* 1 for plane 0, 2 for plane 1&2 each */ 182 183 /* Minimum X and Y resolutions */ 184 #define MIN_XRES 64 185 #define MIN_YRES 64 186 187 /* HW cursor parameters */ 188 #define MAX_CURS 32 189 190 /* Modes of operation of DIU */ 191 #define MFB_MODE0 0 /* DIU off */ 192 #define MFB_MODE1 1 /* All three planes output to display */ 193 #define MFB_MODE2 2 /* Plane 1 to display, planes 2+3 written back*/ 194 #define MFB_MODE3 3 /* All three planes written back to memory */ 195 #define MFB_MODE4 4 /* Color bar generation */ 196 197 /* INT_STATUS/INT_MASK field descriptions */ 198 #define INT_VSYNC 0x01 /* Vsync interrupt */ 199 #define INT_VSYNC_WB 0x02 /* Vsync interrupt for write back operation */ 200 #define INT_UNDRUN 0x04 /* Under run exception interrupt */ 201 #define INT_PARERR 0x08 /* Display parameters error interrupt */ 202 #define INT_LS_BF_VS 0x10 /* Lines before vsync. interrupt */ 203 204 /* Panels'operation modes */ 205 #define MFB_TYPE_OUTPUT 0 /* Panel output to display */ 206 #define MFB_TYPE_OFF 1 /* Panel off */ 207 #define MFB_TYPE_WB 2 /* Panel written back to memory */ 208 #define MFB_TYPE_TEST 3 /* Panel generate color bar */ 209 210 #endif /* __KERNEL__ */ 211 #endif /* __FSL_DIU_FB_H__ */ 212