1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2020-2023 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8 #ifndef CPUCP_IF_H 9 #define CPUCP_IF_H 10 11 #include <linux/types.h> 12 #include <linux/if_ether.h> 13 14 #include "hl_boot_if.h" 15 16 #define NUM_HBM_PSEUDO_CH 2 17 #define NUM_HBM_CH_PER_DEV 8 18 #define CPUCP_PKT_HBM_ECC_INFO_WR_PAR_SHIFT 0 19 #define CPUCP_PKT_HBM_ECC_INFO_WR_PAR_MASK 0x00000001 20 #define CPUCP_PKT_HBM_ECC_INFO_RD_PAR_SHIFT 1 21 #define CPUCP_PKT_HBM_ECC_INFO_RD_PAR_MASK 0x00000002 22 #define CPUCP_PKT_HBM_ECC_INFO_CA_PAR_SHIFT 2 23 #define CPUCP_PKT_HBM_ECC_INFO_CA_PAR_MASK 0x00000004 24 #define CPUCP_PKT_HBM_ECC_INFO_DERR_SHIFT 3 25 #define CPUCP_PKT_HBM_ECC_INFO_DERR_MASK 0x00000008 26 #define CPUCP_PKT_HBM_ECC_INFO_SERR_SHIFT 4 27 #define CPUCP_PKT_HBM_ECC_INFO_SERR_MASK 0x00000010 28 #define CPUCP_PKT_HBM_ECC_INFO_TYPE_SHIFT 5 29 #define CPUCP_PKT_HBM_ECC_INFO_TYPE_MASK 0x00000020 30 #define CPUCP_PKT_HBM_ECC_INFO_HBM_CH_SHIFT 6 31 #define CPUCP_PKT_HBM_ECC_INFO_HBM_CH_MASK 0x000007C0 32 33 #define PLL_MAP_MAX_BITS 128 34 #define PLL_MAP_LEN (PLL_MAP_MAX_BITS / 8) 35 36 enum eq_event_id { 37 EQ_EVENT_NIC_STS_REQUEST = 0, 38 EQ_EVENT_PWR_MODE_0, 39 EQ_EVENT_PWR_MODE_1, 40 EQ_EVENT_PWR_MODE_2, 41 EQ_EVENT_PWR_MODE_3, 42 EQ_EVENT_PWR_BRK_ENTRY, 43 EQ_EVENT_PWR_BRK_EXIT, 44 EQ_EVENT_HEARTBEAT, 45 }; 46 47 /* 48 * info of the pkt queue pointers in the first async occurrence 49 */ 50 struct cpucp_pkt_sync_err { 51 __le32 pi; 52 __le32 ci; 53 }; 54 55 struct hl_eq_hbm_ecc_data { 56 /* SERR counter */ 57 __le32 sec_cnt; 58 /* DERR counter */ 59 __le32 dec_cnt; 60 /* Supplemental Information according to the mask bits */ 61 __le32 hbm_ecc_info; 62 /* Address in hbm where the ecc happened */ 63 __le32 first_addr; 64 /* SERR continuous address counter */ 65 __le32 sec_cont_cnt; 66 __le32 pad; 67 }; 68 69 /* 70 * EVENT QUEUE 71 */ 72 73 struct hl_eq_header { 74 __le32 reserved; 75 __le32 ctl; 76 }; 77 78 struct hl_eq_ecc_data { 79 __le64 ecc_address; 80 __le64 ecc_syndrom; 81 __u8 memory_wrapper_idx; 82 __u8 is_critical; 83 __le16 block_id; 84 __u8 pad[4]; 85 }; 86 87 enum hl_sm_sei_cause { 88 SM_SEI_SO_OVERFLOW, 89 SM_SEI_LBW_4B_UNALIGNED, 90 SM_SEI_AXI_RESPONSE_ERR 91 }; 92 93 struct hl_eq_sm_sei_data { 94 __le32 sei_log; 95 /* enum hl_sm_sei_cause */ 96 __u8 sei_cause; 97 __u8 pad[3]; 98 }; 99 100 enum hl_fw_alive_severity { 101 FW_ALIVE_SEVERITY_MINOR, 102 FW_ALIVE_SEVERITY_CRITICAL 103 }; 104 105 struct hl_eq_fw_alive { 106 __le64 uptime_seconds; 107 __le32 process_id; 108 __le32 thread_id; 109 /* enum hl_fw_alive_severity */ 110 __u8 severity; 111 __u8 pad[7]; 112 }; 113 114 struct hl_eq_intr_cause { 115 __le64 intr_cause_data; 116 }; 117 118 struct hl_eq_pcie_drain_ind_data { 119 struct hl_eq_intr_cause intr_cause; 120 __le64 drain_wr_addr_lbw; 121 __le64 drain_rd_addr_lbw; 122 __le64 drain_wr_addr_hbw; 123 __le64 drain_rd_addr_hbw; 124 }; 125 126 struct hl_eq_razwi_lbw_info_regs { 127 __le32 rr_aw_razwi_reg; 128 __le32 rr_aw_razwi_id_reg; 129 __le32 rr_ar_razwi_reg; 130 __le32 rr_ar_razwi_id_reg; 131 }; 132 133 struct hl_eq_razwi_hbw_info_regs { 134 __le32 rr_aw_razwi_hi_reg; 135 __le32 rr_aw_razwi_lo_reg; 136 __le32 rr_aw_razwi_id_reg; 137 __le32 rr_ar_razwi_hi_reg; 138 __le32 rr_ar_razwi_lo_reg; 139 __le32 rr_ar_razwi_id_reg; 140 }; 141 142 /* razwi_happened masks */ 143 #define RAZWI_HAPPENED_HBW 0x1 144 #define RAZWI_HAPPENED_LBW 0x2 145 #define RAZWI_HAPPENED_AW 0x4 146 #define RAZWI_HAPPENED_AR 0x8 147 148 struct hl_eq_razwi_info { 149 __le32 razwi_happened_mask; 150 union { 151 struct hl_eq_razwi_lbw_info_regs lbw; 152 struct hl_eq_razwi_hbw_info_regs hbw; 153 }; 154 __le32 pad; 155 }; 156 157 struct hl_eq_razwi_with_intr_cause { 158 struct hl_eq_razwi_info razwi_info; 159 struct hl_eq_intr_cause intr_cause; 160 }; 161 162 #define HBM_CA_ERR_CMD_LIFO_LEN 8 163 #define HBM_RD_ERR_DATA_LIFO_LEN 8 164 #define HBM_WR_PAR_CMD_LIFO_LEN 11 165 166 enum hl_hbm_sei_cause { 167 /* Command/address parity error event is split into 2 events due to 168 * size limitation: ODD suffix for odd HBM CK_t cycles and EVEN suffix 169 * for even HBM CK_t cycles 170 */ 171 HBM_SEI_CMD_PARITY_EVEN, 172 HBM_SEI_CMD_PARITY_ODD, 173 /* Read errors can be reflected as a combination of SERR/DERR/parity 174 * errors. Therefore, we define one event for all read error types. 175 * LKD will perform further proccessing. 176 */ 177 HBM_SEI_READ_ERR, 178 HBM_SEI_WRITE_DATA_PARITY_ERR, 179 HBM_SEI_CATTRIP, 180 HBM_SEI_MEM_BIST_FAIL, 181 HBM_SEI_DFI, 182 HBM_SEI_INV_TEMP_READ_OUT, 183 HBM_SEI_BIST_FAIL, 184 }; 185 186 /* Masks for parsing hl_hbm_sei_headr fields */ 187 #define HBM_ECC_SERR_CNTR_MASK 0xFF 188 #define HBM_ECC_DERR_CNTR_MASK 0xFF00 189 #define HBM_RD_PARITY_CNTR_MASK 0xFF0000 190 191 /* HBM index and MC index are known by the event_id */ 192 struct hl_hbm_sei_header { 193 union { 194 /* relevant only in case of HBM read error */ 195 struct { 196 __u8 ecc_serr_cnt; 197 __u8 ecc_derr_cnt; 198 __u8 read_par_cnt; 199 __u8 reserved; 200 }; 201 /* All other cases */ 202 __le32 cnt; 203 }; 204 __u8 sei_cause; /* enum hl_hbm_sei_cause */ 205 __u8 mc_channel; /* range: 0-3 */ 206 __u8 mc_pseudo_channel; /* range: 0-7 */ 207 __u8 is_critical; 208 }; 209 210 #define HBM_RD_ADDR_SID_SHIFT 0 211 #define HBM_RD_ADDR_SID_MASK 0x1 212 #define HBM_RD_ADDR_BG_SHIFT 1 213 #define HBM_RD_ADDR_BG_MASK 0x6 214 #define HBM_RD_ADDR_BA_SHIFT 3 215 #define HBM_RD_ADDR_BA_MASK 0x18 216 #define HBM_RD_ADDR_COL_SHIFT 5 217 #define HBM_RD_ADDR_COL_MASK 0x7E0 218 #define HBM_RD_ADDR_ROW_SHIFT 11 219 #define HBM_RD_ADDR_ROW_MASK 0x3FFF800 220 221 struct hbm_rd_addr { 222 union { 223 /* bit fields are only for FW use */ 224 struct { 225 u32 dbg_rd_err_addr_sid:1; 226 u32 dbg_rd_err_addr_bg:2; 227 u32 dbg_rd_err_addr_ba:2; 228 u32 dbg_rd_err_addr_col:6; 229 u32 dbg_rd_err_addr_row:15; 230 u32 reserved:6; 231 }; 232 __le32 rd_addr_val; 233 }; 234 }; 235 236 #define HBM_RD_ERR_BEAT_SHIFT 2 237 /* dbg_rd_err_misc fields: */ 238 /* Read parity is calculated per DW on every beat */ 239 #define HBM_RD_ERR_PAR_ERR_BEAT0_SHIFT 0 240 #define HBM_RD_ERR_PAR_ERR_BEAT0_MASK 0x3 241 #define HBM_RD_ERR_PAR_DATA_BEAT0_SHIFT 8 242 #define HBM_RD_ERR_PAR_DATA_BEAT0_MASK 0x300 243 /* ECC is calculated per PC on every beat */ 244 #define HBM_RD_ERR_SERR_BEAT0_SHIFT 16 245 #define HBM_RD_ERR_SERR_BEAT0_MASK 0x10000 246 #define HBM_RD_ERR_DERR_BEAT0_SHIFT 24 247 #define HBM_RD_ERR_DERR_BEAT0_MASK 0x100000 248 249 struct hl_eq_hbm_sei_read_err_intr_info { 250 /* DFI_RD_ERR_REP_ADDR */ 251 struct hbm_rd_addr dbg_rd_err_addr; 252 /* DFI_RD_ERR_REP_ERR */ 253 union { 254 struct { 255 /* bit fields are only for FW use */ 256 u32 dbg_rd_err_par:8; 257 u32 dbg_rd_err_par_data:8; 258 u32 dbg_rd_err_serr:4; 259 u32 dbg_rd_err_derr:4; 260 u32 reserved:8; 261 }; 262 __le32 dbg_rd_err_misc; 263 }; 264 /* DFI_RD_ERR_REP_DM */ 265 __le32 dbg_rd_err_dm; 266 /* DFI_RD_ERR_REP_SYNDROME */ 267 __le32 dbg_rd_err_syndrome; 268 /* DFI_RD_ERR_REP_DATA */ 269 __le32 dbg_rd_err_data[HBM_RD_ERR_DATA_LIFO_LEN]; 270 }; 271 272 struct hl_eq_hbm_sei_ca_par_intr_info { 273 /* 14 LSBs */ 274 __le16 dbg_row[HBM_CA_ERR_CMD_LIFO_LEN]; 275 /* 18 LSBs */ 276 __le32 dbg_col[HBM_CA_ERR_CMD_LIFO_LEN]; 277 }; 278 279 #define WR_PAR_LAST_CMD_COL_SHIFT 0 280 #define WR_PAR_LAST_CMD_COL_MASK 0x3F 281 #define WR_PAR_LAST_CMD_BG_SHIFT 6 282 #define WR_PAR_LAST_CMD_BG_MASK 0xC0 283 #define WR_PAR_LAST_CMD_BA_SHIFT 8 284 #define WR_PAR_LAST_CMD_BA_MASK 0x300 285 #define WR_PAR_LAST_CMD_SID_SHIFT 10 286 #define WR_PAR_LAST_CMD_SID_MASK 0x400 287 288 /* Row address isn't latched */ 289 struct hbm_sei_wr_cmd_address { 290 /* DFI_DERR_LAST_CMD */ 291 union { 292 struct { 293 /* bit fields are only for FW use */ 294 u32 col:6; 295 u32 bg:2; 296 u32 ba:2; 297 u32 sid:1; 298 u32 reserved:21; 299 }; 300 __le32 dbg_wr_cmd_addr; 301 }; 302 }; 303 304 struct hl_eq_hbm_sei_wr_par_intr_info { 305 /* entry 0: WR command address from the 1st cycle prior to the error 306 * entry 1: WR command address from the 2nd cycle prior to the error 307 * and so on... 308 */ 309 struct hbm_sei_wr_cmd_address dbg_last_wr_cmds[HBM_WR_PAR_CMD_LIFO_LEN]; 310 /* derr[0:1] - 1st HBM cycle DERR output 311 * derr[2:3] - 2nd HBM cycle DERR output 312 */ 313 __u8 dbg_derr; 314 /* extend to reach 8B */ 315 __u8 pad[3]; 316 }; 317 318 /* 319 * this struct represents the following sei causes: 320 * command parity, ECC double error, ECC single error, dfi error, cattrip, 321 * temperature read-out, read parity error and write parity error. 322 * some only use the header while some have extra data. 323 */ 324 struct hl_eq_hbm_sei_data { 325 struct hl_hbm_sei_header hdr; 326 union { 327 struct hl_eq_hbm_sei_ca_par_intr_info ca_parity_even_info; 328 struct hl_eq_hbm_sei_ca_par_intr_info ca_parity_odd_info; 329 struct hl_eq_hbm_sei_read_err_intr_info read_err_info; 330 struct hl_eq_hbm_sei_wr_par_intr_info wr_parity_info; 331 }; 332 }; 333 334 /* Engine/farm arc interrupt type */ 335 enum hl_engine_arc_interrupt_type { 336 /* Qman/farm ARC DCCM QUEUE FULL interrupt type */ 337 ENGINE_ARC_DCCM_QUEUE_FULL_IRQ = 1 338 }; 339 340 /* Data structure specifies details of payload of DCCM QUEUE FULL interrupt */ 341 struct hl_engine_arc_dccm_queue_full_irq { 342 /* Queue index value which caused DCCM QUEUE FULL */ 343 __le32 queue_index; 344 __le32 pad; 345 }; 346 347 /* Data structure specifies details of QM/FARM ARC interrupt */ 348 struct hl_eq_engine_arc_intr_data { 349 /* ARC engine id e.g. DCORE0_TPC0_QM_ARC, DCORE0_TCP1_QM_ARC */ 350 __le32 engine_id; 351 __le32 intr_type; /* enum hl_engine_arc_interrupt_type */ 352 /* More info related to the interrupt e.g. queue index 353 * incase of DCCM_QUEUE_FULL interrupt. 354 */ 355 __le64 payload; 356 __le64 pad[5]; 357 }; 358 359 #define ADDR_DEC_ADDRESS_COUNT_MAX 4 360 361 /* Data structure specifies details of ADDR_DEC interrupt */ 362 struct hl_eq_addr_dec_intr_data { 363 struct hl_eq_intr_cause intr_cause; 364 __le64 addr[ADDR_DEC_ADDRESS_COUNT_MAX]; 365 __u8 addr_cnt; 366 __u8 pad[7]; 367 }; 368 369 struct hl_eq_entry { 370 struct hl_eq_header hdr; 371 union { 372 __le64 data_placeholder; 373 struct hl_eq_ecc_data ecc_data; 374 struct hl_eq_hbm_ecc_data hbm_ecc_data; /* Obsolete */ 375 struct hl_eq_sm_sei_data sm_sei_data; 376 struct cpucp_pkt_sync_err pkt_sync_err; 377 struct hl_eq_fw_alive fw_alive; 378 struct hl_eq_intr_cause intr_cause; 379 struct hl_eq_pcie_drain_ind_data pcie_drain_ind_data; 380 struct hl_eq_razwi_info razwi_info; 381 struct hl_eq_razwi_with_intr_cause razwi_with_intr_cause; 382 struct hl_eq_hbm_sei_data sei_data; /* Gaudi2 HBM */ 383 struct hl_eq_engine_arc_intr_data arc_data; 384 struct hl_eq_addr_dec_intr_data addr_dec; 385 __le64 data[7]; 386 }; 387 }; 388 389 #define HL_EQ_ENTRY_SIZE sizeof(struct hl_eq_entry) 390 391 #define EQ_CTL_READY_SHIFT 31 392 #define EQ_CTL_READY_MASK 0x80000000 393 394 #define EQ_CTL_EVENT_TYPE_SHIFT 16 395 #define EQ_CTL_EVENT_TYPE_MASK 0x0FFF0000 396 397 #define EQ_CTL_INDEX_SHIFT 0 398 #define EQ_CTL_INDEX_MASK 0x0000FFFF 399 400 enum pq_init_status { 401 PQ_INIT_STATUS_NA = 0, 402 PQ_INIT_STATUS_READY_FOR_CP, 403 PQ_INIT_STATUS_READY_FOR_HOST, 404 PQ_INIT_STATUS_READY_FOR_CP_SINGLE_MSI, 405 PQ_INIT_STATUS_LEN_NOT_POWER_OF_TWO_ERR, 406 PQ_INIT_STATUS_ILLEGAL_Q_ADDR_ERR 407 }; 408 409 /* 410 * CpuCP Primary Queue Packets 411 * 412 * During normal operation, the host's kernel driver needs to send various 413 * messages to CpuCP, usually either to SET some value into a H/W periphery or 414 * to GET the current value of some H/W periphery. For example, SET the 415 * frequency of MME/TPC and GET the value of the thermal sensor. 416 * 417 * These messages can be initiated either by the User application or by the 418 * host's driver itself, e.g. power management code. In either case, the 419 * communication from the host's driver to CpuCP will *always* be in 420 * synchronous mode, meaning that the host will send a single message and poll 421 * until the message was acknowledged and the results are ready (if results are 422 * needed). 423 * 424 * This means that only a single message can be sent at a time and the host's 425 * driver must wait for its result before sending the next message. Having said 426 * that, because these are control messages which are sent in a relatively low 427 * frequency, this limitation seems acceptable. It's important to note that 428 * in case of multiple devices, messages to different devices *can* be sent 429 * at the same time. 430 * 431 * The message, inputs/outputs (if relevant) and fence object will be located 432 * on the device DDR at an address that will be determined by the host's driver. 433 * During device initialization phase, the host will pass to CpuCP that address. 434 * Most of the message types will contain inputs/outputs inside the message 435 * itself. The common part of each message will contain the opcode of the 436 * message (its type) and a field representing a fence object. 437 * 438 * When the host's driver wishes to send a message to CPU CP, it will write the 439 * message contents to the device DDR, clear the fence object and then write to 440 * the PSOC_ARC1_AUX_SW_INTR, to issue interrupt 121 to ARC Management CPU. 441 * 442 * Upon receiving the interrupt (#121), CpuCP will read the message from the 443 * DDR. In case the message is a SET operation, CpuCP will first perform the 444 * operation and then write to the fence object on the device DDR. In case the 445 * message is a GET operation, CpuCP will first fill the results section on the 446 * device DDR and then write to the fence object. If an error occurred, CpuCP 447 * will fill the rc field with the right error code. 448 * 449 * In the meantime, the host's driver will poll on the fence object. Once the 450 * host sees that the fence object is signaled, it will read the results from 451 * the device DDR (if relevant) and resume the code execution in the host's 452 * driver. 453 * 454 * To use QMAN packets, the opcode must be the QMAN opcode, shifted by 8 455 * so the value being put by the host's driver matches the value read by CpuCP 456 * 457 * Non-QMAN packets should be limited to values 1 through (2^8 - 1) 458 * 459 * Detailed description: 460 * 461 * CPUCP_PACKET_DISABLE_PCI_ACCESS - 462 * After receiving this packet the embedded CPU must NOT issue PCI 463 * transactions (read/write) towards the Host CPU. This also include 464 * sending MSI-X interrupts. 465 * This packet is usually sent before the device is moved to D3Hot state. 466 * 467 * CPUCP_PACKET_ENABLE_PCI_ACCESS - 468 * After receiving this packet the embedded CPU is allowed to issue PCI 469 * transactions towards the Host CPU, including sending MSI-X interrupts. 470 * This packet is usually send after the device is moved to D0 state. 471 * 472 * CPUCP_PACKET_TEMPERATURE_GET - 473 * Fetch the current temperature / Max / Max Hyst / Critical / 474 * Critical Hyst of a specified thermal sensor. The packet's 475 * arguments specify the desired sensor and the field to get. 476 * 477 * CPUCP_PACKET_VOLTAGE_GET - 478 * Fetch the voltage / Max / Min of a specified sensor. The packet's 479 * arguments specify the sensor and type. 480 * 481 * CPUCP_PACKET_CURRENT_GET - 482 * Fetch the current / Max / Min of a specified sensor. The packet's 483 * arguments specify the sensor and type. 484 * 485 * CPUCP_PACKET_FAN_SPEED_GET - 486 * Fetch the speed / Max / Min of a specified fan. The packet's 487 * arguments specify the sensor and type. 488 * 489 * CPUCP_PACKET_PWM_GET - 490 * Fetch the pwm value / mode of a specified pwm. The packet's 491 * arguments specify the sensor and type. 492 * 493 * CPUCP_PACKET_PWM_SET - 494 * Set the pwm value / mode of a specified pwm. The packet's 495 * arguments specify the sensor, type and value. 496 * 497 * CPUCP_PACKET_FREQUENCY_SET - 498 * Set the frequency of a specified PLL. The packet's arguments specify 499 * the PLL and the desired frequency. The actual frequency in the device 500 * might differ from the requested frequency. 501 * 502 * CPUCP_PACKET_FREQUENCY_GET - 503 * Fetch the frequency of a specified PLL. The packet's arguments specify 504 * the PLL. 505 * 506 * CPUCP_PACKET_LED_SET - 507 * Set the state of a specified led. The packet's arguments 508 * specify the led and the desired state. 509 * 510 * CPUCP_PACKET_I2C_WR - 511 * Write 32-bit value to I2C device. The packet's arguments specify the 512 * I2C bus, address and value. 513 * 514 * CPUCP_PACKET_I2C_RD - 515 * Read 32-bit value from I2C device. The packet's arguments specify the 516 * I2C bus and address. 517 * 518 * CPUCP_PACKET_INFO_GET - 519 * Fetch information from the device as specified in the packet's 520 * structure. The host's driver passes the max size it allows the CpuCP to 521 * write to the structure, to prevent data corruption in case of 522 * mismatched driver/FW versions. 523 * 524 * CPUCP_PACKET_FLASH_PROGRAM_REMOVED - this packet was removed 525 * 526 * CPUCP_PACKET_UNMASK_RAZWI_IRQ - 527 * Unmask the given IRQ. The IRQ number is specified in the value field. 528 * The packet is sent after receiving an interrupt and printing its 529 * relevant information. 530 * 531 * CPUCP_PACKET_UNMASK_RAZWI_IRQ_ARRAY - 532 * Unmask the given IRQs. The IRQs numbers are specified in an array right 533 * after the cpucp_packet structure, where its first element is the array 534 * length. The packet is sent after a soft reset was done in order to 535 * handle any interrupts that were sent during the reset process. 536 * 537 * CPUCP_PACKET_TEST - 538 * Test packet for CpuCP connectivity. The CPU will put the fence value 539 * in the result field. 540 * 541 * CPUCP_PACKET_FREQUENCY_CURR_GET - 542 * Fetch the current frequency of a specified PLL. The packet's arguments 543 * specify the PLL. 544 * 545 * CPUCP_PACKET_MAX_POWER_GET - 546 * Fetch the maximal power of the device. 547 * 548 * CPUCP_PACKET_MAX_POWER_SET - 549 * Set the maximal power of the device. The packet's arguments specify 550 * the power. 551 * 552 * CPUCP_PACKET_EEPROM_DATA_GET - 553 * Get EEPROM data from the CpuCP kernel. The buffer is specified in the 554 * addr field. The CPU will put the returned data size in the result 555 * field. In addition, the host's driver passes the max size it allows the 556 * CpuCP to write to the structure, to prevent data corruption in case of 557 * mismatched driver/FW versions. 558 * 559 * CPUCP_PACKET_NIC_INFO_GET - 560 * Fetch information from the device regarding the NIC. the host's driver 561 * passes the max size it allows the CpuCP to write to the structure, to 562 * prevent data corruption in case of mismatched driver/FW versions. 563 * 564 * CPUCP_PACKET_TEMPERATURE_SET - 565 * Set the value of the offset property of a specified thermal sensor. 566 * The packet's arguments specify the desired sensor and the field to 567 * set. 568 * 569 * CPUCP_PACKET_VOLTAGE_SET - 570 * Trigger the reset_history property of a specified voltage sensor. 571 * The packet's arguments specify the desired sensor and the field to 572 * set. 573 * 574 * CPUCP_PACKET_CURRENT_SET - 575 * Trigger the reset_history property of a specified current sensor. 576 * The packet's arguments specify the desired sensor and the field to 577 * set. 578 * 579 * CPUCP_PACKET_PCIE_THROUGHPUT_GET - 580 * Get throughput of PCIe. 581 * The packet's arguments specify the transaction direction (TX/RX). 582 * The window measurement is 10[msec], and the return value is in KB/sec. 583 * 584 * CPUCP_PACKET_PCIE_REPLAY_CNT_GET 585 * Replay count measures number of "replay" events, which is basicly 586 * number of retries done by PCIe. 587 * 588 * CPUCP_PACKET_TOTAL_ENERGY_GET - 589 * Total Energy is measurement of energy from the time FW Linux 590 * is loaded. It is calculated by multiplying the average power 591 * by time (passed from armcp start). The units are in MilliJouls. 592 * 593 * CPUCP_PACKET_PLL_INFO_GET - 594 * Fetch frequencies of PLL from the required PLL IP. 595 * The packet's arguments specify the device PLL type 596 * Pll type is the PLL from device pll_index enum. 597 * The result is composed of 4 outputs, each is 16-bit 598 * frequency in MHz. 599 * 600 * CPUCP_PACKET_POWER_GET - 601 * Fetch the present power consumption of the device (Current * Voltage). 602 * 603 * CPUCP_PACKET_NIC_PFC_SET - 604 * Enable/Disable the NIC PFC feature. The packet's arguments specify the 605 * NIC port, relevant lanes to configure and one bit indication for 606 * enable/disable. 607 * 608 * CPUCP_PACKET_NIC_FAULT_GET - 609 * Fetch the current indication for local/remote faults from the NIC MAC. 610 * The result is 32-bit value of the relevant register. 611 * 612 * CPUCP_PACKET_NIC_LPBK_SET - 613 * Enable/Disable the MAC loopback feature. The packet's arguments specify 614 * the NIC port, relevant lanes to configure and one bit indication for 615 * enable/disable. 616 * 617 * CPUCP_PACKET_NIC_MAC_INIT - 618 * Configure the NIC MAC channels. The packet's arguments specify the 619 * NIC port and the speed. 620 * 621 * CPUCP_PACKET_MSI_INFO_SET - 622 * set the index number for each supported msi type going from 623 * host to device 624 * 625 * CPUCP_PACKET_NIC_XPCS91_REGS_GET - 626 * Fetch the un/correctable counters values from the NIC MAC. 627 * 628 * CPUCP_PACKET_NIC_STAT_REGS_GET - 629 * Fetch various NIC MAC counters from the NIC STAT. 630 * 631 * CPUCP_PACKET_NIC_STAT_REGS_CLR - 632 * Clear the various NIC MAC counters in the NIC STAT. 633 * 634 * CPUCP_PACKET_NIC_STAT_REGS_ALL_GET - 635 * Fetch all NIC MAC counters from the NIC STAT. 636 * 637 * CPUCP_PACKET_IS_IDLE_CHECK - 638 * Check if the device is IDLE in regard to the DMA/compute engines 639 * and QMANs. The f/w will return a bitmask where each bit represents 640 * a different engine or QMAN according to enum cpucp_idle_mask. 641 * The bit will be 1 if the engine is NOT idle. 642 * 643 * CPUCP_PACKET_HBM_REPLACED_ROWS_INFO_GET - 644 * Fetch all HBM replaced-rows and prending to be replaced rows data. 645 * 646 * CPUCP_PACKET_HBM_PENDING_ROWS_STATUS - 647 * Fetch status of HBM rows pending replacement and need a reboot to 648 * be replaced. 649 * 650 * CPUCP_PACKET_POWER_SET - 651 * Resets power history of device to 0 652 * 653 * CPUCP_PACKET_ENGINE_CORE_ASID_SET - 654 * Packet to perform engine core ASID configuration 655 * 656 * CPUCP_PACKET_SEC_ATTEST_GET - 657 * Get the attestaion data that is collected during various stages of the 658 * boot sequence. the attestation data is also hashed with some unique 659 * number (nonce) provided by the host to prevent replay attacks. 660 * public key and certificate also provided as part of the FW response. 661 * 662 * CPUCP_PACKET_MONITOR_DUMP_GET - 663 * Get monitors registers dump from the CpuCP kernel. 664 * The CPU will put the registers dump in the a buffer allocated by the driver 665 * which address is passed via the CpuCp packet. In addition, the host's driver 666 * passes the max size it allows the CpuCP to write to the structure, to prevent 667 * data corruption in case of mismatched driver/FW versions. 668 * Obsolete. 669 * 670 * CPUCP_PACKET_GENERIC_PASSTHROUGH - 671 * Generic opcode for all firmware info that is only passed to host 672 * through the LKD, without getting parsed there. 673 * 674 * CPUCP_PACKET_ACTIVE_STATUS_SET - 675 * LKD sends FW indication whether device is free or in use, this indication is reported 676 * also to the BMC. 677 * 678 * CPUCP_PACKET_SOFT_RESET - 679 * Packet to perform soft-reset. 680 * 681 * CPUCP_PACKET_INTS_REGISTER - 682 * Packet to inform FW that queues have been established and LKD is ready to receive 683 * EQ events. 684 */ 685 686 enum cpucp_packet_id { 687 CPUCP_PACKET_DISABLE_PCI_ACCESS = 1, /* internal */ 688 CPUCP_PACKET_ENABLE_PCI_ACCESS, /* internal */ 689 CPUCP_PACKET_TEMPERATURE_GET, /* sysfs */ 690 CPUCP_PACKET_VOLTAGE_GET, /* sysfs */ 691 CPUCP_PACKET_CURRENT_GET, /* sysfs */ 692 CPUCP_PACKET_FAN_SPEED_GET, /* sysfs */ 693 CPUCP_PACKET_PWM_GET, /* sysfs */ 694 CPUCP_PACKET_PWM_SET, /* sysfs */ 695 CPUCP_PACKET_FREQUENCY_SET, /* sysfs */ 696 CPUCP_PACKET_FREQUENCY_GET, /* sysfs */ 697 CPUCP_PACKET_LED_SET, /* debugfs */ 698 CPUCP_PACKET_I2C_WR, /* debugfs */ 699 CPUCP_PACKET_I2C_RD, /* debugfs */ 700 CPUCP_PACKET_INFO_GET, /* IOCTL */ 701 CPUCP_PACKET_FLASH_PROGRAM_REMOVED, 702 CPUCP_PACKET_UNMASK_RAZWI_IRQ, /* internal */ 703 CPUCP_PACKET_UNMASK_RAZWI_IRQ_ARRAY, /* internal */ 704 CPUCP_PACKET_TEST, /* internal */ 705 CPUCP_PACKET_FREQUENCY_CURR_GET, /* sysfs */ 706 CPUCP_PACKET_MAX_POWER_GET, /* sysfs */ 707 CPUCP_PACKET_MAX_POWER_SET, /* sysfs */ 708 CPUCP_PACKET_EEPROM_DATA_GET, /* sysfs */ 709 CPUCP_PACKET_NIC_INFO_GET, /* internal */ 710 CPUCP_PACKET_TEMPERATURE_SET, /* sysfs */ 711 CPUCP_PACKET_VOLTAGE_SET, /* sysfs */ 712 CPUCP_PACKET_CURRENT_SET, /* sysfs */ 713 CPUCP_PACKET_PCIE_THROUGHPUT_GET, /* internal */ 714 CPUCP_PACKET_PCIE_REPLAY_CNT_GET, /* internal */ 715 CPUCP_PACKET_TOTAL_ENERGY_GET, /* internal */ 716 CPUCP_PACKET_PLL_INFO_GET, /* internal */ 717 CPUCP_PACKET_NIC_STATUS, /* internal */ 718 CPUCP_PACKET_POWER_GET, /* internal */ 719 CPUCP_PACKET_NIC_PFC_SET, /* internal */ 720 CPUCP_PACKET_NIC_FAULT_GET, /* internal */ 721 CPUCP_PACKET_NIC_LPBK_SET, /* internal */ 722 CPUCP_PACKET_NIC_MAC_CFG, /* internal */ 723 CPUCP_PACKET_MSI_INFO_SET, /* internal */ 724 CPUCP_PACKET_NIC_XPCS91_REGS_GET, /* internal */ 725 CPUCP_PACKET_NIC_STAT_REGS_GET, /* internal */ 726 CPUCP_PACKET_NIC_STAT_REGS_CLR, /* internal */ 727 CPUCP_PACKET_NIC_STAT_REGS_ALL_GET, /* internal */ 728 CPUCP_PACKET_IS_IDLE_CHECK, /* internal */ 729 CPUCP_PACKET_HBM_REPLACED_ROWS_INFO_GET,/* internal */ 730 CPUCP_PACKET_HBM_PENDING_ROWS_STATUS, /* internal */ 731 CPUCP_PACKET_POWER_SET, /* internal */ 732 CPUCP_PACKET_RESERVED, /* not used */ 733 CPUCP_PACKET_ENGINE_CORE_ASID_SET, /* internal */ 734 CPUCP_PACKET_RESERVED2, /* not used */ 735 CPUCP_PACKET_SEC_ATTEST_GET, /* internal */ 736 CPUCP_PACKET_RESERVED3, /* not used */ 737 CPUCP_PACKET_RESERVED4, /* not used */ 738 CPUCP_PACKET_MONITOR_DUMP_GET, /* debugfs */ 739 CPUCP_PACKET_RESERVED5, /* not used */ 740 CPUCP_PACKET_RESERVED6, /* not used */ 741 CPUCP_PACKET_RESERVED7, /* not used */ 742 CPUCP_PACKET_GENERIC_PASSTHROUGH, /* IOCTL */ 743 CPUCP_PACKET_RESERVED8, /* not used */ 744 CPUCP_PACKET_ACTIVE_STATUS_SET, /* internal */ 745 CPUCP_PACKET_RESERVED9, /* not used */ 746 CPUCP_PACKET_RESERVED10, /* not used */ 747 CPUCP_PACKET_RESERVED11, /* not used */ 748 CPUCP_PACKET_RESERVED12, /* internal */ 749 CPUCP_PACKET_RESERVED13, /* internal */ 750 CPUCP_PACKET_SOFT_RESET, /* internal */ 751 CPUCP_PACKET_INTS_REGISTER, /* internal */ 752 CPUCP_PACKET_ID_MAX /* must be last */ 753 }; 754 755 #define CPUCP_PACKET_FENCE_VAL 0xFE8CE7A5 756 757 #define CPUCP_PKT_CTL_RC_SHIFT 12 758 #define CPUCP_PKT_CTL_RC_MASK 0x0000F000 759 760 #define CPUCP_PKT_CTL_OPCODE_SHIFT 16 761 #define CPUCP_PKT_CTL_OPCODE_MASK 0x1FFF0000 762 763 #define CPUCP_PKT_RES_PLL_OUT0_SHIFT 0 764 #define CPUCP_PKT_RES_PLL_OUT0_MASK 0x000000000000FFFFull 765 #define CPUCP_PKT_RES_PLL_OUT1_SHIFT 16 766 #define CPUCP_PKT_RES_PLL_OUT1_MASK 0x00000000FFFF0000ull 767 #define CPUCP_PKT_RES_PLL_OUT2_SHIFT 32 768 #define CPUCP_PKT_RES_PLL_OUT2_MASK 0x0000FFFF00000000ull 769 #define CPUCP_PKT_RES_PLL_OUT3_SHIFT 48 770 #define CPUCP_PKT_RES_PLL_OUT3_MASK 0xFFFF000000000000ull 771 772 #define CPUCP_PKT_RES_EEPROM_OUT0_SHIFT 0 773 #define CPUCP_PKT_RES_EEPROM_OUT0_MASK 0x000000000000FFFFull 774 #define CPUCP_PKT_RES_EEPROM_OUT1_SHIFT 16 775 #define CPUCP_PKT_RES_EEPROM_OUT1_MASK 0x0000000000FF0000ull 776 777 #define CPUCP_PKT_VAL_PFC_IN1_SHIFT 0 778 #define CPUCP_PKT_VAL_PFC_IN1_MASK 0x0000000000000001ull 779 #define CPUCP_PKT_VAL_PFC_IN2_SHIFT 1 780 #define CPUCP_PKT_VAL_PFC_IN2_MASK 0x000000000000001Eull 781 782 #define CPUCP_PKT_VAL_LPBK_IN1_SHIFT 0 783 #define CPUCP_PKT_VAL_LPBK_IN1_MASK 0x0000000000000001ull 784 #define CPUCP_PKT_VAL_LPBK_IN2_SHIFT 1 785 #define CPUCP_PKT_VAL_LPBK_IN2_MASK 0x000000000000001Eull 786 787 #define CPUCP_PKT_VAL_MAC_CNT_IN1_SHIFT 0 788 #define CPUCP_PKT_VAL_MAC_CNT_IN1_MASK 0x0000000000000001ull 789 #define CPUCP_PKT_VAL_MAC_CNT_IN2_SHIFT 1 790 #define CPUCP_PKT_VAL_MAC_CNT_IN2_MASK 0x00000000FFFFFFFEull 791 792 /* heartbeat status bits */ 793 #define CPUCP_PKT_HB_STATUS_EQ_FAULT_SHIFT 0 794 #define CPUCP_PKT_HB_STATUS_EQ_FAULT_MASK 0x00000001 795 796 struct cpucp_packet { 797 union { 798 __le64 value; /* For SET packets */ 799 __le64 result; /* For GET packets */ 800 __le64 addr; /* For PQ */ 801 }; 802 803 __le32 ctl; 804 805 __le32 fence; /* Signal to host that message is completed */ 806 807 union { 808 struct {/* For temperature/current/voltage/fan/pwm get/set */ 809 __le16 sensor_index; 810 __le16 type; 811 }; 812 813 struct { /* For I2C read/write */ 814 __u8 i2c_bus; 815 __u8 i2c_addr; 816 __u8 i2c_reg; 817 /* 818 * In legacy implemetations, i2c_len was not present, 819 * was unused and just added as pad. 820 * So if i2c_len is 0, it is treated as legacy 821 * and r/w 1 Byte, else if i2c_len is specified, 822 * its treated as new multibyte r/w support. 823 */ 824 __u8 i2c_len; 825 }; 826 827 struct {/* For PLL info fetch */ 828 __le16 pll_type; 829 /* TODO pll_reg is kept temporary before removal */ 830 __le16 pll_reg; 831 }; 832 833 /* For any general request */ 834 __le32 index; 835 836 /* For frequency get/set */ 837 __le32 pll_index; 838 839 /* For led set */ 840 __le32 led_index; 841 842 /* For get CpuCP info/EEPROM data/NIC info */ 843 __le32 data_max_size; 844 845 /* 846 * For any general status bitmask. Shall be used whenever the 847 * result cannot be used to hold general purpose data. 848 */ 849 __le32 status_mask; 850 851 /* random, used once number, for security packets */ 852 __le32 nonce; 853 }; 854 855 union { 856 /* For NIC requests */ 857 __le32 port_index; 858 859 /* For Generic packet sub index */ 860 __le32 pkt_subidx; 861 }; 862 }; 863 864 struct cpucp_unmask_irq_arr_packet { 865 struct cpucp_packet cpucp_pkt; 866 __le32 length; 867 __le32 irqs[]; 868 }; 869 870 struct cpucp_nic_status_packet { 871 struct cpucp_packet cpucp_pkt; 872 __le32 length; 873 __le32 data[]; 874 }; 875 876 struct cpucp_array_data_packet { 877 struct cpucp_packet cpucp_pkt; 878 __le32 length; 879 __le32 data[]; 880 }; 881 882 enum cpucp_led_index { 883 CPUCP_LED0_INDEX = 0, 884 CPUCP_LED1_INDEX, 885 CPUCP_LED2_INDEX, 886 CPUCP_LED_MAX_INDEX = CPUCP_LED2_INDEX 887 }; 888 889 /* 890 * enum cpucp_packet_rc - Error return code 891 * @cpucp_packet_success -> in case of success. 892 * @cpucp_packet_invalid -> this is to support first generation platforms. 893 * @cpucp_packet_fault -> in case of processing error like failing to 894 * get device binding or semaphore etc. 895 * @cpucp_packet_invalid_pkt -> when cpucp packet is un-supported. 896 * @cpucp_packet_invalid_params -> when checking parameter like length of buffer 897 * or attribute value etc. 898 * @cpucp_packet_rc_max -> It indicates size of enum so should be at last. 899 */ 900 enum cpucp_packet_rc { 901 cpucp_packet_success, 902 cpucp_packet_invalid, 903 cpucp_packet_fault, 904 cpucp_packet_invalid_pkt, 905 cpucp_packet_invalid_params, 906 cpucp_packet_rc_max 907 }; 908 909 /* 910 * cpucp_temp_type should adhere to hwmon_temp_attributes 911 * defined in Linux kernel hwmon.h file 912 */ 913 enum cpucp_temp_type { 914 cpucp_temp_input, 915 cpucp_temp_min = 4, 916 cpucp_temp_min_hyst, 917 cpucp_temp_max = 6, 918 cpucp_temp_max_hyst, 919 cpucp_temp_crit, 920 cpucp_temp_crit_hyst, 921 cpucp_temp_offset = 19, 922 cpucp_temp_lowest = 21, 923 cpucp_temp_highest = 22, 924 cpucp_temp_reset_history = 23, 925 cpucp_temp_warn = 24, 926 cpucp_temp_max_crit = 25, 927 cpucp_temp_max_warn = 26, 928 }; 929 930 enum cpucp_in_attributes { 931 cpucp_in_input, 932 cpucp_in_min, 933 cpucp_in_max, 934 cpucp_in_lowest = 6, 935 cpucp_in_highest = 7, 936 cpucp_in_reset_history, 937 cpucp_in_intr_alarm_a, 938 cpucp_in_intr_alarm_b, 939 }; 940 941 enum cpucp_curr_attributes { 942 cpucp_curr_input, 943 cpucp_curr_min, 944 cpucp_curr_max, 945 cpucp_curr_lowest = 6, 946 cpucp_curr_highest = 7, 947 cpucp_curr_reset_history 948 }; 949 950 enum cpucp_fan_attributes { 951 cpucp_fan_input, 952 cpucp_fan_min = 2, 953 cpucp_fan_max 954 }; 955 956 enum cpucp_pwm_attributes { 957 cpucp_pwm_input, 958 cpucp_pwm_enable 959 }; 960 961 enum cpucp_pcie_throughput_attributes { 962 cpucp_pcie_throughput_tx, 963 cpucp_pcie_throughput_rx 964 }; 965 966 /* TODO temporary kept before removal */ 967 enum cpucp_pll_reg_attributes { 968 cpucp_pll_nr_reg, 969 cpucp_pll_nf_reg, 970 cpucp_pll_od_reg, 971 cpucp_pll_div_factor_reg, 972 cpucp_pll_div_sel_reg 973 }; 974 975 /* TODO temporary kept before removal */ 976 enum cpucp_pll_type_attributes { 977 cpucp_pll_cpu, 978 cpucp_pll_pci, 979 }; 980 981 /* 982 * cpucp_power_type aligns with hwmon_power_attributes 983 * defined in Linux kernel hwmon.h file 984 */ 985 enum cpucp_power_type { 986 CPUCP_POWER_INPUT = 8, 987 CPUCP_POWER_INPUT_HIGHEST = 9, 988 CPUCP_POWER_RESET_INPUT_HISTORY = 11 989 }; 990 991 /* 992 * MSI type enumeration table for all ASICs and future SW versions. 993 * For future ASIC-LKD compatibility, we can only add new enumerations. 994 * at the end of the table (before CPUCP_NUM_OF_MSI_TYPES). 995 * Changing the order of entries or removing entries is not allowed. 996 */ 997 enum cpucp_msi_type { 998 CPUCP_EVENT_QUEUE_MSI_TYPE, 999 CPUCP_NIC_PORT1_MSI_TYPE, 1000 CPUCP_NIC_PORT3_MSI_TYPE, 1001 CPUCP_NIC_PORT5_MSI_TYPE, 1002 CPUCP_NIC_PORT7_MSI_TYPE, 1003 CPUCP_NIC_PORT9_MSI_TYPE, 1004 CPUCP_EVENT_QUEUE_ERR_MSI_TYPE, 1005 CPUCP_NUM_OF_MSI_TYPES 1006 }; 1007 1008 /* 1009 * PLL enumeration table used for all ASICs and future SW versions. 1010 * For future ASIC-LKD compatibility, we can only add new enumerations. 1011 * at the end of the table. 1012 * Changing the order of entries or removing entries is not allowed. 1013 */ 1014 enum pll_index { 1015 CPU_PLL = 0, 1016 PCI_PLL = 1, 1017 NIC_PLL = 2, 1018 DMA_PLL = 3, 1019 MESH_PLL = 4, 1020 MME_PLL = 5, 1021 TPC_PLL = 6, 1022 IF_PLL = 7, 1023 SRAM_PLL = 8, 1024 NS_PLL = 9, 1025 HBM_PLL = 10, 1026 MSS_PLL = 11, 1027 DDR_PLL = 12, 1028 VID_PLL = 13, 1029 BANK_PLL = 14, 1030 MMU_PLL = 15, 1031 IC_PLL = 16, 1032 MC_PLL = 17, 1033 EMMC_PLL = 18, 1034 D2D_PLL = 19, 1035 CS_PLL = 20, 1036 C2C_PLL = 21, 1037 NCH_PLL = 22, 1038 C2M_PLL = 23, 1039 PLL_MAX 1040 }; 1041 1042 enum rl_index { 1043 TPC_RL = 0, 1044 MME_RL, 1045 EDMA_RL, 1046 }; 1047 1048 enum pvt_index { 1049 PVT_SW, 1050 PVT_SE, 1051 PVT_NW, 1052 PVT_NE 1053 }; 1054 1055 /* Event Queue Packets */ 1056 1057 struct eq_generic_event { 1058 __le64 data[7]; 1059 }; 1060 1061 /* 1062 * CpuCP info 1063 */ 1064 1065 #define CARD_NAME_MAX_LEN 16 1066 #define CPUCP_MAX_SENSORS 128 1067 #define CPUCP_MAX_NICS 128 1068 #define CPUCP_LANES_PER_NIC 4 1069 #define CPUCP_NIC_QSFP_EEPROM_MAX_LEN 1024 1070 #define CPUCP_MAX_NIC_LANES (CPUCP_MAX_NICS * CPUCP_LANES_PER_NIC) 1071 #define CPUCP_NIC_MASK_ARR_LEN ((CPUCP_MAX_NICS + 63) / 64) 1072 #define CPUCP_NIC_POLARITY_ARR_LEN ((CPUCP_MAX_NIC_LANES + 63) / 64) 1073 #define CPUCP_HBM_ROW_REPLACE_MAX 32 1074 1075 struct cpucp_sensor { 1076 __le32 type; 1077 __le32 flags; 1078 }; 1079 1080 /** 1081 * struct cpucp_card_types - ASIC card type. 1082 * @cpucp_card_type_pci: PCI card. 1083 * @cpucp_card_type_pmc: PCI Mezzanine Card. 1084 */ 1085 enum cpucp_card_types { 1086 cpucp_card_type_pci, 1087 cpucp_card_type_pmc 1088 }; 1089 1090 #define CPUCP_SEC_CONF_ENABLED_SHIFT 0 1091 #define CPUCP_SEC_CONF_ENABLED_MASK 0x00000001 1092 1093 #define CPUCP_SEC_CONF_FLASH_WP_SHIFT 1 1094 #define CPUCP_SEC_CONF_FLASH_WP_MASK 0x00000002 1095 1096 #define CPUCP_SEC_CONF_EEPROM_WP_SHIFT 2 1097 #define CPUCP_SEC_CONF_EEPROM_WP_MASK 0x00000004 1098 1099 /** 1100 * struct cpucp_security_info - Security information. 1101 * @config: configuration bit field 1102 * @keys_num: number of stored keys 1103 * @revoked_keys: revoked keys bit field 1104 * @min_svn: minimal security version 1105 */ 1106 struct cpucp_security_info { 1107 __u8 config; 1108 __u8 keys_num; 1109 __u8 revoked_keys; 1110 __u8 min_svn; 1111 }; 1112 1113 /** 1114 * struct cpucp_info - Info from CpuCP that is necessary to the host's driver 1115 * @sensors: available sensors description. 1116 * @kernel_version: CpuCP linux kernel version. 1117 * @reserved: reserved field. 1118 * @card_type: card configuration type. 1119 * @card_location: in a server, each card has different connections topology 1120 * depending on its location (relevant for PMC card type) 1121 * @cpld_version: CPLD programmed F/W version. 1122 * @infineon_version: Infineon main DC-DC version. 1123 * @fuse_version: silicon production FUSE information. 1124 * @thermal_version: thermald S/W version. 1125 * @cpucp_version: CpuCP S/W version. 1126 * @infineon_second_stage_version: Infineon 2nd stage DC-DC version. 1127 * @dram_size: available DRAM size. 1128 * @card_name: card name that will be displayed in HWMON subsystem on the host 1129 * @tpc_binning_mask: TPC binning mask, 1 bit per TPC instance 1130 * (0 = functional, 1 = binned) 1131 * @decoder_binning_mask: Decoder binning mask, 1 bit per decoder instance 1132 * (0 = functional, 1 = binned), maximum 1 per dcore 1133 * @sram_binning: Categorize SRAM functionality 1134 * (0 = fully functional, 1 = lower-half is not functional, 1135 * 2 = upper-half is not functional) 1136 * @sec_info: security information 1137 * @pll_map: Bit map of supported PLLs for current ASIC version. 1138 * @mme_binning_mask: MME binning mask, 1139 * bits [0:6] <==> dcore0 mme fma 1140 * bits [7:13] <==> dcore1 mme fma 1141 * bits [14:20] <==> dcore0 mme ima 1142 * bits [21:27] <==> dcore1 mme ima 1143 * For each group, if the 6th bit is set then first 5 bits 1144 * represent the col's idx [0-31], otherwise these bits are 1145 * ignored, and col idx 32 is binned. 7th bit is don't care. 1146 * @dram_binning_mask: DRAM binning mask, 1 bit per dram instance 1147 * (0 = functional 1 = binned) 1148 * @memory_repair_flag: eFuse flag indicating memory repair 1149 * @edma_binning_mask: EDMA binning mask, 1 bit per EDMA instance 1150 * (0 = functional 1 = binned) 1151 * @xbar_binning_mask: Xbar binning mask, 1 bit per Xbar instance 1152 * (0 = functional 1 = binned) 1153 * @interposer_version: Interposer version programmed in eFuse 1154 * @substrate_version: Substrate version programmed in eFuse 1155 * @eq_health_check_supported: eq health check feature supported in FW. 1156 * @fw_hbm_region_size: Size in bytes of FW reserved region in HBM. 1157 * @fw_os_version: Firmware OS Version 1158 */ 1159 struct cpucp_info { 1160 struct cpucp_sensor sensors[CPUCP_MAX_SENSORS]; 1161 __u8 kernel_version[VERSION_MAX_LEN]; 1162 __le32 reserved; 1163 __le32 card_type; 1164 __le32 card_location; 1165 __le32 cpld_version; 1166 __le32 infineon_version; 1167 __u8 fuse_version[VERSION_MAX_LEN]; 1168 __u8 thermal_version[VERSION_MAX_LEN]; 1169 __u8 cpucp_version[VERSION_MAX_LEN]; 1170 __le32 infineon_second_stage_version; 1171 __le64 dram_size; 1172 char card_name[CARD_NAME_MAX_LEN]; 1173 __le64 tpc_binning_mask; 1174 __le64 decoder_binning_mask; 1175 __u8 sram_binning; 1176 __u8 dram_binning_mask; 1177 __u8 memory_repair_flag; 1178 __u8 edma_binning_mask; 1179 __u8 xbar_binning_mask; 1180 __u8 interposer_version; 1181 __u8 substrate_version; 1182 __u8 eq_health_check_supported; 1183 struct cpucp_security_info sec_info; 1184 __le32 fw_hbm_region_size; 1185 __u8 pll_map[PLL_MAP_LEN]; 1186 __le64 mme_binning_mask; 1187 __u8 fw_os_version[VERSION_MAX_LEN]; 1188 }; 1189 1190 struct cpucp_mac_addr { 1191 __u8 mac_addr[ETH_ALEN]; 1192 }; 1193 1194 enum cpucp_serdes_type { 1195 TYPE_1_SERDES_TYPE, 1196 TYPE_2_SERDES_TYPE, 1197 HLS1_SERDES_TYPE, 1198 HLS1H_SERDES_TYPE, 1199 HLS2_SERDES_TYPE, 1200 HLS2_TYPE_1_SERDES_TYPE, 1201 MAX_NUM_SERDES_TYPE, /* number of types */ 1202 UNKNOWN_SERDES_TYPE = 0xFFFF /* serdes_type is u16 */ 1203 }; 1204 1205 struct cpucp_nic_info { 1206 struct cpucp_mac_addr mac_addrs[CPUCP_MAX_NICS]; 1207 __le64 link_mask[CPUCP_NIC_MASK_ARR_LEN]; 1208 __le64 pol_tx_mask[CPUCP_NIC_POLARITY_ARR_LEN]; 1209 __le64 pol_rx_mask[CPUCP_NIC_POLARITY_ARR_LEN]; 1210 __le64 link_ext_mask[CPUCP_NIC_MASK_ARR_LEN]; 1211 __u8 qsfp_eeprom[CPUCP_NIC_QSFP_EEPROM_MAX_LEN]; 1212 __le64 auto_neg_mask[CPUCP_NIC_MASK_ARR_LEN]; 1213 __le16 serdes_type; /* enum cpucp_serdes_type */ 1214 __le16 tx_swap_map[CPUCP_MAX_NICS]; 1215 __u8 reserved[6]; 1216 }; 1217 1218 #define PAGE_DISCARD_MAX 64 1219 1220 struct page_discard_info { 1221 __u8 num_entries; 1222 __u8 reserved[7]; 1223 __le32 mmu_page_idx[PAGE_DISCARD_MAX]; 1224 }; 1225 1226 /* 1227 * struct frac_val - fracture value represented by "integer.frac". 1228 * @integer: the integer part of the fracture value; 1229 * @frac: the fracture part of the fracture value. 1230 */ 1231 struct frac_val { 1232 union { 1233 struct { 1234 __le16 integer; 1235 __le16 frac; 1236 }; 1237 __le32 val; 1238 }; 1239 }; 1240 1241 /* 1242 * struct ser_val - the SER (symbol error rate) value is represented by "integer * 10 ^ -exp". 1243 * @integer: the integer part of the SER value; 1244 * @exp: the exponent part of the SER value. 1245 */ 1246 struct ser_val { 1247 __le16 integer; 1248 __le16 exp; 1249 }; 1250 1251 /* 1252 * struct cpucp_nic_status - describes the status of a NIC port. 1253 * @port: NIC port index. 1254 * @bad_format_cnt: e.g. CRC. 1255 * @responder_out_of_sequence_psn_cnt: e.g NAK. 1256 * @high_ber_reinit_cnt: link reinit due to high BER. 1257 * @correctable_err_cnt: e.g. bit-flip. 1258 * @uncorrectable_err_cnt: e.g. MAC errors. 1259 * @retraining_cnt: re-training counter. 1260 * @up: is port up. 1261 * @pcs_link: has PCS link. 1262 * @phy_ready: is PHY ready. 1263 * @auto_neg: is Autoneg enabled. 1264 * @timeout_retransmission_cnt: timeout retransmission events. 1265 * @high_ber_cnt: high ber events. 1266 * @pre_fec_ser: pre FEC SER value. 1267 * @post_fec_ser: post FEC SER value. 1268 * @throughput: measured throughput. 1269 * @latency: measured latency. 1270 */ 1271 struct cpucp_nic_status { 1272 __le32 port; 1273 __le32 bad_format_cnt; 1274 __le32 responder_out_of_sequence_psn_cnt; 1275 __le32 high_ber_reinit; 1276 __le32 correctable_err_cnt; 1277 __le32 uncorrectable_err_cnt; 1278 __le32 retraining_cnt; 1279 __u8 up; 1280 __u8 pcs_link; 1281 __u8 phy_ready; 1282 __u8 auto_neg; 1283 __le32 timeout_retransmission_cnt; 1284 __le32 high_ber_cnt; 1285 struct ser_val pre_fec_ser; 1286 struct ser_val post_fec_ser; 1287 struct frac_val bandwidth; 1288 struct frac_val lat; 1289 }; 1290 1291 enum cpucp_hbm_row_replace_cause { 1292 REPLACE_CAUSE_DOUBLE_ECC_ERR, 1293 REPLACE_CAUSE_MULTI_SINGLE_ECC_ERR, 1294 }; 1295 1296 struct cpucp_hbm_row_info { 1297 __u8 hbm_idx; 1298 __u8 pc; 1299 __u8 sid; 1300 __u8 bank_idx; 1301 __le16 row_addr; 1302 __u8 replaced_row_cause; /* enum cpucp_hbm_row_replace_cause */ 1303 __u8 pad; 1304 }; 1305 1306 struct cpucp_hbm_row_replaced_rows_info { 1307 __le16 num_replaced_rows; 1308 __u8 pad[6]; 1309 struct cpucp_hbm_row_info replaced_rows[CPUCP_HBM_ROW_REPLACE_MAX]; 1310 }; 1311 1312 enum cpu_reset_status { 1313 CPU_RST_STATUS_NA = 0, 1314 CPU_RST_STATUS_SOFT_RST_DONE = 1, 1315 }; 1316 1317 #define SEC_PCR_DATA_BUF_SZ 256 1318 #define SEC_PCR_QUOTE_BUF_SZ 510 /* (512 - 2) 2 bytes used for size */ 1319 #define SEC_SIGNATURE_BUF_SZ 255 /* (256 - 1) 1 byte used for size */ 1320 #define SEC_PUB_DATA_BUF_SZ 510 /* (512 - 2) 2 bytes used for size */ 1321 #define SEC_CERTIFICATE_BUF_SZ 2046 /* (2048 - 2) 2 bytes used for size */ 1322 1323 /* 1324 * struct cpucp_sec_attest_info - attestation report of the boot 1325 * @pcr_data: raw values of the PCR registers 1326 * @pcr_num_reg: number of PCR registers in the pcr_data array 1327 * @pcr_reg_len: length of each PCR register in the pcr_data array (bytes) 1328 * @nonce: number only used once. random number provided by host. this also 1329 * passed to the quote command as a qualifying data. 1330 * @pcr_quote_len: length of the attestation quote data (bytes) 1331 * @pcr_quote: attestation report data structure 1332 * @quote_sig_len: length of the attestation report signature (bytes) 1333 * @quote_sig: signature structure of the attestation report 1334 * @pub_data_len: length of the public data (bytes) 1335 * @public_data: public key for the signed attestation 1336 * (outPublic + name + qualifiedName) 1337 * @certificate_len: length of the certificate (bytes) 1338 * @certificate: certificate for the attestation signing key 1339 */ 1340 struct cpucp_sec_attest_info { 1341 __u8 pcr_data[SEC_PCR_DATA_BUF_SZ]; 1342 __u8 pcr_num_reg; 1343 __u8 pcr_reg_len; 1344 __le16 pad0; 1345 __le32 nonce; 1346 __le16 pcr_quote_len; 1347 __u8 pcr_quote[SEC_PCR_QUOTE_BUF_SZ]; 1348 __u8 quote_sig_len; 1349 __u8 quote_sig[SEC_SIGNATURE_BUF_SZ]; 1350 __le16 pub_data_len; 1351 __u8 public_data[SEC_PUB_DATA_BUF_SZ]; 1352 __le16 certificate_len; 1353 __u8 certificate[SEC_CERTIFICATE_BUF_SZ]; 1354 }; 1355 1356 /* 1357 * struct cpucp_dev_info_signed - device information signed by a secured device 1358 * @info: device information structure as defined above 1359 * @nonce: number only used once. random number provided by host. this number is 1360 * hashed and signed along with the device information. 1361 * @info_sig_len: length of the attestation signature (bytes) 1362 * @info_sig: signature of the info + nonce data. 1363 * @pub_data_len: length of the public data (bytes) 1364 * @public_data: public key info signed info data 1365 * (outPublic + name + qualifiedName) 1366 * @certificate_len: length of the certificate (bytes) 1367 * @certificate: certificate for the signing key 1368 */ 1369 struct cpucp_dev_info_signed { 1370 struct cpucp_info info; /* assumed to be 64bit aligned */ 1371 __le32 nonce; 1372 __le32 pad0; 1373 __u8 info_sig_len; 1374 __u8 info_sig[SEC_SIGNATURE_BUF_SZ]; 1375 __le16 pub_data_len; 1376 __u8 public_data[SEC_PUB_DATA_BUF_SZ]; 1377 __le16 certificate_len; 1378 __u8 certificate[SEC_CERTIFICATE_BUF_SZ]; 1379 }; 1380 1381 #define DCORE_MON_REGS_SZ 512 1382 /* 1383 * struct dcore_monitor_regs_data - DCORE monitor regs data. 1384 * the structure follows sync manager block layout. Obsolete. 1385 * @mon_pay_addrl: array of payload address low bits. 1386 * @mon_pay_addrh: array of payload address high bits. 1387 * @mon_pay_data: array of payload data. 1388 * @mon_arm: array of monitor arm. 1389 * @mon_status: array of monitor status. 1390 */ 1391 struct dcore_monitor_regs_data { 1392 __le32 mon_pay_addrl[DCORE_MON_REGS_SZ]; 1393 __le32 mon_pay_addrh[DCORE_MON_REGS_SZ]; 1394 __le32 mon_pay_data[DCORE_MON_REGS_SZ]; 1395 __le32 mon_arm[DCORE_MON_REGS_SZ]; 1396 __le32 mon_status[DCORE_MON_REGS_SZ]; 1397 }; 1398 1399 /* contains SM data for each SYNC_MNGR (Obsolete) */ 1400 struct cpucp_monitor_dump { 1401 struct dcore_monitor_regs_data sync_mngr_w_s; 1402 struct dcore_monitor_regs_data sync_mngr_e_s; 1403 struct dcore_monitor_regs_data sync_mngr_w_n; 1404 struct dcore_monitor_regs_data sync_mngr_e_n; 1405 }; 1406 1407 /* 1408 * The Type of the generic request (and other input arguments) will be fetched from user by reading 1409 * from "pkt_subidx" field in struct cpucp_packet. 1410 * 1411 * HL_PASSTHROUGHT_VERSIONS - Fetch all firmware versions. 1412 */ 1413 enum hl_passthrough_type { 1414 HL_PASSTHROUGH_VERSIONS, 1415 }; 1416 1417 #endif /* CPUCP_IF_H */ 1418