1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2019 HiSilicon Limited. */ 3 #ifndef HISI_ACC_QM_H 4 #define HISI_ACC_QM_H 5 6 #include <linux/bitfield.h> 7 #include <linux/debugfs.h> 8 #include <linux/iopoll.h> 9 #include <linux/module.h> 10 #include <linux/pci.h> 11 12 #define QM_QNUM_V1 4096 13 #define QM_QNUM_V2 1024 14 #define QM_MAX_VFS_NUM_V2 63 15 16 /* qm user domain */ 17 #define QM_ARUSER_M_CFG_1 0x100088 18 #define AXUSER_SNOOP_ENABLE BIT(30) 19 #define AXUSER_CMD_TYPE GENMASK(14, 12) 20 #define AXUSER_CMD_SMMU_NORMAL 1 21 #define AXUSER_NS BIT(6) 22 #define AXUSER_NO BIT(5) 23 #define AXUSER_FP BIT(4) 24 #define AXUSER_SSV BIT(0) 25 #define AXUSER_BASE (AXUSER_SNOOP_ENABLE | \ 26 FIELD_PREP(AXUSER_CMD_TYPE, \ 27 AXUSER_CMD_SMMU_NORMAL) | \ 28 AXUSER_NS | AXUSER_NO | AXUSER_FP) 29 #define QM_ARUSER_M_CFG_ENABLE 0x100090 30 #define ARUSER_M_CFG_ENABLE 0xfffffffe 31 #define QM_AWUSER_M_CFG_1 0x100098 32 #define QM_AWUSER_M_CFG_ENABLE 0x1000a0 33 #define AWUSER_M_CFG_ENABLE 0xfffffffe 34 #define QM_WUSER_M_CFG_ENABLE 0x1000a8 35 #define WUSER_M_CFG_ENABLE 0xffffffff 36 37 /* mailbox */ 38 #define QM_MB_CMD_SQC 0x0 39 #define QM_MB_CMD_CQC 0x1 40 #define QM_MB_CMD_EQC 0x2 41 #define QM_MB_CMD_AEQC 0x3 42 #define QM_MB_CMD_SQC_BT 0x4 43 #define QM_MB_CMD_CQC_BT 0x5 44 #define QM_MB_CMD_SQC_VFT_V2 0x6 45 #define QM_MB_CMD_STOP_QP 0x8 46 #define QM_MB_CMD_SRC 0xc 47 #define QM_MB_CMD_DST 0xd 48 49 #define QM_MB_CMD_SEND_BASE 0x300 50 #define QM_MB_EVENT_SHIFT 8 51 #define QM_MB_BUSY_SHIFT 13 52 #define QM_MB_OP_SHIFT 14 53 #define QM_MB_CMD_DATA_ADDR_L 0x304 54 #define QM_MB_CMD_DATA_ADDR_H 0x308 55 #define QM_MB_MAX_WAIT_CNT 6000 56 57 /* doorbell */ 58 #define QM_DOORBELL_CMD_SQ 0 59 #define QM_DOORBELL_CMD_CQ 1 60 #define QM_DOORBELL_CMD_EQ 2 61 #define QM_DOORBELL_CMD_AEQ 3 62 63 #define QM_DOORBELL_SQ_CQ_BASE_V2 0x1000 64 #define QM_DOORBELL_EQ_AEQ_BASE_V2 0x2000 65 #define QM_QP_MAX_NUM_SHIFT 11 66 #define QM_DB_CMD_SHIFT_V2 12 67 #define QM_DB_RAND_SHIFT_V2 16 68 #define QM_DB_INDEX_SHIFT_V2 32 69 #define QM_DB_PRIORITY_SHIFT_V2 48 70 #define QM_VF_STATE 0x60 71 72 /* qm cache */ 73 #define QM_CACHE_CTL 0x100050 74 #define SQC_CACHE_ENABLE BIT(0) 75 #define CQC_CACHE_ENABLE BIT(1) 76 #define SQC_CACHE_WB_ENABLE BIT(4) 77 #define SQC_CACHE_WB_THRD GENMASK(10, 5) 78 #define CQC_CACHE_WB_ENABLE BIT(11) 79 #define CQC_CACHE_WB_THRD GENMASK(17, 12) 80 #define QM_AXI_M_CFG 0x1000ac 81 #define AXI_M_CFG 0xffff 82 #define QM_AXI_M_CFG_ENABLE 0x1000b0 83 #define AM_CFG_SINGLE_PORT_MAX_TRANS 0x300014 84 #define AXI_M_CFG_ENABLE 0xffffffff 85 #define QM_PEH_AXUSER_CFG 0x1000cc 86 #define QM_PEH_AXUSER_CFG_ENABLE 0x1000d0 87 #define PEH_AXUSER_CFG 0x401001 88 #define PEH_AXUSER_CFG_ENABLE 0xffffffff 89 90 #define QM_MIN_QNUM 2 91 #define HISI_ACC_SGL_SGE_NR_MAX 255 92 #define QM_SHAPER_CFG 0x100164 93 #define QM_SHAPER_ENABLE BIT(30) 94 #define QM_SHAPER_TYPE1_OFFSET 10 95 96 /* page number for queue file region */ 97 #define QM_DOORBELL_PAGE_NR 1 98 99 /* uacce mode of the driver */ 100 #define UACCE_MODE_NOUACCE 0 /* don't use uacce */ 101 #define UACCE_MODE_SVA 1 /* use uacce sva mode */ 102 #define UACCE_MODE_DESC "0(default) means only register to crypto, 1 means both register to crypto and uacce" 103 104 enum qm_stop_reason { 105 QM_NORMAL, 106 QM_SOFT_RESET, 107 QM_DOWN, 108 }; 109 110 enum qm_state { 111 QM_INIT = 0, 112 QM_START, 113 QM_CLOSE, 114 QM_STOP, 115 }; 116 117 enum qp_state { 118 QP_INIT = 1, 119 QP_START, 120 QP_STOP, 121 QP_CLOSE, 122 }; 123 124 enum qm_hw_ver { 125 QM_HW_V1 = 0x20, 126 QM_HW_V2 = 0x21, 127 QM_HW_V3 = 0x30, 128 }; 129 130 enum qm_fun_type { 131 QM_HW_PF, 132 QM_HW_VF, 133 }; 134 135 enum qm_debug_file { 136 CURRENT_QM, 137 CURRENT_Q, 138 CLEAR_ENABLE, 139 DEBUG_FILE_NUM, 140 }; 141 142 enum qm_vf_state { 143 QM_READY = 0, 144 QM_NOT_READY, 145 }; 146 147 enum qm_cap_bits { 148 QM_SUPPORT_DB_ISOLATION = 0x0, 149 QM_SUPPORT_FUNC_QOS, 150 QM_SUPPORT_STOP_QP, 151 QM_SUPPORT_MB_COMMAND, 152 QM_SUPPORT_SVA_PREFETCH, 153 QM_SUPPORT_RPM, 154 }; 155 156 struct dfx_diff_registers { 157 u32 *regs; 158 u32 reg_offset; 159 u32 reg_len; 160 }; 161 162 struct qm_dfx { 163 atomic64_t err_irq_cnt; 164 atomic64_t aeq_irq_cnt; 165 atomic64_t abnormal_irq_cnt; 166 atomic64_t create_qp_err_cnt; 167 atomic64_t mb_err_cnt; 168 }; 169 170 struct debugfs_file { 171 enum qm_debug_file index; 172 struct mutex lock; 173 struct qm_debug *debug; 174 }; 175 176 struct qm_debug { 177 u32 curr_qm_qp_num; 178 u32 sqe_mask_offset; 179 u32 sqe_mask_len; 180 struct qm_dfx dfx; 181 struct dentry *debug_root; 182 struct dentry *qm_d; 183 struct debugfs_file files[DEBUG_FILE_NUM]; 184 unsigned int *qm_last_words; 185 /* ACC engines recoreding last regs */ 186 unsigned int *last_words; 187 struct dfx_diff_registers *qm_diff_regs; 188 struct dfx_diff_registers *acc_diff_regs; 189 }; 190 191 struct qm_shaper_factor { 192 u32 func_qos; 193 u64 cir_b; 194 u64 cir_u; 195 u64 cir_s; 196 u64 cbs_s; 197 }; 198 199 struct qm_dma { 200 void *va; 201 dma_addr_t dma; 202 size_t size; 203 }; 204 205 struct hisi_qm_status { 206 u32 eq_head; 207 bool eqc_phase; 208 u32 aeq_head; 209 bool aeqc_phase; 210 atomic_t flags; 211 int stop_reason; 212 }; 213 214 struct hisi_qm; 215 216 struct hisi_qm_err_info { 217 char *acpi_rst; 218 u32 msi_wr_port; 219 u32 ecc_2bits_mask; 220 u32 qm_shutdown_mask; 221 u32 dev_shutdown_mask; 222 u32 qm_reset_mask; 223 u32 dev_reset_mask; 224 u32 ce; 225 u32 nfe; 226 u32 fe; 227 }; 228 229 struct hisi_qm_err_status { 230 u32 is_qm_ecc_mbit; 231 u32 is_dev_ecc_mbit; 232 }; 233 234 struct hisi_qm_err_ini { 235 int (*hw_init)(struct hisi_qm *qm); 236 void (*hw_err_enable)(struct hisi_qm *qm); 237 void (*hw_err_disable)(struct hisi_qm *qm); 238 u32 (*get_dev_hw_err_status)(struct hisi_qm *qm); 239 void (*clear_dev_hw_err_status)(struct hisi_qm *qm, u32 err_sts); 240 void (*open_axi_master_ooo)(struct hisi_qm *qm); 241 void (*close_axi_master_ooo)(struct hisi_qm *qm); 242 void (*open_sva_prefetch)(struct hisi_qm *qm); 243 void (*close_sva_prefetch)(struct hisi_qm *qm); 244 void (*log_dev_hw_err)(struct hisi_qm *qm, u32 err_sts); 245 void (*show_last_dfx_regs)(struct hisi_qm *qm); 246 void (*err_info_init)(struct hisi_qm *qm); 247 }; 248 249 struct hisi_qm_cap_info { 250 u32 type; 251 /* Register offset */ 252 u32 offset; 253 /* Bit offset in register */ 254 u32 shift; 255 u32 mask; 256 u32 v1_val; 257 u32 v2_val; 258 u32 v3_val; 259 }; 260 261 struct hisi_qm_list { 262 struct mutex lock; 263 struct list_head list; 264 int (*register_to_crypto)(struct hisi_qm *qm); 265 void (*unregister_from_crypto)(struct hisi_qm *qm); 266 }; 267 268 struct hisi_qm_poll_data { 269 struct hisi_qm *qm; 270 struct work_struct work; 271 u16 *qp_finish_id; 272 }; 273 274 /** 275 * struct qm_err_isolate 276 * @isolate_lock: protects device error log 277 * @err_threshold: user config error threshold which triggers isolation 278 * @is_isolate: device isolation state 279 * @uacce_hw_errs: index into qm device error list 280 */ 281 struct qm_err_isolate { 282 struct mutex isolate_lock; 283 u32 err_threshold; 284 bool is_isolate; 285 struct list_head qm_hw_errs; 286 }; 287 288 struct hisi_qm { 289 enum qm_hw_ver ver; 290 enum qm_fun_type fun_type; 291 const char *dev_name; 292 struct pci_dev *pdev; 293 void __iomem *io_base; 294 void __iomem *db_io_base; 295 296 /* Capbility version, 0: not supports */ 297 u32 cap_ver; 298 u32 sqe_size; 299 u32 qp_base; 300 u32 qp_num; 301 u32 qp_in_used; 302 u32 ctrl_qp_num; 303 u32 max_qp_num; 304 u32 vfs_num; 305 u32 db_interval; 306 u16 eq_depth; 307 u16 aeq_depth; 308 struct list_head list; 309 struct hisi_qm_list *qm_list; 310 311 struct qm_dma qdma; 312 struct qm_sqc *sqc; 313 struct qm_cqc *cqc; 314 struct qm_eqe *eqe; 315 struct qm_aeqe *aeqe; 316 dma_addr_t sqc_dma; 317 dma_addr_t cqc_dma; 318 dma_addr_t eqe_dma; 319 dma_addr_t aeqe_dma; 320 321 struct hisi_qm_status status; 322 const struct hisi_qm_err_ini *err_ini; 323 struct hisi_qm_err_info err_info; 324 struct hisi_qm_err_status err_status; 325 /* driver removing and reset sched */ 326 unsigned long misc_ctl; 327 /* Device capability bit */ 328 unsigned long caps; 329 330 struct rw_semaphore qps_lock; 331 struct idr qp_idr; 332 struct hisi_qp *qp_array; 333 struct hisi_qm_poll_data *poll_data; 334 335 struct mutex mailbox_lock; 336 337 const struct hisi_qm_hw_ops *ops; 338 339 struct qm_debug debug; 340 341 u32 error_mask; 342 343 struct workqueue_struct *wq; 344 struct work_struct rst_work; 345 struct work_struct cmd_process; 346 347 const char *algs; 348 bool use_sva; 349 350 resource_size_t phys_base; 351 resource_size_t db_phys_base; 352 struct uacce_device *uacce; 353 int mode; 354 struct qm_shaper_factor *factor; 355 u32 mb_qos; 356 u32 type_rate; 357 struct qm_err_isolate isolate_data; 358 }; 359 360 struct hisi_qp_status { 361 atomic_t used; 362 u16 sq_tail; 363 u16 cq_head; 364 bool cqc_phase; 365 atomic_t flags; 366 }; 367 368 struct hisi_qp_ops { 369 int (*fill_sqe)(void *sqe, void *q_parm, void *d_parm); 370 }; 371 372 struct hisi_qp { 373 u32 qp_id; 374 u16 sq_depth; 375 u16 cq_depth; 376 u8 alg_type; 377 u8 req_type; 378 379 struct qm_dma qdma; 380 void *sqe; 381 struct qm_cqe *cqe; 382 dma_addr_t sqe_dma; 383 dma_addr_t cqe_dma; 384 385 struct hisi_qp_status qp_status; 386 struct hisi_qp_ops *hw_ops; 387 void *qp_ctx; 388 void (*req_cb)(struct hisi_qp *qp, void *data); 389 void (*event_cb)(struct hisi_qp *qp); 390 391 struct hisi_qm *qm; 392 bool is_resetting; 393 bool is_in_kernel; 394 u16 pasid; 395 struct uacce_queue *uacce_q; 396 }; 397 398 static inline int q_num_set(const char *val, const struct kernel_param *kp, 399 unsigned int device) 400 { 401 struct pci_dev *pdev; 402 u32 n, q_num; 403 int ret; 404 405 if (!val) 406 return -EINVAL; 407 408 pdev = pci_get_device(PCI_VENDOR_ID_HUAWEI, device, NULL); 409 if (!pdev) { 410 q_num = min_t(u32, QM_QNUM_V1, QM_QNUM_V2); 411 pr_info("No device found currently, suppose queue number is %u\n", 412 q_num); 413 } else { 414 if (pdev->revision == QM_HW_V1) 415 q_num = QM_QNUM_V1; 416 else 417 q_num = QM_QNUM_V2; 418 419 pci_dev_put(pdev); 420 } 421 422 ret = kstrtou32(val, 10, &n); 423 if (ret || n < QM_MIN_QNUM || n > q_num) 424 return -EINVAL; 425 426 return param_set_int(val, kp); 427 } 428 429 static inline int vfs_num_set(const char *val, const struct kernel_param *kp) 430 { 431 u32 n; 432 int ret; 433 434 if (!val) 435 return -EINVAL; 436 437 ret = kstrtou32(val, 10, &n); 438 if (ret < 0) 439 return ret; 440 441 if (n > QM_MAX_VFS_NUM_V2) 442 return -EINVAL; 443 444 return param_set_int(val, kp); 445 } 446 447 static inline int mode_set(const char *val, const struct kernel_param *kp) 448 { 449 u32 n; 450 int ret; 451 452 if (!val) 453 return -EINVAL; 454 455 ret = kstrtou32(val, 10, &n); 456 if (ret != 0 || (n != UACCE_MODE_SVA && 457 n != UACCE_MODE_NOUACCE)) 458 return -EINVAL; 459 460 return param_set_int(val, kp); 461 } 462 463 static inline int uacce_mode_set(const char *val, const struct kernel_param *kp) 464 { 465 return mode_set(val, kp); 466 } 467 468 static inline void hisi_qm_init_list(struct hisi_qm_list *qm_list) 469 { 470 INIT_LIST_HEAD(&qm_list->list); 471 mutex_init(&qm_list->lock); 472 } 473 474 int hisi_qm_init(struct hisi_qm *qm); 475 void hisi_qm_uninit(struct hisi_qm *qm); 476 int hisi_qm_start(struct hisi_qm *qm); 477 int hisi_qm_stop(struct hisi_qm *qm, enum qm_stop_reason r); 478 int hisi_qm_start_qp(struct hisi_qp *qp, unsigned long arg); 479 int hisi_qm_stop_qp(struct hisi_qp *qp); 480 int hisi_qp_send(struct hisi_qp *qp, const void *msg); 481 void hisi_qm_debug_init(struct hisi_qm *qm); 482 void hisi_qm_debug_regs_clear(struct hisi_qm *qm); 483 int hisi_qm_sriov_enable(struct pci_dev *pdev, int max_vfs); 484 int hisi_qm_sriov_disable(struct pci_dev *pdev, bool is_frozen); 485 int hisi_qm_sriov_configure(struct pci_dev *pdev, int num_vfs); 486 void hisi_qm_dev_err_init(struct hisi_qm *qm); 487 void hisi_qm_dev_err_uninit(struct hisi_qm *qm); 488 int hisi_qm_regs_debugfs_init(struct hisi_qm *qm, 489 struct dfx_diff_registers *dregs, u32 reg_len); 490 void hisi_qm_regs_debugfs_uninit(struct hisi_qm *qm, u32 reg_len); 491 void hisi_qm_acc_diff_regs_dump(struct hisi_qm *qm, struct seq_file *s, 492 struct dfx_diff_registers *dregs, u32 regs_len); 493 494 pci_ers_result_t hisi_qm_dev_err_detected(struct pci_dev *pdev, 495 pci_channel_state_t state); 496 pci_ers_result_t hisi_qm_dev_slot_reset(struct pci_dev *pdev); 497 void hisi_qm_reset_prepare(struct pci_dev *pdev); 498 void hisi_qm_reset_done(struct pci_dev *pdev); 499 500 int hisi_qm_wait_mb_ready(struct hisi_qm *qm); 501 int hisi_qm_mb(struct hisi_qm *qm, u8 cmd, dma_addr_t dma_addr, u16 queue, 502 bool op); 503 504 struct hisi_acc_sgl_pool; 505 struct hisi_acc_hw_sgl *hisi_acc_sg_buf_map_to_hw_sgl(struct device *dev, 506 struct scatterlist *sgl, struct hisi_acc_sgl_pool *pool, 507 u32 index, dma_addr_t *hw_sgl_dma); 508 void hisi_acc_sg_buf_unmap(struct device *dev, struct scatterlist *sgl, 509 struct hisi_acc_hw_sgl *hw_sgl); 510 struct hisi_acc_sgl_pool *hisi_acc_create_sgl_pool(struct device *dev, 511 u32 count, u32 sge_nr); 512 void hisi_acc_free_sgl_pool(struct device *dev, 513 struct hisi_acc_sgl_pool *pool); 514 int hisi_qm_alloc_qps_node(struct hisi_qm_list *qm_list, int qp_num, 515 u8 alg_type, int node, struct hisi_qp **qps); 516 void hisi_qm_free_qps(struct hisi_qp **qps, int qp_num); 517 void hisi_qm_dev_shutdown(struct pci_dev *pdev); 518 void hisi_qm_wait_task_finish(struct hisi_qm *qm, struct hisi_qm_list *qm_list); 519 int hisi_qm_alg_register(struct hisi_qm *qm, struct hisi_qm_list *qm_list); 520 void hisi_qm_alg_unregister(struct hisi_qm *qm, struct hisi_qm_list *qm_list); 521 int hisi_qm_resume(struct device *dev); 522 int hisi_qm_suspend(struct device *dev); 523 void hisi_qm_pm_uninit(struct hisi_qm *qm); 524 void hisi_qm_pm_init(struct hisi_qm *qm); 525 int hisi_qm_get_dfx_access(struct hisi_qm *qm); 526 void hisi_qm_put_dfx_access(struct hisi_qm *qm); 527 void hisi_qm_regs_dump(struct seq_file *s, struct debugfs_regset32 *regset); 528 u32 hisi_qm_get_hw_info(struct hisi_qm *qm, 529 const struct hisi_qm_cap_info *info_table, 530 u32 index, bool is_read); 531 532 /* Used by VFIO ACC live migration driver */ 533 struct pci_driver *hisi_sec_get_pf_driver(void); 534 struct pci_driver *hisi_hpre_get_pf_driver(void); 535 struct pci_driver *hisi_zip_get_pf_driver(void); 536 #endif 537