1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) ST Ericsson SA 2011 4 * 5 * STE Ux500 PRCMU API 6 */ 7 #ifndef __MACH_PRCMU_H 8 #define __MACH_PRCMU_H 9 10 #include <linux/interrupt.h> 11 #include <linux/notifier.h> 12 #include <linux/err.h> 13 14 #include <dt-bindings/mfd/dbx500-prcmu.h> /* For clock identifiers */ 15 16 /* Offset for the firmware version within the TCPM */ 17 #define DB8500_PRCMU_FW_VERSION_OFFSET 0xA4 18 #define DBX540_PRCMU_FW_VERSION_OFFSET 0xA8 19 20 /* PRCMU Wakeup defines */ 21 enum prcmu_wakeup_index { 22 PRCMU_WAKEUP_INDEX_RTC, 23 PRCMU_WAKEUP_INDEX_RTT0, 24 PRCMU_WAKEUP_INDEX_RTT1, 25 PRCMU_WAKEUP_INDEX_HSI0, 26 PRCMU_WAKEUP_INDEX_HSI1, 27 PRCMU_WAKEUP_INDEX_USB, 28 PRCMU_WAKEUP_INDEX_ABB, 29 PRCMU_WAKEUP_INDEX_ABB_FIFO, 30 PRCMU_WAKEUP_INDEX_ARM, 31 PRCMU_WAKEUP_INDEX_CD_IRQ, 32 NUM_PRCMU_WAKEUP_INDICES 33 }; 34 #define PRCMU_WAKEUP(_name) (BIT(PRCMU_WAKEUP_INDEX_##_name)) 35 36 /* EPOD (power domain) IDs */ 37 38 /* 39 * DB8500 EPODs 40 * - EPOD_ID_SVAMMDSP: power domain for SVA MMDSP 41 * - EPOD_ID_SVAPIPE: power domain for SVA pipe 42 * - EPOD_ID_SIAMMDSP: power domain for SIA MMDSP 43 * - EPOD_ID_SIAPIPE: power domain for SIA pipe 44 * - EPOD_ID_SGA: power domain for SGA 45 * - EPOD_ID_B2R2_MCDE: power domain for B2R2 and MCDE 46 * - EPOD_ID_ESRAM12: power domain for ESRAM 1 and 2 47 * - EPOD_ID_ESRAM34: power domain for ESRAM 3 and 4 48 * - NUM_EPOD_ID: number of power domains 49 * 50 * TODO: These should be prefixed. 51 */ 52 #define EPOD_ID_SVAMMDSP 0 53 #define EPOD_ID_SVAPIPE 1 54 #define EPOD_ID_SIAMMDSP 2 55 #define EPOD_ID_SIAPIPE 3 56 #define EPOD_ID_SGA 4 57 #define EPOD_ID_B2R2_MCDE 5 58 #define EPOD_ID_ESRAM12 6 59 #define EPOD_ID_ESRAM34 7 60 #define NUM_EPOD_ID 8 61 62 /* 63 * state definition for EPOD (power domain) 64 * - EPOD_STATE_NO_CHANGE: The EPOD should remain unchanged 65 * - EPOD_STATE_OFF: The EPOD is switched off 66 * - EPOD_STATE_RAMRET: The EPOD is switched off with its internal RAM in 67 * retention 68 * - EPOD_STATE_ON_CLK_OFF: The EPOD is switched on, clock is still off 69 * - EPOD_STATE_ON: Same as above, but with clock enabled 70 */ 71 #define EPOD_STATE_NO_CHANGE 0x00 72 #define EPOD_STATE_OFF 0x01 73 #define EPOD_STATE_RAMRET 0x02 74 #define EPOD_STATE_ON_CLK_OFF 0x03 75 #define EPOD_STATE_ON 0x04 76 77 /* 78 * CLKOUT sources 79 */ 80 #define PRCMU_CLKSRC_CLK38M 0x00 81 #define PRCMU_CLKSRC_ACLK 0x01 82 #define PRCMU_CLKSRC_SYSCLK 0x02 83 #define PRCMU_CLKSRC_LCDCLK 0x03 84 #define PRCMU_CLKSRC_SDMMCCLK 0x04 85 #define PRCMU_CLKSRC_TVCLK 0x05 86 #define PRCMU_CLKSRC_TIMCLK 0x06 87 #define PRCMU_CLKSRC_CLK009 0x07 88 /* These are only valid for CLKOUT1: */ 89 #define PRCMU_CLKSRC_SIAMMDSPCLK 0x40 90 #define PRCMU_CLKSRC_I2CCLK 0x41 91 #define PRCMU_CLKSRC_MSP02CLK 0x42 92 #define PRCMU_CLKSRC_ARMPLL_OBSCLK 0x43 93 #define PRCMU_CLKSRC_HSIRXCLK 0x44 94 #define PRCMU_CLKSRC_HSITXCLK 0x45 95 #define PRCMU_CLKSRC_ARMCLKFIX 0x46 96 #define PRCMU_CLKSRC_HDMICLK 0x47 97 98 /** 99 * enum prcmu_wdog_id - PRCMU watchdog IDs 100 * @PRCMU_WDOG_ALL: use all timers 101 * @PRCMU_WDOG_CPU1: use first CPU timer only 102 * @PRCMU_WDOG_CPU2: use second CPU timer conly 103 */ 104 enum prcmu_wdog_id { 105 PRCMU_WDOG_ALL = 0x00, 106 PRCMU_WDOG_CPU1 = 0x01, 107 PRCMU_WDOG_CPU2 = 0x02, 108 }; 109 110 /** 111 * enum ape_opp - APE OPP states definition 112 * @APE_OPP_INIT: 113 * @APE_NO_CHANGE: The APE operating point is unchanged 114 * @APE_100_OPP: The new APE operating point is ape100opp 115 * @APE_50_OPP: 50% 116 * @APE_50_PARTLY_25_OPP: 50%, except some clocks at 25%. 117 */ 118 enum ape_opp { 119 APE_OPP_INIT = 0x00, 120 APE_NO_CHANGE = 0x01, 121 APE_100_OPP = 0x02, 122 APE_50_OPP = 0x03, 123 APE_50_PARTLY_25_OPP = 0xFF, 124 }; 125 126 /** 127 * enum arm_opp - ARM OPP states definition 128 * @ARM_OPP_INIT: 129 * @ARM_NO_CHANGE: The ARM operating point is unchanged 130 * @ARM_100_OPP: The new ARM operating point is arm100opp 131 * @ARM_50_OPP: The new ARM operating point is arm50opp 132 * @ARM_MAX_OPP: Operating point is "max" (more than 100) 133 * @ARM_MAX_FREQ100OPP: Set max opp if available, else 100 134 * @ARM_EXTCLK: The new ARM operating point is armExtClk 135 */ 136 enum arm_opp { 137 ARM_OPP_INIT = 0x00, 138 ARM_NO_CHANGE = 0x01, 139 ARM_100_OPP = 0x02, 140 ARM_50_OPP = 0x03, 141 ARM_MAX_OPP = 0x04, 142 ARM_MAX_FREQ100OPP = 0x05, 143 ARM_EXTCLK = 0x07 144 }; 145 146 /** 147 * enum ddr_opp - DDR OPP states definition 148 * @DDR_100_OPP: The new DDR operating point is ddr100opp 149 * @DDR_50_OPP: The new DDR operating point is ddr50opp 150 * @DDR_25_OPP: The new DDR operating point is ddr25opp 151 */ 152 enum ddr_opp { 153 DDR_100_OPP = 0x00, 154 DDR_50_OPP = 0x01, 155 DDR_25_OPP = 0x02, 156 }; 157 158 /* 159 * Definitions for controlling ESRAM0 in deep sleep. 160 */ 161 #define ESRAM0_DEEP_SLEEP_STATE_OFF 1 162 #define ESRAM0_DEEP_SLEEP_STATE_RET 2 163 164 /** 165 * enum ddr_pwrst - DDR power states definition 166 * @DDR_PWR_STATE_UNCHANGED: SDRAM and DDR controller state is unchanged 167 * @DDR_PWR_STATE_ON: 168 * @DDR_PWR_STATE_OFFLOWLAT: 169 * @DDR_PWR_STATE_OFFHIGHLAT: 170 */ 171 enum ddr_pwrst { 172 DDR_PWR_STATE_UNCHANGED = 0x00, 173 DDR_PWR_STATE_ON = 0x01, 174 DDR_PWR_STATE_OFFLOWLAT = 0x02, 175 DDR_PWR_STATE_OFFHIGHLAT = 0x03 176 }; 177 178 #define DB8500_PRCMU_LEGACY_OFFSET 0xDD4 179 180 #define PRCMU_FW_PROJECT_U8500 2 181 #define PRCMU_FW_PROJECT_U8400 3 182 #define PRCMU_FW_PROJECT_U9500 4 /* Customer specific */ 183 #define PRCMU_FW_PROJECT_U8500_MBB 5 184 #define PRCMU_FW_PROJECT_U8500_C1 6 185 #define PRCMU_FW_PROJECT_U8500_C2 7 186 #define PRCMU_FW_PROJECT_U8500_C3 8 187 #define PRCMU_FW_PROJECT_U8500_C4 9 188 #define PRCMU_FW_PROJECT_U9500_MBL 10 189 #define PRCMU_FW_PROJECT_U8500_MBL 11 /* Customer specific */ 190 #define PRCMU_FW_PROJECT_U8500_MBL2 12 /* Customer specific */ 191 #define PRCMU_FW_PROJECT_U8520 13 192 #define PRCMU_FW_PROJECT_U8420 14 193 #define PRCMU_FW_PROJECT_A9420 20 194 /* [32..63] 9540 and derivatives */ 195 #define PRCMU_FW_PROJECT_U9540 32 196 /* [64..95] 8540 and derivatives */ 197 #define PRCMU_FW_PROJECT_L8540 64 198 /* [96..126] 8580 and derivatives */ 199 #define PRCMU_FW_PROJECT_L8580 96 200 201 #define PRCMU_FW_PROJECT_NAME_LEN 20 202 struct prcmu_fw_version { 203 u32 project; /* Notice, project shifted with 8 on ux540 */ 204 u8 api_version; 205 u8 func_version; 206 u8 errata; 207 char project_name[PRCMU_FW_PROJECT_NAME_LEN]; 208 }; 209 210 #include <linux/mfd/db8500-prcmu.h> 211 212 #if defined(CONFIG_UX500_SOC_DB8500) 213 214 static inline void prcmu_early_init(u32 phy_base, u32 size) 215 { 216 return db8500_prcmu_early_init(phy_base, size); 217 } 218 219 static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk, 220 bool keep_ap_pll) 221 { 222 return db8500_prcmu_set_power_state(state, keep_ulp_clk, 223 keep_ap_pll); 224 } 225 226 static inline u8 prcmu_get_power_state_result(void) 227 { 228 return db8500_prcmu_get_power_state_result(); 229 } 230 231 static inline int prcmu_set_epod(u16 epod_id, u8 epod_state) 232 { 233 return db8500_prcmu_set_epod(epod_id, epod_state); 234 } 235 236 static inline void prcmu_enable_wakeups(u32 wakeups) 237 { 238 db8500_prcmu_enable_wakeups(wakeups); 239 } 240 241 static inline void prcmu_disable_wakeups(void) 242 { 243 prcmu_enable_wakeups(0); 244 } 245 246 static inline void prcmu_config_abb_event_readout(u32 abb_events) 247 { 248 db8500_prcmu_config_abb_event_readout(abb_events); 249 } 250 251 static inline void prcmu_get_abb_event_buffer(void __iomem **buf) 252 { 253 db8500_prcmu_get_abb_event_buffer(buf); 254 } 255 256 int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size); 257 int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size); 258 int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask, u8 size); 259 260 int prcmu_config_clkout(u8 clkout, u8 source, u8 div); 261 262 static inline int prcmu_request_clock(u8 clock, bool enable) 263 { 264 return db8500_prcmu_request_clock(clock, enable); 265 } 266 267 unsigned long prcmu_clock_rate(u8 clock); 268 long prcmu_round_clock_rate(u8 clock, unsigned long rate); 269 int prcmu_set_clock_rate(u8 clock, unsigned long rate); 270 271 static inline int prcmu_get_ddr_opp(void) 272 { 273 return db8500_prcmu_get_ddr_opp(); 274 } 275 276 static inline int prcmu_set_arm_opp(u8 opp) 277 { 278 return db8500_prcmu_set_arm_opp(opp); 279 } 280 281 static inline int prcmu_get_arm_opp(void) 282 { 283 return db8500_prcmu_get_arm_opp(); 284 } 285 286 static inline int prcmu_set_ape_opp(u8 opp) 287 { 288 return db8500_prcmu_set_ape_opp(opp); 289 } 290 291 static inline int prcmu_get_ape_opp(void) 292 { 293 return db8500_prcmu_get_ape_opp(); 294 } 295 296 static inline int prcmu_request_ape_opp_100_voltage(bool enable) 297 { 298 return db8500_prcmu_request_ape_opp_100_voltage(enable); 299 } 300 301 static inline void prcmu_system_reset(u16 reset_code) 302 { 303 return db8500_prcmu_system_reset(reset_code); 304 } 305 306 static inline u16 prcmu_get_reset_code(void) 307 { 308 return db8500_prcmu_get_reset_code(); 309 } 310 311 int prcmu_ac_wake_req(void); 312 void prcmu_ac_sleep_req(void); 313 static inline void prcmu_modem_reset(void) 314 { 315 return db8500_prcmu_modem_reset(); 316 } 317 318 static inline bool prcmu_is_ac_wake_requested(void) 319 { 320 return db8500_prcmu_is_ac_wake_requested(); 321 } 322 323 static inline int prcmu_set_display_clocks(void) 324 { 325 return db8500_prcmu_set_display_clocks(); 326 } 327 328 static inline int prcmu_disable_dsipll(void) 329 { 330 return db8500_prcmu_disable_dsipll(); 331 } 332 333 static inline int prcmu_enable_dsipll(void) 334 { 335 return db8500_prcmu_enable_dsipll(); 336 } 337 338 static inline int prcmu_config_esram0_deep_sleep(u8 state) 339 { 340 return db8500_prcmu_config_esram0_deep_sleep(state); 341 } 342 343 static inline int prcmu_config_hotdog(u8 threshold) 344 { 345 return db8500_prcmu_config_hotdog(threshold); 346 } 347 348 static inline int prcmu_config_hotmon(u8 low, u8 high) 349 { 350 return db8500_prcmu_config_hotmon(low, high); 351 } 352 353 static inline int prcmu_start_temp_sense(u16 cycles32k) 354 { 355 return db8500_prcmu_start_temp_sense(cycles32k); 356 } 357 358 static inline int prcmu_stop_temp_sense(void) 359 { 360 return db8500_prcmu_stop_temp_sense(); 361 } 362 363 static inline u32 prcmu_read(unsigned int reg) 364 { 365 return db8500_prcmu_read(reg); 366 } 367 368 static inline void prcmu_write(unsigned int reg, u32 value) 369 { 370 db8500_prcmu_write(reg, value); 371 } 372 373 static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value) 374 { 375 db8500_prcmu_write_masked(reg, mask, value); 376 } 377 378 static inline int prcmu_enable_a9wdog(u8 id) 379 { 380 return db8500_prcmu_enable_a9wdog(id); 381 } 382 383 static inline int prcmu_disable_a9wdog(u8 id) 384 { 385 return db8500_prcmu_disable_a9wdog(id); 386 } 387 388 static inline int prcmu_kick_a9wdog(u8 id) 389 { 390 return db8500_prcmu_kick_a9wdog(id); 391 } 392 393 static inline int prcmu_load_a9wdog(u8 id, u32 timeout) 394 { 395 return db8500_prcmu_load_a9wdog(id, timeout); 396 } 397 398 static inline int prcmu_config_a9wdog(u8 num, bool sleep_auto_off) 399 { 400 return db8500_prcmu_config_a9wdog(num, sleep_auto_off); 401 } 402 #else 403 404 static inline void prcmu_early_init(u32 phy_base, u32 size) {} 405 406 static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk, 407 bool keep_ap_pll) 408 { 409 return 0; 410 } 411 412 static inline int prcmu_set_epod(u16 epod_id, u8 epod_state) 413 { 414 return 0; 415 } 416 417 static inline void prcmu_enable_wakeups(u32 wakeups) {} 418 419 static inline void prcmu_disable_wakeups(void) {} 420 421 static inline int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size) 422 { 423 return -ENOSYS; 424 } 425 426 static inline int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size) 427 { 428 return -ENOSYS; 429 } 430 431 static inline int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask, 432 u8 size) 433 { 434 return -ENOSYS; 435 } 436 437 static inline int prcmu_config_clkout(u8 clkout, u8 source, u8 div) 438 { 439 return 0; 440 } 441 442 static inline int prcmu_request_clock(u8 clock, bool enable) 443 { 444 return 0; 445 } 446 447 static inline long prcmu_round_clock_rate(u8 clock, unsigned long rate) 448 { 449 return 0; 450 } 451 452 static inline int prcmu_set_clock_rate(u8 clock, unsigned long rate) 453 { 454 return 0; 455 } 456 457 static inline unsigned long prcmu_clock_rate(u8 clock) 458 { 459 return 0; 460 } 461 462 static inline int prcmu_set_ape_opp(u8 opp) 463 { 464 return 0; 465 } 466 467 static inline int prcmu_get_ape_opp(void) 468 { 469 return APE_100_OPP; 470 } 471 472 static inline int prcmu_request_ape_opp_100_voltage(bool enable) 473 { 474 return 0; 475 } 476 477 static inline int prcmu_set_arm_opp(u8 opp) 478 { 479 return 0; 480 } 481 482 static inline int prcmu_get_arm_opp(void) 483 { 484 return ARM_100_OPP; 485 } 486 487 static inline int prcmu_get_ddr_opp(void) 488 { 489 return DDR_100_OPP; 490 } 491 492 static inline void prcmu_system_reset(u16 reset_code) {} 493 494 static inline u16 prcmu_get_reset_code(void) 495 { 496 return 0; 497 } 498 499 static inline int prcmu_ac_wake_req(void) 500 { 501 return 0; 502 } 503 504 static inline void prcmu_ac_sleep_req(void) {} 505 506 static inline void prcmu_modem_reset(void) {} 507 508 static inline bool prcmu_is_ac_wake_requested(void) 509 { 510 return false; 511 } 512 513 static inline int prcmu_set_display_clocks(void) 514 { 515 return 0; 516 } 517 518 static inline int prcmu_disable_dsipll(void) 519 { 520 return 0; 521 } 522 523 static inline int prcmu_enable_dsipll(void) 524 { 525 return 0; 526 } 527 528 static inline int prcmu_config_esram0_deep_sleep(u8 state) 529 { 530 return 0; 531 } 532 533 static inline void prcmu_config_abb_event_readout(u32 abb_events) {} 534 535 static inline void prcmu_get_abb_event_buffer(void __iomem **buf) 536 { 537 *buf = NULL; 538 } 539 540 static inline int prcmu_config_hotdog(u8 threshold) 541 { 542 return 0; 543 } 544 545 static inline int prcmu_config_hotmon(u8 low, u8 high) 546 { 547 return 0; 548 } 549 550 static inline int prcmu_start_temp_sense(u16 cycles32k) 551 { 552 return 0; 553 } 554 555 static inline int prcmu_stop_temp_sense(void) 556 { 557 return 0; 558 } 559 560 static inline u32 prcmu_read(unsigned int reg) 561 { 562 return 0; 563 } 564 565 static inline void prcmu_write(unsigned int reg, u32 value) {} 566 567 static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value) {} 568 569 #endif 570 571 static inline void prcmu_set(unsigned int reg, u32 bits) 572 { 573 prcmu_write_masked(reg, bits, bits); 574 } 575 576 static inline void prcmu_clear(unsigned int reg, u32 bits) 577 { 578 prcmu_write_masked(reg, bits, 0); 579 } 580 581 /* PRCMU QoS APE OPP class */ 582 #define PRCMU_QOS_APE_OPP 1 583 #define PRCMU_QOS_DDR_OPP 2 584 #define PRCMU_QOS_ARM_OPP 3 585 #define PRCMU_QOS_DEFAULT_VALUE -1 586 587 #ifdef CONFIG_DBX500_PRCMU_QOS_POWER 588 589 unsigned long prcmu_qos_get_cpufreq_opp_delay(void); 590 void prcmu_qos_set_cpufreq_opp_delay(unsigned long); 591 void prcmu_qos_force_opp(int, s32); 592 int prcmu_qos_requirement(int pm_qos_class); 593 int prcmu_qos_add_requirement(int pm_qos_class, char *name, s32 value); 594 int prcmu_qos_update_requirement(int pm_qos_class, char *name, s32 new_value); 595 void prcmu_qos_remove_requirement(int pm_qos_class, char *name); 596 int prcmu_qos_add_notifier(int prcmu_qos_class, 597 struct notifier_block *notifier); 598 int prcmu_qos_remove_notifier(int prcmu_qos_class, 599 struct notifier_block *notifier); 600 601 #else 602 603 static inline unsigned long prcmu_qos_get_cpufreq_opp_delay(void) 604 { 605 return 0; 606 } 607 608 static inline void prcmu_qos_set_cpufreq_opp_delay(unsigned long n) {} 609 610 static inline void prcmu_qos_force_opp(int prcmu_qos_class, s32 i) {} 611 612 static inline int prcmu_qos_requirement(int prcmu_qos_class) 613 { 614 return 0; 615 } 616 617 static inline int prcmu_qos_add_requirement(int prcmu_qos_class, 618 char *name, s32 value) 619 { 620 return 0; 621 } 622 623 static inline int prcmu_qos_update_requirement(int prcmu_qos_class, 624 char *name, s32 new_value) 625 { 626 return 0; 627 } 628 629 static inline void prcmu_qos_remove_requirement(int prcmu_qos_class, char *name) 630 { 631 } 632 633 static inline int prcmu_qos_add_notifier(int prcmu_qos_class, 634 struct notifier_block *notifier) 635 { 636 return 0; 637 } 638 static inline int prcmu_qos_remove_notifier(int prcmu_qos_class, 639 struct notifier_block *notifier) 640 { 641 return 0; 642 } 643 644 #endif 645 646 #endif /* __MACH_PRCMU_H */ 647