1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) ST Ericsson SA 2011 4 * 5 * STE Ux500 PRCMU API 6 */ 7 #ifndef __MACH_PRCMU_H 8 #define __MACH_PRCMU_H 9 10 #include <linux/interrupt.h> 11 #include <linux/notifier.h> 12 #include <linux/err.h> 13 14 #include <dt-bindings/mfd/dbx500-prcmu.h> /* For clock identifiers */ 15 16 /* Offset for the firmware version within the TCPM */ 17 #define DB8500_PRCMU_FW_VERSION_OFFSET 0xA4 18 #define DBX540_PRCMU_FW_VERSION_OFFSET 0xA8 19 20 /* PRCMU Wakeup defines */ 21 enum prcmu_wakeup_index { 22 PRCMU_WAKEUP_INDEX_RTC, 23 PRCMU_WAKEUP_INDEX_RTT0, 24 PRCMU_WAKEUP_INDEX_RTT1, 25 PRCMU_WAKEUP_INDEX_HSI0, 26 PRCMU_WAKEUP_INDEX_HSI1, 27 PRCMU_WAKEUP_INDEX_USB, 28 PRCMU_WAKEUP_INDEX_ABB, 29 PRCMU_WAKEUP_INDEX_ABB_FIFO, 30 PRCMU_WAKEUP_INDEX_ARM, 31 PRCMU_WAKEUP_INDEX_CD_IRQ, 32 NUM_PRCMU_WAKEUP_INDICES 33 }; 34 #define PRCMU_WAKEUP(_name) (BIT(PRCMU_WAKEUP_INDEX_##_name)) 35 36 /* EPOD (power domain) IDs */ 37 38 /* 39 * DB8500 EPODs 40 * - EPOD_ID_SVAMMDSP: power domain for SVA MMDSP 41 * - EPOD_ID_SVAPIPE: power domain for SVA pipe 42 * - EPOD_ID_SIAMMDSP: power domain for SIA MMDSP 43 * - EPOD_ID_SIAPIPE: power domain for SIA pipe 44 * - EPOD_ID_SGA: power domain for SGA 45 * - EPOD_ID_B2R2_MCDE: power domain for B2R2 and MCDE 46 * - EPOD_ID_ESRAM12: power domain for ESRAM 1 and 2 47 * - EPOD_ID_ESRAM34: power domain for ESRAM 3 and 4 48 * - NUM_EPOD_ID: number of power domains 49 * 50 * TODO: These should be prefixed. 51 */ 52 #define EPOD_ID_SVAMMDSP 0 53 #define EPOD_ID_SVAPIPE 1 54 #define EPOD_ID_SIAMMDSP 2 55 #define EPOD_ID_SIAPIPE 3 56 #define EPOD_ID_SGA 4 57 #define EPOD_ID_B2R2_MCDE 5 58 #define EPOD_ID_ESRAM12 6 59 #define EPOD_ID_ESRAM34 7 60 #define NUM_EPOD_ID 8 61 62 /* 63 * state definition for EPOD (power domain) 64 * - EPOD_STATE_NO_CHANGE: The EPOD should remain unchanged 65 * - EPOD_STATE_OFF: The EPOD is switched off 66 * - EPOD_STATE_RAMRET: The EPOD is switched off with its internal RAM in 67 * retention 68 * - EPOD_STATE_ON_CLK_OFF: The EPOD is switched on, clock is still off 69 * - EPOD_STATE_ON: Same as above, but with clock enabled 70 */ 71 #define EPOD_STATE_NO_CHANGE 0x00 72 #define EPOD_STATE_OFF 0x01 73 #define EPOD_STATE_RAMRET 0x02 74 #define EPOD_STATE_ON_CLK_OFF 0x03 75 #define EPOD_STATE_ON 0x04 76 77 /* 78 * CLKOUT sources 79 */ 80 #define PRCMU_CLKSRC_CLK38M 0x00 81 #define PRCMU_CLKSRC_ACLK 0x01 82 #define PRCMU_CLKSRC_SYSCLK 0x02 83 #define PRCMU_CLKSRC_LCDCLK 0x03 84 #define PRCMU_CLKSRC_SDMMCCLK 0x04 85 #define PRCMU_CLKSRC_TVCLK 0x05 86 #define PRCMU_CLKSRC_TIMCLK 0x06 87 #define PRCMU_CLKSRC_CLK009 0x07 88 /* These are only valid for CLKOUT1: */ 89 #define PRCMU_CLKSRC_SIAMMDSPCLK 0x40 90 #define PRCMU_CLKSRC_I2CCLK 0x41 91 #define PRCMU_CLKSRC_MSP02CLK 0x42 92 #define PRCMU_CLKSRC_ARMPLL_OBSCLK 0x43 93 #define PRCMU_CLKSRC_HSIRXCLK 0x44 94 #define PRCMU_CLKSRC_HSITXCLK 0x45 95 #define PRCMU_CLKSRC_ARMCLKFIX 0x46 96 #define PRCMU_CLKSRC_HDMICLK 0x47 97 98 /** 99 * enum prcmu_wdog_id - PRCMU watchdog IDs 100 * @PRCMU_WDOG_ALL: use all timers 101 * @PRCMU_WDOG_CPU1: use first CPU timer only 102 * @PRCMU_WDOG_CPU2: use second CPU timer conly 103 */ 104 enum prcmu_wdog_id { 105 PRCMU_WDOG_ALL = 0x00, 106 PRCMU_WDOG_CPU1 = 0x01, 107 PRCMU_WDOG_CPU2 = 0x02, 108 }; 109 110 /** 111 * enum ape_opp - APE OPP states definition 112 * @APE_OPP_INIT: 113 * @APE_NO_CHANGE: The APE operating point is unchanged 114 * @APE_100_OPP: The new APE operating point is ape100opp 115 * @APE_50_OPP: 50% 116 * @APE_50_PARTLY_25_OPP: 50%, except some clocks at 25%. 117 */ 118 enum ape_opp { 119 APE_OPP_INIT = 0x00, 120 APE_NO_CHANGE = 0x01, 121 APE_100_OPP = 0x02, 122 APE_50_OPP = 0x03, 123 APE_50_PARTLY_25_OPP = 0xFF, 124 }; 125 126 /** 127 * enum arm_opp - ARM OPP states definition 128 * @ARM_OPP_INIT: 129 * @ARM_NO_CHANGE: The ARM operating point is unchanged 130 * @ARM_100_OPP: The new ARM operating point is arm100opp 131 * @ARM_50_OPP: The new ARM operating point is arm50opp 132 * @ARM_MAX_OPP: Operating point is "max" (more than 100) 133 * @ARM_MAX_FREQ100OPP: Set max opp if available, else 100 134 * @ARM_EXTCLK: The new ARM operating point is armExtClk 135 */ 136 enum arm_opp { 137 ARM_OPP_INIT = 0x00, 138 ARM_NO_CHANGE = 0x01, 139 ARM_100_OPP = 0x02, 140 ARM_50_OPP = 0x03, 141 ARM_MAX_OPP = 0x04, 142 ARM_MAX_FREQ100OPP = 0x05, 143 ARM_EXTCLK = 0x07 144 }; 145 146 /** 147 * enum ddr_opp - DDR OPP states definition 148 * @DDR_100_OPP: The new DDR operating point is ddr100opp 149 * @DDR_50_OPP: The new DDR operating point is ddr50opp 150 * @DDR_25_OPP: The new DDR operating point is ddr25opp 151 */ 152 enum ddr_opp { 153 DDR_100_OPP = 0x00, 154 DDR_50_OPP = 0x01, 155 DDR_25_OPP = 0x02, 156 }; 157 158 /* 159 * Definitions for controlling ESRAM0 in deep sleep. 160 */ 161 #define ESRAM0_DEEP_SLEEP_STATE_OFF 1 162 #define ESRAM0_DEEP_SLEEP_STATE_RET 2 163 164 /** 165 * enum ddr_pwrst - DDR power states definition 166 * @DDR_PWR_STATE_UNCHANGED: SDRAM and DDR controller state is unchanged 167 * @DDR_PWR_STATE_ON: 168 * @DDR_PWR_STATE_OFFLOWLAT: 169 * @DDR_PWR_STATE_OFFHIGHLAT: 170 */ 171 enum ddr_pwrst { 172 DDR_PWR_STATE_UNCHANGED = 0x00, 173 DDR_PWR_STATE_ON = 0x01, 174 DDR_PWR_STATE_OFFLOWLAT = 0x02, 175 DDR_PWR_STATE_OFFHIGHLAT = 0x03 176 }; 177 178 #define DB8500_PRCMU_LEGACY_OFFSET 0xDD4 179 180 #define PRCMU_FW_PROJECT_U8500 2 181 #define PRCMU_FW_PROJECT_U8400 3 182 #define PRCMU_FW_PROJECT_U9500 4 /* Customer specific */ 183 #define PRCMU_FW_PROJECT_U8500_MBB 5 184 #define PRCMU_FW_PROJECT_U8500_C1 6 185 #define PRCMU_FW_PROJECT_U8500_C2 7 186 #define PRCMU_FW_PROJECT_U8500_C3 8 187 #define PRCMU_FW_PROJECT_U8500_C4 9 188 #define PRCMU_FW_PROJECT_U9500_MBL 10 189 #define PRCMU_FW_PROJECT_U8500_MBL 11 /* Customer specific */ 190 #define PRCMU_FW_PROJECT_U8500_MBL2 12 /* Customer specific */ 191 #define PRCMU_FW_PROJECT_U8520 13 192 #define PRCMU_FW_PROJECT_U8420 14 193 #define PRCMU_FW_PROJECT_U8420_SYSCLK 17 194 #define PRCMU_FW_PROJECT_A9420 20 195 /* [32..63] 9540 and derivatives */ 196 #define PRCMU_FW_PROJECT_U9540 32 197 /* [64..95] 8540 and derivatives */ 198 #define PRCMU_FW_PROJECT_L8540 64 199 /* [96..126] 8580 and derivatives */ 200 #define PRCMU_FW_PROJECT_L8580 96 201 202 #define PRCMU_FW_PROJECT_NAME_LEN 20 203 struct prcmu_fw_version { 204 u32 project; /* Notice, project shifted with 8 on ux540 */ 205 u8 api_version; 206 u8 func_version; 207 u8 errata; 208 char project_name[PRCMU_FW_PROJECT_NAME_LEN]; 209 }; 210 211 #include <linux/mfd/db8500-prcmu.h> 212 213 #if defined(CONFIG_UX500_SOC_DB8500) 214 215 static inline void prcmu_early_init(void) 216 { 217 return db8500_prcmu_early_init(); 218 } 219 220 static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk, 221 bool keep_ap_pll) 222 { 223 return db8500_prcmu_set_power_state(state, keep_ulp_clk, 224 keep_ap_pll); 225 } 226 227 static inline u8 prcmu_get_power_state_result(void) 228 { 229 return db8500_prcmu_get_power_state_result(); 230 } 231 232 static inline int prcmu_set_epod(u16 epod_id, u8 epod_state) 233 { 234 return db8500_prcmu_set_epod(epod_id, epod_state); 235 } 236 237 static inline void prcmu_enable_wakeups(u32 wakeups) 238 { 239 db8500_prcmu_enable_wakeups(wakeups); 240 } 241 242 static inline void prcmu_disable_wakeups(void) 243 { 244 prcmu_enable_wakeups(0); 245 } 246 247 static inline void prcmu_config_abb_event_readout(u32 abb_events) 248 { 249 db8500_prcmu_config_abb_event_readout(abb_events); 250 } 251 252 static inline void prcmu_get_abb_event_buffer(void __iomem **buf) 253 { 254 db8500_prcmu_get_abb_event_buffer(buf); 255 } 256 257 int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size); 258 int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size); 259 int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask, u8 size); 260 261 int prcmu_config_clkout(u8 clkout, u8 source, u8 div); 262 263 static inline int prcmu_request_clock(u8 clock, bool enable) 264 { 265 return db8500_prcmu_request_clock(clock, enable); 266 } 267 268 unsigned long prcmu_clock_rate(u8 clock); 269 long prcmu_round_clock_rate(u8 clock, unsigned long rate); 270 int prcmu_set_clock_rate(u8 clock, unsigned long rate); 271 272 static inline int prcmu_get_ddr_opp(void) 273 { 274 return db8500_prcmu_get_ddr_opp(); 275 } 276 277 static inline int prcmu_set_arm_opp(u8 opp) 278 { 279 return db8500_prcmu_set_arm_opp(opp); 280 } 281 282 static inline int prcmu_get_arm_opp(void) 283 { 284 return db8500_prcmu_get_arm_opp(); 285 } 286 287 static inline int prcmu_set_ape_opp(u8 opp) 288 { 289 return db8500_prcmu_set_ape_opp(opp); 290 } 291 292 static inline int prcmu_get_ape_opp(void) 293 { 294 return db8500_prcmu_get_ape_opp(); 295 } 296 297 static inline int prcmu_request_ape_opp_100_voltage(bool enable) 298 { 299 return db8500_prcmu_request_ape_opp_100_voltage(enable); 300 } 301 302 static inline void prcmu_system_reset(u16 reset_code) 303 { 304 return db8500_prcmu_system_reset(reset_code); 305 } 306 307 static inline u16 prcmu_get_reset_code(void) 308 { 309 return db8500_prcmu_get_reset_code(); 310 } 311 312 int prcmu_ac_wake_req(void); 313 void prcmu_ac_sleep_req(void); 314 static inline void prcmu_modem_reset(void) 315 { 316 return db8500_prcmu_modem_reset(); 317 } 318 319 static inline bool prcmu_is_ac_wake_requested(void) 320 { 321 return db8500_prcmu_is_ac_wake_requested(); 322 } 323 324 static inline int prcmu_set_display_clocks(void) 325 { 326 return db8500_prcmu_set_display_clocks(); 327 } 328 329 static inline int prcmu_disable_dsipll(void) 330 { 331 return db8500_prcmu_disable_dsipll(); 332 } 333 334 static inline int prcmu_enable_dsipll(void) 335 { 336 return db8500_prcmu_enable_dsipll(); 337 } 338 339 static inline int prcmu_config_esram0_deep_sleep(u8 state) 340 { 341 return db8500_prcmu_config_esram0_deep_sleep(state); 342 } 343 344 static inline int prcmu_config_hotdog(u8 threshold) 345 { 346 return db8500_prcmu_config_hotdog(threshold); 347 } 348 349 static inline int prcmu_config_hotmon(u8 low, u8 high) 350 { 351 return db8500_prcmu_config_hotmon(low, high); 352 } 353 354 static inline int prcmu_start_temp_sense(u16 cycles32k) 355 { 356 return db8500_prcmu_start_temp_sense(cycles32k); 357 } 358 359 static inline int prcmu_stop_temp_sense(void) 360 { 361 return db8500_prcmu_stop_temp_sense(); 362 } 363 364 static inline u32 prcmu_read(unsigned int reg) 365 { 366 return db8500_prcmu_read(reg); 367 } 368 369 static inline void prcmu_write(unsigned int reg, u32 value) 370 { 371 db8500_prcmu_write(reg, value); 372 } 373 374 static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value) 375 { 376 db8500_prcmu_write_masked(reg, mask, value); 377 } 378 379 static inline int prcmu_enable_a9wdog(u8 id) 380 { 381 return db8500_prcmu_enable_a9wdog(id); 382 } 383 384 static inline int prcmu_disable_a9wdog(u8 id) 385 { 386 return db8500_prcmu_disable_a9wdog(id); 387 } 388 389 static inline int prcmu_kick_a9wdog(u8 id) 390 { 391 return db8500_prcmu_kick_a9wdog(id); 392 } 393 394 static inline int prcmu_load_a9wdog(u8 id, u32 timeout) 395 { 396 return db8500_prcmu_load_a9wdog(id, timeout); 397 } 398 399 static inline int prcmu_config_a9wdog(u8 num, bool sleep_auto_off) 400 { 401 return db8500_prcmu_config_a9wdog(num, sleep_auto_off); 402 } 403 #else 404 405 static inline void prcmu_early_init(void) {} 406 407 static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk, 408 bool keep_ap_pll) 409 { 410 return 0; 411 } 412 413 static inline int prcmu_set_epod(u16 epod_id, u8 epod_state) 414 { 415 return 0; 416 } 417 418 static inline void prcmu_enable_wakeups(u32 wakeups) {} 419 420 static inline void prcmu_disable_wakeups(void) {} 421 422 static inline int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size) 423 { 424 return -ENOSYS; 425 } 426 427 static inline int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size) 428 { 429 return -ENOSYS; 430 } 431 432 static inline int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask, 433 u8 size) 434 { 435 return -ENOSYS; 436 } 437 438 static inline int prcmu_config_clkout(u8 clkout, u8 source, u8 div) 439 { 440 return 0; 441 } 442 443 static inline int prcmu_request_clock(u8 clock, bool enable) 444 { 445 return 0; 446 } 447 448 static inline long prcmu_round_clock_rate(u8 clock, unsigned long rate) 449 { 450 return 0; 451 } 452 453 static inline int prcmu_set_clock_rate(u8 clock, unsigned long rate) 454 { 455 return 0; 456 } 457 458 static inline unsigned long prcmu_clock_rate(u8 clock) 459 { 460 return 0; 461 } 462 463 static inline int prcmu_set_ape_opp(u8 opp) 464 { 465 return 0; 466 } 467 468 static inline int prcmu_get_ape_opp(void) 469 { 470 return APE_100_OPP; 471 } 472 473 static inline int prcmu_request_ape_opp_100_voltage(bool enable) 474 { 475 return 0; 476 } 477 478 static inline int prcmu_set_arm_opp(u8 opp) 479 { 480 return 0; 481 } 482 483 static inline int prcmu_get_arm_opp(void) 484 { 485 return ARM_100_OPP; 486 } 487 488 static inline int prcmu_get_ddr_opp(void) 489 { 490 return DDR_100_OPP; 491 } 492 493 static inline void prcmu_system_reset(u16 reset_code) {} 494 495 static inline u16 prcmu_get_reset_code(void) 496 { 497 return 0; 498 } 499 500 static inline int prcmu_ac_wake_req(void) 501 { 502 return 0; 503 } 504 505 static inline void prcmu_ac_sleep_req(void) {} 506 507 static inline void prcmu_modem_reset(void) {} 508 509 static inline bool prcmu_is_ac_wake_requested(void) 510 { 511 return false; 512 } 513 514 static inline int prcmu_set_display_clocks(void) 515 { 516 return 0; 517 } 518 519 static inline int prcmu_disable_dsipll(void) 520 { 521 return 0; 522 } 523 524 static inline int prcmu_enable_dsipll(void) 525 { 526 return 0; 527 } 528 529 static inline int prcmu_config_esram0_deep_sleep(u8 state) 530 { 531 return 0; 532 } 533 534 static inline void prcmu_config_abb_event_readout(u32 abb_events) {} 535 536 static inline void prcmu_get_abb_event_buffer(void __iomem **buf) 537 { 538 *buf = NULL; 539 } 540 541 static inline int prcmu_config_hotdog(u8 threshold) 542 { 543 return 0; 544 } 545 546 static inline int prcmu_config_hotmon(u8 low, u8 high) 547 { 548 return 0; 549 } 550 551 static inline int prcmu_start_temp_sense(u16 cycles32k) 552 { 553 return 0; 554 } 555 556 static inline int prcmu_stop_temp_sense(void) 557 { 558 return 0; 559 } 560 561 static inline u32 prcmu_read(unsigned int reg) 562 { 563 return 0; 564 } 565 566 static inline void prcmu_write(unsigned int reg, u32 value) {} 567 568 static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value) {} 569 570 #endif 571 572 static inline void prcmu_set(unsigned int reg, u32 bits) 573 { 574 prcmu_write_masked(reg, bits, bits); 575 } 576 577 static inline void prcmu_clear(unsigned int reg, u32 bits) 578 { 579 prcmu_write_masked(reg, bits, 0); 580 } 581 582 /* PRCMU QoS APE OPP class */ 583 #define PRCMU_QOS_APE_OPP 1 584 #define PRCMU_QOS_DDR_OPP 2 585 #define PRCMU_QOS_ARM_OPP 3 586 #define PRCMU_QOS_DEFAULT_VALUE -1 587 588 #ifdef CONFIG_DBX500_PRCMU_QOS_POWER 589 590 unsigned long prcmu_qos_get_cpufreq_opp_delay(void); 591 void prcmu_qos_set_cpufreq_opp_delay(unsigned long); 592 void prcmu_qos_force_opp(int, s32); 593 int prcmu_qos_requirement(int pm_qos_class); 594 int prcmu_qos_add_requirement(int pm_qos_class, char *name, s32 value); 595 int prcmu_qos_update_requirement(int pm_qos_class, char *name, s32 new_value); 596 void prcmu_qos_remove_requirement(int pm_qos_class, char *name); 597 int prcmu_qos_add_notifier(int prcmu_qos_class, 598 struct notifier_block *notifier); 599 int prcmu_qos_remove_notifier(int prcmu_qos_class, 600 struct notifier_block *notifier); 601 602 #else 603 604 static inline unsigned long prcmu_qos_get_cpufreq_opp_delay(void) 605 { 606 return 0; 607 } 608 609 static inline void prcmu_qos_set_cpufreq_opp_delay(unsigned long n) {} 610 611 static inline void prcmu_qos_force_opp(int prcmu_qos_class, s32 i) {} 612 613 static inline int prcmu_qos_requirement(int prcmu_qos_class) 614 { 615 return 0; 616 } 617 618 static inline int prcmu_qos_add_requirement(int prcmu_qos_class, 619 char *name, s32 value) 620 { 621 return 0; 622 } 623 624 static inline int prcmu_qos_update_requirement(int prcmu_qos_class, 625 char *name, s32 new_value) 626 { 627 return 0; 628 } 629 630 static inline void prcmu_qos_remove_requirement(int prcmu_qos_class, char *name) 631 { 632 } 633 634 static inline int prcmu_qos_add_notifier(int prcmu_qos_class, 635 struct notifier_block *notifier) 636 { 637 return 0; 638 } 639 static inline int prcmu_qos_remove_notifier(int prcmu_qos_class, 640 struct notifier_block *notifier) 641 { 642 return 0; 643 } 644 645 #endif 646 647 #endif /* __MACH_PRCMU_H */ 648