1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Functions to access LP87565 power management chip. 4 * 5 * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ 6 */ 7 8 #ifndef __LINUX_MFD_LP87565_H 9 #define __LINUX_MFD_LP87565_H 10 11 #include <linux/i2c.h> 12 #include <linux/regulator/driver.h> 13 #include <linux/regulator/machine.h> 14 15 enum lp87565_device_type { 16 LP87565_DEVICE_TYPE_UNKNOWN = 0, 17 LP87565_DEVICE_TYPE_LP87565_Q1, 18 }; 19 20 /* All register addresses */ 21 #define LP87565_REG_DEV_REV 0X00 22 #define LP87565_REG_OTP_REV 0X01 23 #define LP87565_REG_BUCK0_CTRL_1 0X02 24 #define LP87565_REG_BUCK0_CTRL_2 0X03 25 26 #define LP87565_REG_BUCK1_CTRL_1 0X04 27 #define LP87565_REG_BUCK1_CTRL_2 0X05 28 29 #define LP87565_REG_BUCK2_CTRL_1 0X06 30 #define LP87565_REG_BUCK2_CTRL_2 0X07 31 32 #define LP87565_REG_BUCK3_CTRL_1 0X08 33 #define LP87565_REG_BUCK3_CTRL_2 0X09 34 35 #define LP87565_REG_BUCK0_VOUT 0X0A 36 #define LP87565_REG_BUCK0_FLOOR_VOUT 0X0B 37 38 #define LP87565_REG_BUCK1_VOUT 0X0C 39 #define LP87565_REG_BUCK1_FLOOR_VOUT 0X0D 40 41 #define LP87565_REG_BUCK2_VOUT 0X0E 42 #define LP87565_REG_BUCK2_FLOOR_VOUT 0X0F 43 44 #define LP87565_REG_BUCK3_VOUT 0X10 45 #define LP87565_REG_BUCK3_FLOOR_VOUT 0X11 46 47 #define LP87565_REG_BUCK0_DELAY 0X12 48 #define LP87565_REG_BUCK1_DELAY 0X13 49 50 #define LP87565_REG_BUCK2_DELAY 0X14 51 #define LP87565_REG_BUCK3_DELAY 0X15 52 53 #define LP87565_REG_GPO2_DELAY 0X16 54 #define LP87565_REG_GPO3_DELAY 0X17 55 #define LP87565_REG_RESET 0X18 56 #define LP87565_REG_CONFIG 0X19 57 58 #define LP87565_REG_INT_TOP_1 0X1A 59 #define LP87565_REG_INT_TOP_2 0X1B 60 61 #define LP87565_REG_INT_BUCK_0_1 0X1C 62 #define LP87565_REG_INT_BUCK_2_3 0X1D 63 #define LP87565_REG_TOP_STAT 0X1E 64 #define LP87565_REG_BUCK_0_1_STAT 0X1F 65 #define LP87565_REG_BUCK_2_3_STAT 0x20 66 67 #define LP87565_REG_TOP_MASK_1 0x21 68 #define LP87565_REG_TOP_MASK_2 0x22 69 70 #define LP87565_REG_BUCK_0_1_MASK 0x23 71 #define LP87565_REG_BUCK_2_3_MASK 0x24 72 #define LP87565_REG_SEL_I_LOAD 0x25 73 74 #define LP87565_REG_I_LOAD_2 0x26 75 #define LP87565_REG_I_LOAD_1 0x27 76 77 #define LP87565_REG_PGOOD_CTRL1 0x28 78 #define LP87565_REG_PGOOD_CTRL2 0x29 79 #define LP87565_REG_PGOOD_FLT 0x2A 80 #define LP87565_REG_PLL_CTRL 0x2B 81 #define LP87565_REG_PIN_FUNCTION 0x2C 82 #define LP87565_REG_GPIO_CONFIG 0x2D 83 #define LP87565_REG_GPIO_IN 0x2E 84 #define LP87565_REG_GPIO_OUT 0x2F 85 86 #define LP87565_REG_MAX LP87565_REG_GPIO_OUT 87 88 /* Register field definitions */ 89 #define LP87565_DEV_REV_DEV_ID 0xC0 90 #define LP87565_DEV_REV_ALL_LAYER 0x30 91 #define LP87565_DEV_REV_METAL_LAYER 0x0F 92 93 #define LP87565_OTP_REV_OTP_ID 0xFF 94 95 #define LP87565_BUCK_CTRL_1_EN BIT(7) 96 #define LP87565_BUCK_CTRL_1_EN_PIN_CTRL BIT(6) 97 #define LP87565_BUCK_CTRL_1_PIN_SELECT_EN 0x30 98 99 #define LP87565_BUCK_CTRL_1_ROOF_FLOOR_EN BIT(3) 100 #define LP87565_BUCK_CTRL_1_RDIS_EN BIT(2) 101 #define LP87565_BUCK_CTRL_1_FPWM BIT(1) 102 /* Bit0 is reserved for BUCK1 and BUCK3 and valid only for BUCK0 and BUCK2 */ 103 #define LP87565_BUCK_CTRL_1_FPWM_MP_0_2 BIT(0) 104 105 #define LP87565_BUCK_CTRL_2_ILIM 0x38 106 #define LP87565_BUCK_CTRL_2_SLEW_RATE 0x07 107 108 #define LP87565_BUCK_VSET 0xFF 109 #define LP87565_BUCK_FLOOR_VSET 0xFF 110 111 #define LP87565_BUCK_SHUTDOWN_DELAY 0xF0 112 #define LP87565_BUCK_STARTUP_DELAY 0x0F 113 114 #define LP87565_GPIO_SHUTDOWN_DELAY 0xF0 115 #define LP87565_GPIO_STARTUP_DELAY 0x0F 116 117 #define LP87565_RESET_SW_RESET BIT(0) 118 119 #define LP87565_CONFIG_DOUBLE_DELAY BIT(7) 120 #define LP87565_CONFIG_CLKIN_PD BIT(6) 121 #define LP87565_CONFIG_EN4_PD BIT(5) 122 #define LP87565_CONFIG_EN3_PD BIT(4) 123 #define LP87565_CONFIG_TDIE_WARN_LEVEL BIT(3) 124 #define LP87565_CONFIG_EN2_PD BIT(2) 125 #define LP87565_CONFIG_EN1_PD BIT(1) 126 127 #define LP87565_INT_GPIO BIT(7) 128 #define LP87565_INT_BUCK23 BIT(6) 129 #define LP87565_INT_BUCK01 BIT(5) 130 #define LP87565_NO_SYNC_CLK BIT(4) 131 #define LP87565_TDIE_SD BIT(3) 132 #define LP87565_TDIE_WARN BIT(2) 133 #define LP87565_INT_OVP BIT(1) 134 #define LP87565_I_LOAD_READY BIT(0) 135 136 #define LP87565_INT_TOP2_RESET_REG BIT(0) 137 138 #define LP87565_BUCK1_PG_INT BIT(6) 139 #define LP87565_BUCK1_SC_INT BIT(5) 140 #define LP87565_BUCK1_ILIM_INT BIT(4) 141 #define LP87565_BUCK0_PG_INT BIT(2) 142 #define LP87565_BUCK0_SC_INT BIT(1) 143 #define LP87565_BUCK0_ILIM_INT BIT(0) 144 145 #define LP87565_BUCK3_PG_INT BIT(6) 146 #define LP87565_BUCK3_SC_INT BIT(5) 147 #define LP87565_BUCK3_ILIM_INT BIT(4) 148 #define LP87565_BUCK2_PG_INT BIT(2) 149 #define LP87565_BUCK2_SC_INT BIT(1) 150 #define LP87565_BUCK2_ILIM_INT BIT(0) 151 152 #define LP87565_SYNC_CLK_STAT BIT(4) 153 #define LP87565_TDIE_SD_STAT BIT(3) 154 #define LP87565_TDIE_WARN_STAT BIT(2) 155 #define LP87565_OVP_STAT BIT(1) 156 157 #define LP87565_BUCK1_STAT BIT(7) 158 #define LP87565_BUCK1_PG_STAT BIT(6) 159 #define LP87565_BUCK1_ILIM_STAT BIT(4) 160 #define LP87565_BUCK0_STAT BIT(3) 161 #define LP87565_BUCK0_PG_STAT BIT(2) 162 #define LP87565_BUCK0_ILIM_STAT BIT(0) 163 164 #define LP87565_BUCK3_STAT BIT(7) 165 #define LP87565_BUCK3_PG_STAT BIT(6) 166 #define LP87565_BUCK3_ILIM_STAT BIT(4) 167 #define LP87565_BUCK2_STAT BIT(3) 168 #define LP87565_BUCK2_PG_STAT BIT(2) 169 #define LP87565_BUCK2_ILIM_STAT BIT(0) 170 171 #define LPL87565_GPIO_MASK BIT(7) 172 #define LPL87565_SYNC_CLK_MASK BIT(4) 173 #define LPL87565_TDIE_WARN_MASK BIT(2) 174 #define LPL87565_I_LOAD_READY_MASK BIT(0) 175 176 #define LPL87565_RESET_REG_MASK BIT(0) 177 178 #define LPL87565_BUCK1_PG_MASK BIT(6) 179 #define LPL87565_BUCK1_ILIM_MASK BIT(4) 180 #define LPL87565_BUCK0_PG_MASK BIT(2) 181 #define LPL87565_BUCK0_ILIM_MASK BIT(0) 182 183 #define LPL87565_BUCK3_PG_MASK BIT(6) 184 #define LPL87565_BUCK3_ILIM_MASK BIT(4) 185 #define LPL87565_BUCK2_PG_MASK BIT(2) 186 #define LPL87565_BUCK2_ILIM_MASK BIT(0) 187 188 #define LP87565_LOAD_CURRENT_BUCK_SELECT 0x3 189 190 #define LP87565_I_LOAD2_BUCK_LOAD_CURRENT 0x3 191 #define LP87565_I_LOAD1_BUCK_LOAD_CURRENT 0xFF 192 193 #define LP87565_PG3_SEL 0xC0 194 #define LP87565_PG2_SEL 0x30 195 #define LP87565_PG1_SEL 0x0C 196 #define LP87565_PG0_SEL 0x03 197 198 #define LP87565_HALF_DAY BIT(7) 199 #define LP87565_EN_PG0_NINT BIT(6) 200 #define LP87565_PGOOD_SET_DELAY BIT(5) 201 #define LP87565_EN_PGFLT_STAT BIT(4) 202 #define LP87565_PGOOD_WINDOW BIT(2) 203 #define LP87565_PGOOD_OD BIT(1) 204 #define LP87565_PGOOD_POL BIT(0) 205 206 #define LP87565_PG3_FLT BIT(3) 207 #define LP87565_PG2_FLT BIT(2) 208 #define LP87565_PG1_FLT BIT(1) 209 #define LP87565_PG0_FLT BIT(0) 210 211 #define LP87565_PLL_MODE 0xC0 212 #define LP87565_EXT_CLK_FREQ 0x1F 213 214 #define LP87565_EN_SPREAD_SPEC BIT(7) 215 #define LP87565_EN_PIN_CTRL_GPIO3 BIT(6) 216 #define LP87565_EN_PIN_SELECT_GPIO3 BIT(5) 217 #define LP87565_EN_PIN_CTRL_GPIO2 BIT(4) 218 #define LP87565_EN_PIN_SELECT_GPIO2 BIT(3) 219 #define LP87565_GPIO3_SEL BIT(2) 220 #define LP87565_GPIO2_SEL BIT(1) 221 #define LP87565_GPIO1_SEL BIT(0) 222 223 #define LP87565_GOIO3_OD BIT(6) 224 #define LP87565_GOIO2_OD BIT(5) 225 #define LP87565_GOIO1_OD BIT(4) 226 #define LP87565_GOIO3_DIR BIT(2) 227 #define LP87565_GOIO2_DIR BIT(1) 228 #define LP87565_GOIO1_DIR BIT(0) 229 230 #define LP87565_GOIO3_IN BIT(2) 231 #define LP87565_GOIO2_IN BIT(1) 232 #define LP87565_GOIO1_IN BIT(0) 233 234 #define LP87565_GOIO3_OUT BIT(2) 235 #define LP87565_GOIO2_OUT BIT(1) 236 #define LP87565_GOIO1_OUT BIT(0) 237 238 /* Number of step-down converters available */ 239 #define LP87565_NUM_BUCK 6 240 241 enum LP87565_regulator_id { 242 /* BUCK's */ 243 LP87565_BUCK_0, 244 LP87565_BUCK_1, 245 LP87565_BUCK_2, 246 LP87565_BUCK_3, 247 LP87565_BUCK_10, 248 LP87565_BUCK_23, 249 }; 250 251 /** 252 * struct LP87565 - state holder for the LP87565 driver 253 * @dev: struct device pointer for MFD device 254 * @rev: revision of the LP87565 255 * @dev_type: The device type for example lp87565-q1 256 * @lock: lock guarding the data structure 257 * @regmap: register map of the LP87565 PMIC 258 * 259 * Device data may be used to access the LP87565 chip 260 */ 261 struct lp87565 { 262 struct device *dev; 263 u8 rev; 264 u8 dev_type; 265 struct regmap *regmap; 266 }; 267 #endif /* __LINUX_MFD_LP87565_H */ 268