1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef MFD_TMIO_H 3 #define MFD_TMIO_H 4 5 #include <linux/device.h> 6 #include <linux/fb.h> 7 #include <linux/io.h> 8 #include <linux/jiffies.h> 9 #include <linux/mmc/card.h> 10 #include <linux/platform_device.h> 11 #include <linux/pm_runtime.h> 12 13 #define tmio_ioread8(addr) readb(addr) 14 #define tmio_ioread16(addr) readw(addr) 15 #define tmio_ioread16_rep(r, b, l) readsw(r, b, l) 16 #define tmio_ioread32(addr) \ 17 (((u32)readw((addr))) | (((u32)readw((addr) + 2)) << 16)) 18 19 #define tmio_iowrite8(val, addr) writeb((val), (addr)) 20 #define tmio_iowrite16(val, addr) writew((val), (addr)) 21 #define tmio_iowrite16_rep(r, b, l) writesw(r, b, l) 22 #define tmio_iowrite32(val, addr) \ 23 do { \ 24 writew((val), (addr)); \ 25 writew((val) >> 16, (addr) + 2); \ 26 } while (0) 27 28 #define sd_config_write8(base, shift, reg, val) \ 29 tmio_iowrite8((val), (base) + ((reg) << (shift))) 30 #define sd_config_write16(base, shift, reg, val) \ 31 tmio_iowrite16((val), (base) + ((reg) << (shift))) 32 #define sd_config_write32(base, shift, reg, val) \ 33 do { \ 34 tmio_iowrite16((val), (base) + ((reg) << (shift))); \ 35 tmio_iowrite16((val) >> 16, (base) + ((reg + 2) << (shift))); \ 36 } while (0) 37 38 /* tmio MMC platform flags */ 39 /* 40 * Some controllers can support a 2-byte block size when the bus width 41 * is configured in 4-bit mode. 42 */ 43 #define TMIO_MMC_BLKSZ_2BYTES BIT(1) 44 /* 45 * Some controllers can support SDIO IRQ signalling. 46 */ 47 #define TMIO_MMC_SDIO_IRQ BIT(2) 48 49 /* Some features are only available or tested on R-Car Gen2 or later */ 50 #define TMIO_MMC_MIN_RCAR2 BIT(3) 51 52 /* 53 * Some controllers require waiting for the SD bus to become 54 * idle before writing to some registers. 55 */ 56 #define TMIO_MMC_HAS_IDLE_WAIT BIT(4) 57 58 /* BIT(5) is unused */ 59 60 /* 61 * Some controllers have CMD12 automatically 62 * issue/non-issue register 63 */ 64 #define TMIO_MMC_HAVE_CMD12_CTRL BIT(7) 65 66 /* Controller has some SDIO status bits which must be 1 */ 67 #define TMIO_MMC_SDIO_STATUS_SETBITS BIT(8) 68 69 /* 70 * Some controllers have a 32-bit wide data port register 71 */ 72 #define TMIO_MMC_32BIT_DATA_PORT BIT(9) 73 74 /* 75 * Some controllers allows to set SDx actual clock 76 */ 77 #define TMIO_MMC_CLK_ACTUAL BIT(10) 78 79 /* Some controllers have a CBSY bit */ 80 #define TMIO_MMC_HAVE_CBSY BIT(11) 81 82 /* Some controllers that support HS400 use 4 taps while others use 8. */ 83 #define TMIO_MMC_HAVE_4TAP_HS400 BIT(13) 84 85 int tmio_core_mmc_enable(void __iomem *cnf, int shift, unsigned long base); 86 int tmio_core_mmc_resume(void __iomem *cnf, int shift, unsigned long base); 87 void tmio_core_mmc_pwr(void __iomem *cnf, int shift, int state); 88 void tmio_core_mmc_clk_div(void __iomem *cnf, int shift, int state); 89 90 struct dma_chan; 91 92 /* 93 * data for the MMC controller 94 */ 95 struct tmio_mmc_data { 96 void *chan_priv_tx; 97 void *chan_priv_rx; 98 unsigned int hclk; 99 unsigned long capabilities; 100 unsigned long capabilities2; 101 unsigned long flags; 102 u32 ocr_mask; /* available voltages */ 103 int alignment_shift; 104 dma_addr_t dma_rx_offset; 105 unsigned int max_blk_count; 106 unsigned short max_segs; 107 void (*set_pwr)(struct platform_device *host, int state); 108 void (*set_clk_div)(struct platform_device *host, int state); 109 }; 110 111 /* 112 * data for the NAND controller 113 */ 114 struct tmio_nand_data { 115 struct nand_bbt_descr *badblock_pattern; 116 struct mtd_partition *partition; 117 unsigned int num_partitions; 118 const char *const *part_parsers; 119 }; 120 121 #define FBIO_TMIO_ACC_WRITE 0x7C639300 122 #define FBIO_TMIO_ACC_SYNC 0x7C639301 123 124 struct tmio_fb_data { 125 int (*lcd_set_power)(struct platform_device *fb_dev, 126 bool on); 127 int (*lcd_mode)(struct platform_device *fb_dev, 128 const struct fb_videomode *mode); 129 int num_modes; 130 struct fb_videomode *modes; 131 132 /* in mm: size of screen */ 133 int height; 134 int width; 135 }; 136 137 #endif 138