xref: /linux/include/linux/mlx5/device.h (revision 52338415)
1 /*
2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32 
33 #ifndef MLX5_DEVICE_H
34 #define MLX5_DEVICE_H
35 
36 #include <linux/types.h>
37 #include <rdma/ib_verbs.h>
38 #include <linux/mlx5/mlx5_ifc.h>
39 
40 #if defined(__LITTLE_ENDIAN)
41 #define MLX5_SET_HOST_ENDIANNESS	0
42 #elif defined(__BIG_ENDIAN)
43 #define MLX5_SET_HOST_ENDIANNESS	0x80
44 #else
45 #error Host endianness not defined
46 #endif
47 
48 /* helper macros */
49 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
50 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
51 #define __mlx5_bit_off(typ, fld) (offsetof(struct mlx5_ifc_##typ##_bits, fld))
52 #define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16)
53 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
54 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
55 #define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0xf))
56 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f))
57 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
58 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld))
59 #define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
60 #define __mlx5_16_mask(typ, fld) (__mlx5_mask16(typ, fld) << __mlx5_16_bit_off(typ, fld))
61 #define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits)
62 
63 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
64 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
65 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
66 #define MLX5_ST_SZ_QW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 64)
67 #define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8)
68 #define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32)
69 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
70 #define MLX5_ADDR_OF(typ, p, fld) ((void *)((uint8_t *)(p) + MLX5_BYTE_OFF(typ, fld)))
71 
72 /* insert a value to a struct */
73 #define MLX5_SET(typ, p, fld, v) do { \
74 	u32 _v = v; \
75 	BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32);             \
76 	*((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
77 	cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
78 		     (~__mlx5_dw_mask(typ, fld))) | (((_v) & __mlx5_mask(typ, fld)) \
79 		     << __mlx5_dw_bit_off(typ, fld))); \
80 } while (0)
81 
82 #define MLX5_ARRAY_SET(typ, p, fld, idx, v) do { \
83 	BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 32); \
84 	MLX5_SET(typ, p, fld[idx], v); \
85 } while (0)
86 
87 #define MLX5_SET_TO_ONES(typ, p, fld) do { \
88 	BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32);             \
89 	*((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
90 	cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
91 		     (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \
92 		     << __mlx5_dw_bit_off(typ, fld))); \
93 } while (0)
94 
95 #define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\
96 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
97 __mlx5_mask(typ, fld))
98 
99 #define MLX5_GET_PR(typ, p, fld) ({ \
100 	u32 ___t = MLX5_GET(typ, p, fld); \
101 	pr_debug(#fld " = 0x%x\n", ___t); \
102 	___t; \
103 })
104 
105 #define __MLX5_SET64(typ, p, fld, v) do { \
106 	BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \
107 	*((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \
108 } while (0)
109 
110 #define MLX5_SET64(typ, p, fld, v) do { \
111 	BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
112 	__MLX5_SET64(typ, p, fld, v); \
113 } while (0)
114 
115 #define MLX5_ARRAY_SET64(typ, p, fld, idx, v) do { \
116 	BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
117 	__MLX5_SET64(typ, p, fld[idx], v); \
118 } while (0)
119 
120 #define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld)))
121 
122 #define MLX5_GET64_PR(typ, p, fld) ({ \
123 	u64 ___t = MLX5_GET64(typ, p, fld); \
124 	pr_debug(#fld " = 0x%llx\n", ___t); \
125 	___t; \
126 })
127 
128 #define MLX5_GET16(typ, p, fld) ((be16_to_cpu(*((__be16 *)(p) +\
129 __mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \
130 __mlx5_mask16(typ, fld))
131 
132 #define MLX5_SET16(typ, p, fld, v) do { \
133 	u16 _v = v; \
134 	BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 16);             \
135 	*((__be16 *)(p) + __mlx5_16_off(typ, fld)) = \
136 	cpu_to_be16((be16_to_cpu(*((__be16 *)(p) + __mlx5_16_off(typ, fld))) & \
137 		     (~__mlx5_16_mask(typ, fld))) | (((_v) & __mlx5_mask16(typ, fld)) \
138 		     << __mlx5_16_bit_off(typ, fld))); \
139 } while (0)
140 
141 /* Big endian getters */
142 #define MLX5_GET64_BE(typ, p, fld) (*((__be64 *)(p) +\
143 	__mlx5_64_off(typ, fld)))
144 
145 #define MLX5_GET_BE(type_t, typ, p, fld) ({				  \
146 		type_t tmp;						  \
147 		switch (sizeof(tmp)) {					  \
148 		case sizeof(u8):					  \
149 			tmp = (__force type_t)MLX5_GET(typ, p, fld);	  \
150 			break;						  \
151 		case sizeof(u16):					  \
152 			tmp = (__force type_t)cpu_to_be16(MLX5_GET(typ, p, fld)); \
153 			break;						  \
154 		case sizeof(u32):					  \
155 			tmp = (__force type_t)cpu_to_be32(MLX5_GET(typ, p, fld)); \
156 			break;						  \
157 		case sizeof(u64):					  \
158 			tmp = (__force type_t)MLX5_GET64_BE(typ, p, fld); \
159 			break;						  \
160 			}						  \
161 		tmp;							  \
162 		})
163 
164 enum mlx5_inline_modes {
165 	MLX5_INLINE_MODE_NONE,
166 	MLX5_INLINE_MODE_L2,
167 	MLX5_INLINE_MODE_IP,
168 	MLX5_INLINE_MODE_TCP_UDP,
169 };
170 
171 enum {
172 	MLX5_MAX_COMMANDS		= 32,
173 	MLX5_CMD_DATA_BLOCK_SIZE	= 512,
174 	MLX5_PCI_CMD_XPORT		= 7,
175 	MLX5_MKEY_BSF_OCTO_SIZE		= 4,
176 	MLX5_MAX_PSVS			= 4,
177 };
178 
179 enum {
180 	MLX5_EXTENDED_UD_AV		= 0x80000000,
181 };
182 
183 enum {
184 	MLX5_CQ_STATE_ARMED		= 9,
185 	MLX5_CQ_STATE_ALWAYS_ARMED	= 0xb,
186 	MLX5_CQ_STATE_FIRED		= 0xa,
187 };
188 
189 enum {
190 	MLX5_STAT_RATE_OFFSET	= 5,
191 };
192 
193 enum {
194 	MLX5_INLINE_SEG = 0x80000000,
195 };
196 
197 enum {
198 	MLX5_HW_START_PADDING = MLX5_INLINE_SEG,
199 };
200 
201 enum {
202 	MLX5_MIN_PKEY_TABLE_SIZE = 128,
203 	MLX5_MAX_LOG_PKEY_TABLE  = 5,
204 };
205 
206 enum {
207 	MLX5_MKEY_INBOX_PG_ACCESS = 1 << 31
208 };
209 
210 enum {
211 	MLX5_PFAULT_SUBTYPE_WQE = 0,
212 	MLX5_PFAULT_SUBTYPE_RDMA = 1,
213 };
214 
215 enum wqe_page_fault_type {
216 	MLX5_WQE_PF_TYPE_RMP = 0,
217 	MLX5_WQE_PF_TYPE_REQ_SEND_OR_WRITE = 1,
218 	MLX5_WQE_PF_TYPE_RESP = 2,
219 	MLX5_WQE_PF_TYPE_REQ_READ_OR_ATOMIC = 3,
220 };
221 
222 enum {
223 	MLX5_PERM_LOCAL_READ	= 1 << 2,
224 	MLX5_PERM_LOCAL_WRITE	= 1 << 3,
225 	MLX5_PERM_REMOTE_READ	= 1 << 4,
226 	MLX5_PERM_REMOTE_WRITE	= 1 << 5,
227 	MLX5_PERM_ATOMIC	= 1 << 6,
228 	MLX5_PERM_UMR_EN	= 1 << 7,
229 };
230 
231 enum {
232 	MLX5_PCIE_CTRL_SMALL_FENCE	= 1 << 0,
233 	MLX5_PCIE_CTRL_RELAXED_ORDERING	= 1 << 2,
234 	MLX5_PCIE_CTRL_NO_SNOOP		= 1 << 3,
235 	MLX5_PCIE_CTRL_TLP_PROCE_EN	= 1 << 6,
236 	MLX5_PCIE_CTRL_TPH_MASK		= 3 << 4,
237 };
238 
239 enum {
240 	MLX5_EN_RD	= (u64)1,
241 	MLX5_EN_WR	= (u64)2
242 };
243 
244 enum {
245 	MLX5_ADAPTER_PAGE_SHIFT		= 12,
246 	MLX5_ADAPTER_PAGE_SIZE		= 1 << MLX5_ADAPTER_PAGE_SHIFT,
247 };
248 
249 enum {
250 	MLX5_BFREGS_PER_UAR		= 4,
251 	MLX5_MAX_UARS			= 1 << 8,
252 	MLX5_NON_FP_BFREGS_PER_UAR	= 2,
253 	MLX5_FP_BFREGS_PER_UAR		= MLX5_BFREGS_PER_UAR -
254 					  MLX5_NON_FP_BFREGS_PER_UAR,
255 	MLX5_MAX_BFREGS			= MLX5_MAX_UARS *
256 					  MLX5_NON_FP_BFREGS_PER_UAR,
257 	MLX5_UARS_IN_PAGE		= PAGE_SIZE / MLX5_ADAPTER_PAGE_SIZE,
258 	MLX5_NON_FP_BFREGS_IN_PAGE	= MLX5_NON_FP_BFREGS_PER_UAR * MLX5_UARS_IN_PAGE,
259 	MLX5_MIN_DYN_BFREGS		= 512,
260 	MLX5_MAX_DYN_BFREGS		= 1024,
261 };
262 
263 enum {
264 	MLX5_MKEY_MASK_LEN		= 1ull << 0,
265 	MLX5_MKEY_MASK_PAGE_SIZE	= 1ull << 1,
266 	MLX5_MKEY_MASK_START_ADDR	= 1ull << 6,
267 	MLX5_MKEY_MASK_PD		= 1ull << 7,
268 	MLX5_MKEY_MASK_EN_RINVAL	= 1ull << 8,
269 	MLX5_MKEY_MASK_EN_SIGERR	= 1ull << 9,
270 	MLX5_MKEY_MASK_BSF_EN		= 1ull << 12,
271 	MLX5_MKEY_MASK_KEY		= 1ull << 13,
272 	MLX5_MKEY_MASK_QPN		= 1ull << 14,
273 	MLX5_MKEY_MASK_LR		= 1ull << 17,
274 	MLX5_MKEY_MASK_LW		= 1ull << 18,
275 	MLX5_MKEY_MASK_RR		= 1ull << 19,
276 	MLX5_MKEY_MASK_RW		= 1ull << 20,
277 	MLX5_MKEY_MASK_A		= 1ull << 21,
278 	MLX5_MKEY_MASK_SMALL_FENCE	= 1ull << 23,
279 	MLX5_MKEY_MASK_FREE		= 1ull << 29,
280 };
281 
282 enum {
283 	MLX5_UMR_TRANSLATION_OFFSET_EN	= (1 << 4),
284 
285 	MLX5_UMR_CHECK_NOT_FREE		= (1 << 5),
286 	MLX5_UMR_CHECK_FREE		= (2 << 5),
287 
288 	MLX5_UMR_INLINE			= (1 << 7),
289 };
290 
291 #define MLX5_UMR_MTT_ALIGNMENT 0x40
292 #define MLX5_UMR_MTT_MASK      (MLX5_UMR_MTT_ALIGNMENT - 1)
293 #define MLX5_UMR_MTT_MIN_CHUNK_SIZE MLX5_UMR_MTT_ALIGNMENT
294 
295 #define MLX5_USER_INDEX_LEN (MLX5_FLD_SZ_BYTES(qpc, user_index) * 8)
296 
297 enum {
298 	MLX5_EVENT_QUEUE_TYPE_QP = 0,
299 	MLX5_EVENT_QUEUE_TYPE_RQ = 1,
300 	MLX5_EVENT_QUEUE_TYPE_SQ = 2,
301 	MLX5_EVENT_QUEUE_TYPE_DCT = 6,
302 };
303 
304 /* mlx5 components can subscribe to any one of these events via
305  * mlx5_eq_notifier_register API.
306  */
307 enum mlx5_event {
308 	/* Special value to subscribe to any event */
309 	MLX5_EVENT_TYPE_NOTIFY_ANY	   = 0x0,
310 	/* HW events enum start: comp events are not subscribable */
311 	MLX5_EVENT_TYPE_COMP		   = 0x0,
312 	/* HW Async events enum start: subscribable events */
313 	MLX5_EVENT_TYPE_PATH_MIG	   = 0x01,
314 	MLX5_EVENT_TYPE_COMM_EST	   = 0x02,
315 	MLX5_EVENT_TYPE_SQ_DRAINED	   = 0x03,
316 	MLX5_EVENT_TYPE_SRQ_LAST_WQE	   = 0x13,
317 	MLX5_EVENT_TYPE_SRQ_RQ_LIMIT	   = 0x14,
318 
319 	MLX5_EVENT_TYPE_CQ_ERROR	   = 0x04,
320 	MLX5_EVENT_TYPE_WQ_CATAS_ERROR	   = 0x05,
321 	MLX5_EVENT_TYPE_PATH_MIG_FAILED	   = 0x07,
322 	MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
323 	MLX5_EVENT_TYPE_WQ_ACCESS_ERROR	   = 0x11,
324 	MLX5_EVENT_TYPE_SRQ_CATAS_ERROR	   = 0x12,
325 
326 	MLX5_EVENT_TYPE_INTERNAL_ERROR	   = 0x08,
327 	MLX5_EVENT_TYPE_PORT_CHANGE	   = 0x09,
328 	MLX5_EVENT_TYPE_GPIO_EVENT	   = 0x15,
329 	MLX5_EVENT_TYPE_PORT_MODULE_EVENT  = 0x16,
330 	MLX5_EVENT_TYPE_TEMP_WARN_EVENT    = 0x17,
331 	MLX5_EVENT_TYPE_XRQ_ERROR	   = 0x18,
332 	MLX5_EVENT_TYPE_REMOTE_CONFIG	   = 0x19,
333 	MLX5_EVENT_TYPE_GENERAL_EVENT	   = 0x22,
334 	MLX5_EVENT_TYPE_MONITOR_COUNTER    = 0x24,
335 	MLX5_EVENT_TYPE_PPS_EVENT          = 0x25,
336 
337 	MLX5_EVENT_TYPE_DB_BF_CONGESTION   = 0x1a,
338 	MLX5_EVENT_TYPE_STALL_EVENT	   = 0x1b,
339 
340 	MLX5_EVENT_TYPE_CMD		   = 0x0a,
341 	MLX5_EVENT_TYPE_PAGE_REQUEST	   = 0xb,
342 
343 	MLX5_EVENT_TYPE_PAGE_FAULT	   = 0xc,
344 	MLX5_EVENT_TYPE_NIC_VPORT_CHANGE   = 0xd,
345 
346 	MLX5_EVENT_TYPE_ESW_FUNCTIONS_CHANGED = 0xe,
347 
348 	MLX5_EVENT_TYPE_DCT_DRAINED        = 0x1c,
349 	MLX5_EVENT_TYPE_DCT_KEY_VIOLATION  = 0x1d,
350 
351 	MLX5_EVENT_TYPE_FPGA_ERROR         = 0x20,
352 	MLX5_EVENT_TYPE_FPGA_QP_ERROR      = 0x21,
353 
354 	MLX5_EVENT_TYPE_DEVICE_TRACER      = 0x26,
355 
356 	MLX5_EVENT_TYPE_MAX                = 0x100,
357 };
358 
359 enum {
360 	MLX5_TRACER_SUBTYPE_OWNERSHIP_CHANGE = 0x0,
361 	MLX5_TRACER_SUBTYPE_TRACES_AVAILABLE = 0x1,
362 };
363 
364 enum {
365 	MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT = 0x1,
366 	MLX5_GENERAL_SUBTYPE_PCI_POWER_CHANGE_EVENT = 0x5,
367 };
368 
369 enum {
370 	MLX5_PORT_CHANGE_SUBTYPE_DOWN		= 1,
371 	MLX5_PORT_CHANGE_SUBTYPE_ACTIVE		= 4,
372 	MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED	= 5,
373 	MLX5_PORT_CHANGE_SUBTYPE_LID		= 6,
374 	MLX5_PORT_CHANGE_SUBTYPE_PKEY		= 7,
375 	MLX5_PORT_CHANGE_SUBTYPE_GUID		= 8,
376 	MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG	= 9,
377 };
378 
379 enum {
380 	MLX5_DEV_CAP_FLAG_XRC		= 1LL <<  3,
381 	MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR	= 1LL <<  8,
382 	MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR	= 1LL <<  9,
383 	MLX5_DEV_CAP_FLAG_APM		= 1LL << 17,
384 	MLX5_DEV_CAP_FLAG_ATOMIC	= 1LL << 18,
385 	MLX5_DEV_CAP_FLAG_BLOCK_MCAST	= 1LL << 23,
386 	MLX5_DEV_CAP_FLAG_ON_DMND_PG	= 1LL << 24,
387 	MLX5_DEV_CAP_FLAG_CQ_MODER	= 1LL << 29,
388 	MLX5_DEV_CAP_FLAG_RESIZE_CQ	= 1LL << 30,
389 	MLX5_DEV_CAP_FLAG_DCT		= 1LL << 37,
390 	MLX5_DEV_CAP_FLAG_SIG_HAND_OVER	= 1LL << 40,
391 	MLX5_DEV_CAP_FLAG_CMDIF_CSUM	= 3LL << 46,
392 };
393 
394 enum {
395 	MLX5_ROCE_VERSION_1		= 0,
396 	MLX5_ROCE_VERSION_2		= 2,
397 };
398 
399 enum {
400 	MLX5_ROCE_VERSION_1_CAP		= 1 << MLX5_ROCE_VERSION_1,
401 	MLX5_ROCE_VERSION_2_CAP		= 1 << MLX5_ROCE_VERSION_2,
402 };
403 
404 enum {
405 	MLX5_ROCE_L3_TYPE_IPV4		= 0,
406 	MLX5_ROCE_L3_TYPE_IPV6		= 1,
407 };
408 
409 enum {
410 	MLX5_ROCE_L3_TYPE_IPV4_CAP	= 1 << 1,
411 	MLX5_ROCE_L3_TYPE_IPV6_CAP	= 1 << 2,
412 };
413 
414 enum {
415 	MLX5_OPCODE_NOP			= 0x00,
416 	MLX5_OPCODE_SEND_INVAL		= 0x01,
417 	MLX5_OPCODE_RDMA_WRITE		= 0x08,
418 	MLX5_OPCODE_RDMA_WRITE_IMM	= 0x09,
419 	MLX5_OPCODE_SEND		= 0x0a,
420 	MLX5_OPCODE_SEND_IMM		= 0x0b,
421 	MLX5_OPCODE_LSO			= 0x0e,
422 	MLX5_OPCODE_RDMA_READ		= 0x10,
423 	MLX5_OPCODE_ATOMIC_CS		= 0x11,
424 	MLX5_OPCODE_ATOMIC_FA		= 0x12,
425 	MLX5_OPCODE_ATOMIC_MASKED_CS	= 0x14,
426 	MLX5_OPCODE_ATOMIC_MASKED_FA	= 0x15,
427 	MLX5_OPCODE_BIND_MW		= 0x18,
428 	MLX5_OPCODE_CONFIG_CMD		= 0x1f,
429 	MLX5_OPCODE_ENHANCED_MPSW	= 0x29,
430 
431 	MLX5_RECV_OPCODE_RDMA_WRITE_IMM	= 0x00,
432 	MLX5_RECV_OPCODE_SEND		= 0x01,
433 	MLX5_RECV_OPCODE_SEND_IMM	= 0x02,
434 	MLX5_RECV_OPCODE_SEND_INVAL	= 0x03,
435 
436 	MLX5_CQE_OPCODE_ERROR		= 0x1e,
437 	MLX5_CQE_OPCODE_RESIZE		= 0x16,
438 
439 	MLX5_OPCODE_SET_PSV		= 0x20,
440 	MLX5_OPCODE_GET_PSV		= 0x21,
441 	MLX5_OPCODE_CHECK_PSV		= 0x22,
442 	MLX5_OPCODE_DUMP		= 0x23,
443 	MLX5_OPCODE_RGET_PSV		= 0x26,
444 	MLX5_OPCODE_RCHECK_PSV		= 0x27,
445 
446 	MLX5_OPCODE_UMR			= 0x25,
447 
448 };
449 
450 enum {
451 	MLX5_OPC_MOD_TLS_TIS_STATIC_PARAMS = 0x1,
452 };
453 
454 enum {
455 	MLX5_OPC_MOD_TLS_TIS_PROGRESS_PARAMS = 0x1,
456 };
457 
458 enum {
459 	MLX5_SET_PORT_RESET_QKEY	= 0,
460 	MLX5_SET_PORT_GUID0		= 16,
461 	MLX5_SET_PORT_NODE_GUID		= 17,
462 	MLX5_SET_PORT_SYS_GUID		= 18,
463 	MLX5_SET_PORT_GID_TABLE		= 19,
464 	MLX5_SET_PORT_PKEY_TABLE	= 20,
465 };
466 
467 enum {
468 	MLX5_BW_NO_LIMIT   = 0,
469 	MLX5_100_MBPS_UNIT = 3,
470 	MLX5_GBPS_UNIT	   = 4,
471 };
472 
473 enum {
474 	MLX5_MAX_PAGE_SHIFT		= 31
475 };
476 
477 enum {
478 	MLX5_CAP_OFF_CMDIF_CSUM		= 46,
479 };
480 
481 enum {
482 	/*
483 	 * Max wqe size for rdma read is 512 bytes, so this
484 	 * limits our max_sge_rd as the wqe needs to fit:
485 	 * - ctrl segment (16 bytes)
486 	 * - rdma segment (16 bytes)
487 	 * - scatter elements (16 bytes each)
488 	 */
489 	MLX5_MAX_SGE_RD	= (512 - 16 - 16) / 16
490 };
491 
492 enum mlx5_odp_transport_cap_bits {
493 	MLX5_ODP_SUPPORT_SEND	 = 1 << 31,
494 	MLX5_ODP_SUPPORT_RECV	 = 1 << 30,
495 	MLX5_ODP_SUPPORT_WRITE	 = 1 << 29,
496 	MLX5_ODP_SUPPORT_READ	 = 1 << 28,
497 };
498 
499 struct mlx5_odp_caps {
500 	char reserved[0x10];
501 	struct {
502 		__be32			rc_odp_caps;
503 		__be32			uc_odp_caps;
504 		__be32			ud_odp_caps;
505 	} per_transport_caps;
506 	char reserved2[0xe4];
507 };
508 
509 struct mlx5_cmd_layout {
510 	u8		type;
511 	u8		rsvd0[3];
512 	__be32		inlen;
513 	__be64		in_ptr;
514 	__be32		in[4];
515 	__be32		out[4];
516 	__be64		out_ptr;
517 	__be32		outlen;
518 	u8		token;
519 	u8		sig;
520 	u8		rsvd1;
521 	u8		status_own;
522 };
523 
524 enum mlx5_fatal_assert_bit_offsets {
525 	MLX5_RFR_OFFSET = 31,
526 };
527 
528 struct health_buffer {
529 	__be32		assert_var[5];
530 	__be32		rsvd0[3];
531 	__be32		assert_exit_ptr;
532 	__be32		assert_callra;
533 	__be32		rsvd1[2];
534 	__be32		fw_ver;
535 	__be32		hw_id;
536 	__be32		rfr;
537 	u8		irisc_index;
538 	u8		synd;
539 	__be16		ext_synd;
540 };
541 
542 enum mlx5_initializing_bit_offsets {
543 	MLX5_FW_RESET_SUPPORTED_OFFSET = 30,
544 };
545 
546 enum mlx5_cmd_addr_l_sz_offset {
547 	MLX5_NIC_IFC_OFFSET = 8,
548 };
549 
550 struct mlx5_init_seg {
551 	__be32			fw_rev;
552 	__be32			cmdif_rev_fw_sub;
553 	__be32			rsvd0[2];
554 	__be32			cmdq_addr_h;
555 	__be32			cmdq_addr_l_sz;
556 	__be32			cmd_dbell;
557 	__be32			rsvd1[120];
558 	__be32			initializing;
559 	struct health_buffer	health;
560 	__be32			rsvd2[880];
561 	__be32			internal_timer_h;
562 	__be32			internal_timer_l;
563 	__be32			rsvd3[2];
564 	__be32			health_counter;
565 	__be32			rsvd4[1019];
566 	__be64			ieee1588_clk;
567 	__be32			ieee1588_clk_type;
568 	__be32			clr_intx;
569 };
570 
571 struct mlx5_eqe_comp {
572 	__be32	reserved[6];
573 	__be32	cqn;
574 };
575 
576 struct mlx5_eqe_qp_srq {
577 	__be32	reserved1[5];
578 	u8	type;
579 	u8	reserved2[3];
580 	__be32	qp_srq_n;
581 };
582 
583 struct mlx5_eqe_cq_err {
584 	__be32	cqn;
585 	u8	reserved1[7];
586 	u8	syndrome;
587 };
588 
589 struct mlx5_eqe_xrq_err {
590 	__be32	reserved1[5];
591 	__be32	type_xrqn;
592 	__be32	reserved2;
593 };
594 
595 struct mlx5_eqe_port_state {
596 	u8	reserved0[8];
597 	u8	port;
598 };
599 
600 struct mlx5_eqe_gpio {
601 	__be32	reserved0[2];
602 	__be64	gpio_event;
603 };
604 
605 struct mlx5_eqe_congestion {
606 	u8	type;
607 	u8	rsvd0;
608 	u8	congestion_level;
609 };
610 
611 struct mlx5_eqe_stall_vl {
612 	u8	rsvd0[3];
613 	u8	port_vl;
614 };
615 
616 struct mlx5_eqe_cmd {
617 	__be32	vector;
618 	__be32	rsvd[6];
619 };
620 
621 struct mlx5_eqe_page_req {
622 	__be16		ec_function;
623 	__be16		func_id;
624 	__be32		num_pages;
625 	__be32		rsvd1[5];
626 };
627 
628 struct mlx5_eqe_page_fault {
629 	__be32 bytes_committed;
630 	union {
631 		struct {
632 			u16     reserved1;
633 			__be16  wqe_index;
634 			u16	reserved2;
635 			__be16  packet_length;
636 			__be32  token;
637 			u8	reserved4[8];
638 			__be32  pftype_wq;
639 		} __packed wqe;
640 		struct {
641 			__be32  r_key;
642 			u16	reserved1;
643 			__be16  packet_length;
644 			__be32  rdma_op_len;
645 			__be64  rdma_va;
646 			__be32  pftype_token;
647 		} __packed rdma;
648 	} __packed;
649 } __packed;
650 
651 struct mlx5_eqe_vport_change {
652 	u8		rsvd0[2];
653 	__be16		vport_num;
654 	__be32		rsvd1[6];
655 } __packed;
656 
657 struct mlx5_eqe_port_module {
658 	u8        reserved_at_0[1];
659 	u8        module;
660 	u8        reserved_at_2[1];
661 	u8        module_status;
662 	u8        reserved_at_4[2];
663 	u8        error_type;
664 } __packed;
665 
666 struct mlx5_eqe_pps {
667 	u8		rsvd0[3];
668 	u8		pin;
669 	u8		rsvd1[4];
670 	union {
671 		struct {
672 			__be32		time_sec;
673 			__be32		time_nsec;
674 		};
675 		struct {
676 			__be64		time_stamp;
677 		};
678 	};
679 	u8		rsvd2[12];
680 } __packed;
681 
682 struct mlx5_eqe_dct {
683 	__be32  reserved[6];
684 	__be32  dctn;
685 };
686 
687 struct mlx5_eqe_temp_warning {
688 	__be64 sensor_warning_msb;
689 	__be64 sensor_warning_lsb;
690 } __packed;
691 
692 union ev_data {
693 	__be32				raw[7];
694 	struct mlx5_eqe_cmd		cmd;
695 	struct mlx5_eqe_comp		comp;
696 	struct mlx5_eqe_qp_srq		qp_srq;
697 	struct mlx5_eqe_cq_err		cq_err;
698 	struct mlx5_eqe_port_state	port;
699 	struct mlx5_eqe_gpio		gpio;
700 	struct mlx5_eqe_congestion	cong;
701 	struct mlx5_eqe_stall_vl	stall_vl;
702 	struct mlx5_eqe_page_req	req_pages;
703 	struct mlx5_eqe_page_fault	page_fault;
704 	struct mlx5_eqe_vport_change	vport_change;
705 	struct mlx5_eqe_port_module	port_module;
706 	struct mlx5_eqe_pps		pps;
707 	struct mlx5_eqe_dct             dct;
708 	struct mlx5_eqe_temp_warning	temp_warning;
709 	struct mlx5_eqe_xrq_err		xrq_err;
710 } __packed;
711 
712 struct mlx5_eqe {
713 	u8		rsvd0;
714 	u8		type;
715 	u8		rsvd1;
716 	u8		sub_type;
717 	__be32		rsvd2[7];
718 	union ev_data	data;
719 	__be16		rsvd3;
720 	u8		signature;
721 	u8		owner;
722 } __packed;
723 
724 struct mlx5_cmd_prot_block {
725 	u8		data[MLX5_CMD_DATA_BLOCK_SIZE];
726 	u8		rsvd0[48];
727 	__be64		next;
728 	__be32		block_num;
729 	u8		rsvd1;
730 	u8		token;
731 	u8		ctrl_sig;
732 	u8		sig;
733 };
734 
735 enum {
736 	MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5,
737 };
738 
739 struct mlx5_err_cqe {
740 	u8	rsvd0[32];
741 	__be32	srqn;
742 	u8	rsvd1[18];
743 	u8	vendor_err_synd;
744 	u8	syndrome;
745 	__be32	s_wqe_opcode_qpn;
746 	__be16	wqe_counter;
747 	u8	signature;
748 	u8	op_own;
749 };
750 
751 struct mlx5_cqe64 {
752 	u8		outer_l3_tunneled;
753 	u8		rsvd0;
754 	__be16		wqe_id;
755 	u8		lro_tcppsh_abort_dupack;
756 	u8		lro_min_ttl;
757 	__be16		lro_tcp_win;
758 	__be32		lro_ack_seq_num;
759 	__be32		rss_hash_result;
760 	u8		rss_hash_type;
761 	u8		ml_path;
762 	u8		rsvd20[2];
763 	__be16		check_sum;
764 	__be16		slid;
765 	__be32		flags_rqpn;
766 	u8		hds_ip_ext;
767 	u8		l4_l3_hdr_type;
768 	__be16		vlan_info;
769 	__be32		srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */
770 	__be32		imm_inval_pkey;
771 	u8		rsvd40[4];
772 	__be32		byte_cnt;
773 	__be32		timestamp_h;
774 	__be32		timestamp_l;
775 	__be32		sop_drop_qpn;
776 	__be16		wqe_counter;
777 	u8		signature;
778 	u8		op_own;
779 };
780 
781 struct mlx5_mini_cqe8 {
782 	union {
783 		__be32 rx_hash_result;
784 		struct {
785 			__be16 checksum;
786 			__be16 rsvd;
787 		};
788 		struct {
789 			__be16 wqe_counter;
790 			u8  s_wqe_opcode;
791 			u8  reserved;
792 		} s_wqe_info;
793 	};
794 	__be32 byte_cnt;
795 };
796 
797 enum {
798 	MLX5_NO_INLINE_DATA,
799 	MLX5_INLINE_DATA32_SEG,
800 	MLX5_INLINE_DATA64_SEG,
801 	MLX5_COMPRESSED,
802 };
803 
804 enum {
805 	MLX5_CQE_FORMAT_CSUM = 0x1,
806 };
807 
808 #define MLX5_MINI_CQE_ARRAY_SIZE 8
809 
810 static inline u8 mlx5_get_cqe_format(struct mlx5_cqe64 *cqe)
811 {
812 	return (cqe->op_own >> 2) & 0x3;
813 }
814 
815 static inline u8 get_cqe_opcode(struct mlx5_cqe64 *cqe)
816 {
817 	return cqe->op_own >> 4;
818 }
819 
820 static inline u8 get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe)
821 {
822 	return (cqe->lro_tcppsh_abort_dupack >> 6) & 1;
823 }
824 
825 static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe)
826 {
827 	return (cqe->l4_l3_hdr_type >> 4) & 0x7;
828 }
829 
830 static inline u8 get_cqe_l3_hdr_type(struct mlx5_cqe64 *cqe)
831 {
832 	return (cqe->l4_l3_hdr_type >> 2) & 0x3;
833 }
834 
835 static inline bool cqe_is_tunneled(struct mlx5_cqe64 *cqe)
836 {
837 	return cqe->outer_l3_tunneled & 0x1;
838 }
839 
840 static inline bool cqe_has_vlan(struct mlx5_cqe64 *cqe)
841 {
842 	return cqe->l4_l3_hdr_type & 0x1;
843 }
844 
845 static inline u64 get_cqe_ts(struct mlx5_cqe64 *cqe)
846 {
847 	u32 hi, lo;
848 
849 	hi = be32_to_cpu(cqe->timestamp_h);
850 	lo = be32_to_cpu(cqe->timestamp_l);
851 
852 	return (u64)lo | ((u64)hi << 32);
853 }
854 
855 #define MLX5_MPWQE_LOG_NUM_STRIDES_BASE	(9)
856 #define MLX5_MPWQE_LOG_STRIDE_SZ_BASE	(6)
857 
858 struct mpwrq_cqe_bc {
859 	__be16	filler_consumed_strides;
860 	__be16	byte_cnt;
861 };
862 
863 static inline u16 mpwrq_get_cqe_byte_cnt(struct mlx5_cqe64 *cqe)
864 {
865 	struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
866 
867 	return be16_to_cpu(bc->byte_cnt);
868 }
869 
870 static inline u16 mpwrq_get_cqe_bc_consumed_strides(struct mpwrq_cqe_bc *bc)
871 {
872 	return 0x7fff & be16_to_cpu(bc->filler_consumed_strides);
873 }
874 
875 static inline u16 mpwrq_get_cqe_consumed_strides(struct mlx5_cqe64 *cqe)
876 {
877 	struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
878 
879 	return mpwrq_get_cqe_bc_consumed_strides(bc);
880 }
881 
882 static inline bool mpwrq_is_filler_cqe(struct mlx5_cqe64 *cqe)
883 {
884 	struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
885 
886 	return 0x8000 & be16_to_cpu(bc->filler_consumed_strides);
887 }
888 
889 static inline u16 mpwrq_get_cqe_stride_index(struct mlx5_cqe64 *cqe)
890 {
891 	return be16_to_cpu(cqe->wqe_counter);
892 }
893 
894 enum {
895 	CQE_L4_HDR_TYPE_NONE			= 0x0,
896 	CQE_L4_HDR_TYPE_TCP_NO_ACK		= 0x1,
897 	CQE_L4_HDR_TYPE_UDP			= 0x2,
898 	CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA		= 0x3,
899 	CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA	= 0x4,
900 };
901 
902 enum {
903 	CQE_RSS_HTYPE_IP	= 0x3 << 2,
904 	/* cqe->rss_hash_type[3:2] - IP destination selected for hash
905 	 * (00 = none,  01 = IPv4, 10 = IPv6, 11 = Reserved)
906 	 */
907 	CQE_RSS_HTYPE_L4	= 0x3 << 6,
908 	/* cqe->rss_hash_type[7:6] - L4 destination selected for hash
909 	 * (00 = none, 01 = TCP. 10 = UDP, 11 = IPSEC.SPI
910 	 */
911 };
912 
913 enum {
914 	MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH	= 0x0,
915 	MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6	= 0x1,
916 	MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4	= 0x2,
917 };
918 
919 enum {
920 	CQE_L2_OK	= 1 << 0,
921 	CQE_L3_OK	= 1 << 1,
922 	CQE_L4_OK	= 1 << 2,
923 };
924 
925 struct mlx5_sig_err_cqe {
926 	u8		rsvd0[16];
927 	__be32		expected_trans_sig;
928 	__be32		actual_trans_sig;
929 	__be32		expected_reftag;
930 	__be32		actual_reftag;
931 	__be16		syndrome;
932 	u8		rsvd22[2];
933 	__be32		mkey;
934 	__be64		err_offset;
935 	u8		rsvd30[8];
936 	__be32		qpn;
937 	u8		rsvd38[2];
938 	u8		signature;
939 	u8		op_own;
940 };
941 
942 struct mlx5_wqe_srq_next_seg {
943 	u8			rsvd0[2];
944 	__be16			next_wqe_index;
945 	u8			signature;
946 	u8			rsvd1[11];
947 };
948 
949 union mlx5_ext_cqe {
950 	struct ib_grh	grh;
951 	u8		inl[64];
952 };
953 
954 struct mlx5_cqe128 {
955 	union mlx5_ext_cqe	inl_grh;
956 	struct mlx5_cqe64	cqe64;
957 };
958 
959 enum {
960 	MLX5_MKEY_STATUS_FREE = 1 << 6,
961 };
962 
963 enum {
964 	MLX5_MKEY_REMOTE_INVAL	= 1 << 24,
965 	MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29,
966 	MLX5_MKEY_BSF_EN	= 1 << 30,
967 	MLX5_MKEY_LEN64		= 1 << 31,
968 };
969 
970 struct mlx5_mkey_seg {
971 	/* This is a two bit field occupying bits 31-30.
972 	 * bit 31 is always 0,
973 	 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation
974 	 */
975 	u8		status;
976 	u8		pcie_control;
977 	u8		flags;
978 	u8		version;
979 	__be32		qpn_mkey7_0;
980 	u8		rsvd1[4];
981 	__be32		flags_pd;
982 	__be64		start_addr;
983 	__be64		len;
984 	__be32		bsfs_octo_size;
985 	u8		rsvd2[16];
986 	__be32		xlt_oct_size;
987 	u8		rsvd3[3];
988 	u8		log2_page_size;
989 	u8		rsvd4[4];
990 };
991 
992 #define MLX5_ATTR_EXTENDED_PORT_INFO	cpu_to_be16(0xff90)
993 
994 enum {
995 	MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO	= 1 <<  0
996 };
997 
998 enum {
999 	VPORT_STATE_DOWN		= 0x0,
1000 	VPORT_STATE_UP			= 0x1,
1001 };
1002 
1003 enum {
1004 	MLX5_VPORT_ADMIN_STATE_DOWN  = 0x0,
1005 	MLX5_VPORT_ADMIN_STATE_UP    = 0x1,
1006 	MLX5_VPORT_ADMIN_STATE_AUTO  = 0x2,
1007 };
1008 
1009 enum {
1010 	MLX5_L3_PROT_TYPE_IPV4		= 0,
1011 	MLX5_L3_PROT_TYPE_IPV6		= 1,
1012 };
1013 
1014 enum {
1015 	MLX5_L4_PROT_TYPE_TCP		= 0,
1016 	MLX5_L4_PROT_TYPE_UDP		= 1,
1017 };
1018 
1019 enum {
1020 	MLX5_HASH_FIELD_SEL_SRC_IP	= 1 << 0,
1021 	MLX5_HASH_FIELD_SEL_DST_IP	= 1 << 1,
1022 	MLX5_HASH_FIELD_SEL_L4_SPORT	= 1 << 2,
1023 	MLX5_HASH_FIELD_SEL_L4_DPORT	= 1 << 3,
1024 	MLX5_HASH_FIELD_SEL_IPSEC_SPI	= 1 << 4,
1025 };
1026 
1027 enum {
1028 	MLX5_MATCH_OUTER_HEADERS	= 1 << 0,
1029 	MLX5_MATCH_MISC_PARAMETERS	= 1 << 1,
1030 	MLX5_MATCH_INNER_HEADERS	= 1 << 2,
1031 	MLX5_MATCH_MISC_PARAMETERS_2	= 1 << 3,
1032 	MLX5_MATCH_MISC_PARAMETERS_3	= 1 << 4,
1033 };
1034 
1035 enum {
1036 	MLX5_FLOW_TABLE_TYPE_NIC_RCV	= 0,
1037 	MLX5_FLOW_TABLE_TYPE_ESWITCH	= 4,
1038 };
1039 
1040 enum {
1041 	MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT	= 0,
1042 	MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE	= 1,
1043 	MLX5_FLOW_CONTEXT_DEST_TYPE_TIR		= 2,
1044 };
1045 
1046 enum mlx5_list_type {
1047 	MLX5_NVPRT_LIST_TYPE_UC   = 0x0,
1048 	MLX5_NVPRT_LIST_TYPE_MC   = 0x1,
1049 	MLX5_NVPRT_LIST_TYPE_VLAN = 0x2,
1050 };
1051 
1052 enum {
1053 	MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
1054 	MLX5_RQC_RQ_TYPE_MEMORY_RQ_RPM    = 0x1,
1055 };
1056 
1057 enum mlx5_wol_mode {
1058 	MLX5_WOL_DISABLE        = 0,
1059 	MLX5_WOL_SECURED_MAGIC  = 1 << 1,
1060 	MLX5_WOL_MAGIC          = 1 << 2,
1061 	MLX5_WOL_ARP            = 1 << 3,
1062 	MLX5_WOL_BROADCAST      = 1 << 4,
1063 	MLX5_WOL_MULTICAST      = 1 << 5,
1064 	MLX5_WOL_UNICAST        = 1 << 6,
1065 	MLX5_WOL_PHY_ACTIVITY   = 1 << 7,
1066 };
1067 
1068 enum mlx5_mpls_supported_fields {
1069 	MLX5_FIELD_SUPPORT_MPLS_LABEL = 1 << 0,
1070 	MLX5_FIELD_SUPPORT_MPLS_EXP   = 1 << 1,
1071 	MLX5_FIELD_SUPPORT_MPLS_S_BOS = 1 << 2,
1072 	MLX5_FIELD_SUPPORT_MPLS_TTL   = 1 << 3
1073 };
1074 
1075 enum mlx5_flex_parser_protos {
1076 	MLX5_FLEX_PROTO_GENEVE	      = 1 << 3,
1077 	MLX5_FLEX_PROTO_CW_MPLS_GRE   = 1 << 4,
1078 	MLX5_FLEX_PROTO_CW_MPLS_UDP   = 1 << 5,
1079 };
1080 
1081 /* MLX5 DEV CAPs */
1082 
1083 /* TODO: EAT.ME */
1084 enum mlx5_cap_mode {
1085 	HCA_CAP_OPMOD_GET_MAX	= 0,
1086 	HCA_CAP_OPMOD_GET_CUR	= 1,
1087 };
1088 
1089 enum mlx5_cap_type {
1090 	MLX5_CAP_GENERAL = 0,
1091 	MLX5_CAP_ETHERNET_OFFLOADS,
1092 	MLX5_CAP_ODP,
1093 	MLX5_CAP_ATOMIC,
1094 	MLX5_CAP_ROCE,
1095 	MLX5_CAP_IPOIB_OFFLOADS,
1096 	MLX5_CAP_IPOIB_ENHANCED_OFFLOADS,
1097 	MLX5_CAP_FLOW_TABLE,
1098 	MLX5_CAP_ESWITCH_FLOW_TABLE,
1099 	MLX5_CAP_ESWITCH,
1100 	MLX5_CAP_RESERVED,
1101 	MLX5_CAP_VECTOR_CALC,
1102 	MLX5_CAP_QOS,
1103 	MLX5_CAP_DEBUG,
1104 	MLX5_CAP_RESERVED_14,
1105 	MLX5_CAP_DEV_MEM,
1106 	MLX5_CAP_RESERVED_16,
1107 	MLX5_CAP_TLS,
1108 	MLX5_CAP_DEV_EVENT = 0x14,
1109 	/* NUM OF CAP Types */
1110 	MLX5_CAP_NUM
1111 };
1112 
1113 enum mlx5_pcam_reg_groups {
1114 	MLX5_PCAM_REGS_5000_TO_507F                 = 0x0,
1115 };
1116 
1117 enum mlx5_pcam_feature_groups {
1118 	MLX5_PCAM_FEATURE_ENHANCED_FEATURES         = 0x0,
1119 };
1120 
1121 enum mlx5_mcam_reg_groups {
1122 	MLX5_MCAM_REGS_FIRST_128                    = 0x0,
1123 };
1124 
1125 enum mlx5_mcam_feature_groups {
1126 	MLX5_MCAM_FEATURE_ENHANCED_FEATURES         = 0x0,
1127 };
1128 
1129 enum mlx5_qcam_reg_groups {
1130 	MLX5_QCAM_REGS_FIRST_128                    = 0x0,
1131 };
1132 
1133 enum mlx5_qcam_feature_groups {
1134 	MLX5_QCAM_FEATURE_ENHANCED_FEATURES         = 0x0,
1135 };
1136 
1137 /* GET Dev Caps macros */
1138 #define MLX5_CAP_GEN(mdev, cap) \
1139 	MLX5_GET(cmd_hca_cap, mdev->caps.hca_cur[MLX5_CAP_GENERAL], cap)
1140 
1141 #define MLX5_CAP_GEN_64(mdev, cap) \
1142 	MLX5_GET64(cmd_hca_cap, mdev->caps.hca_cur[MLX5_CAP_GENERAL], cap)
1143 
1144 #define MLX5_CAP_GEN_MAX(mdev, cap) \
1145 	MLX5_GET(cmd_hca_cap, mdev->caps.hca_max[MLX5_CAP_GENERAL], cap)
1146 
1147 #define MLX5_CAP_ETH(mdev, cap) \
1148 	MLX5_GET(per_protocol_networking_offload_caps,\
1149 		 mdev->caps.hca_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1150 
1151 #define MLX5_CAP_ETH_MAX(mdev, cap) \
1152 	MLX5_GET(per_protocol_networking_offload_caps,\
1153 		 mdev->caps.hca_max[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1154 
1155 #define MLX5_CAP_IPOIB_ENHANCED(mdev, cap) \
1156 	MLX5_GET(per_protocol_networking_offload_caps,\
1157 		 mdev->caps.hca_cur[MLX5_CAP_IPOIB_ENHANCED_OFFLOADS], cap)
1158 
1159 #define MLX5_CAP_ROCE(mdev, cap) \
1160 	MLX5_GET(roce_cap, mdev->caps.hca_cur[MLX5_CAP_ROCE], cap)
1161 
1162 #define MLX5_CAP_ROCE_MAX(mdev, cap) \
1163 	MLX5_GET(roce_cap, mdev->caps.hca_max[MLX5_CAP_ROCE], cap)
1164 
1165 #define MLX5_CAP_ATOMIC(mdev, cap) \
1166 	MLX5_GET(atomic_caps, mdev->caps.hca_cur[MLX5_CAP_ATOMIC], cap)
1167 
1168 #define MLX5_CAP_ATOMIC_MAX(mdev, cap) \
1169 	MLX5_GET(atomic_caps, mdev->caps.hca_max[MLX5_CAP_ATOMIC], cap)
1170 
1171 #define MLX5_CAP_FLOWTABLE(mdev, cap) \
1172 	MLX5_GET(flow_table_nic_cap, mdev->caps.hca_cur[MLX5_CAP_FLOW_TABLE], cap)
1173 
1174 #define MLX5_CAP64_FLOWTABLE(mdev, cap) \
1175 	MLX5_GET64(flow_table_nic_cap, (mdev)->caps.hca_cur[MLX5_CAP_FLOW_TABLE], cap)
1176 
1177 #define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \
1178 	MLX5_GET(flow_table_nic_cap, mdev->caps.hca_max[MLX5_CAP_FLOW_TABLE], cap)
1179 
1180 #define MLX5_CAP_FLOWTABLE_NIC_RX(mdev, cap) \
1181 	MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.cap)
1182 
1183 #define MLX5_CAP_FLOWTABLE_NIC_RX_MAX(mdev, cap) \
1184 	MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive.cap)
1185 
1186 #define MLX5_CAP_FLOWTABLE_NIC_TX(mdev, cap) \
1187 		MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit.cap)
1188 
1189 #define MLX5_CAP_FLOWTABLE_NIC_TX_MAX(mdev, cap) \
1190 	MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit.cap)
1191 
1192 #define MLX5_CAP_FLOWTABLE_SNIFFER_RX(mdev, cap) \
1193 	MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_sniffer.cap)
1194 
1195 #define MLX5_CAP_FLOWTABLE_SNIFFER_RX_MAX(mdev, cap) \
1196 	MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive_sniffer.cap)
1197 
1198 #define MLX5_CAP_FLOWTABLE_SNIFFER_TX(mdev, cap) \
1199 	MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_sniffer.cap)
1200 
1201 #define MLX5_CAP_FLOWTABLE_SNIFFER_TX_MAX(mdev, cap) \
1202 	MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit_sniffer.cap)
1203 
1204 #define MLX5_CAP_FLOWTABLE_RDMA_RX(mdev, cap) \
1205 	MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_rdma.cap)
1206 
1207 #define MLX5_CAP_FLOWTABLE_RDMA_RX_MAX(mdev, cap) \
1208 	MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive_rdma.cap)
1209 
1210 #define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \
1211 	MLX5_GET(flow_table_eswitch_cap, \
1212 		 mdev->caps.hca_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1213 
1214 #define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \
1215 	MLX5_GET(flow_table_eswitch_cap, \
1216 		 mdev->caps.hca_max[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1217 
1218 #define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \
1219 	MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap)
1220 
1221 #define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \
1222 	MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_nic_esw_fdb.cap)
1223 
1224 #define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \
1225 	MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_egress.cap)
1226 
1227 #define MLX5_CAP_ESW_EGRESS_ACL_MAX(mdev, cap) \
1228 	MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_egress.cap)
1229 
1230 #define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \
1231 	MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_ingress.cap)
1232 
1233 #define MLX5_CAP_ESW_INGRESS_ACL_MAX(mdev, cap) \
1234 	MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_ingress.cap)
1235 
1236 #define MLX5_CAP_ESW(mdev, cap) \
1237 	MLX5_GET(e_switch_cap, \
1238 		 mdev->caps.hca_cur[MLX5_CAP_ESWITCH], cap)
1239 
1240 #define MLX5_CAP64_ESW_FLOWTABLE(mdev, cap) \
1241 	MLX5_GET64(flow_table_eswitch_cap, \
1242 		(mdev)->caps.hca_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1243 
1244 #define MLX5_CAP_ESW_MAX(mdev, cap) \
1245 	MLX5_GET(e_switch_cap, \
1246 		 mdev->caps.hca_max[MLX5_CAP_ESWITCH], cap)
1247 
1248 #define MLX5_CAP_ODP(mdev, cap)\
1249 	MLX5_GET(odp_cap, mdev->caps.hca_cur[MLX5_CAP_ODP], cap)
1250 
1251 #define MLX5_CAP_ODP_MAX(mdev, cap)\
1252 	MLX5_GET(odp_cap, mdev->caps.hca_max[MLX5_CAP_ODP], cap)
1253 
1254 #define MLX5_CAP_VECTOR_CALC(mdev, cap) \
1255 	MLX5_GET(vector_calc_cap, \
1256 		 mdev->caps.hca_cur[MLX5_CAP_VECTOR_CALC], cap)
1257 
1258 #define MLX5_CAP_QOS(mdev, cap)\
1259 	MLX5_GET(qos_cap, mdev->caps.hca_cur[MLX5_CAP_QOS], cap)
1260 
1261 #define MLX5_CAP_DEBUG(mdev, cap)\
1262 	MLX5_GET(debug_cap, mdev->caps.hca_cur[MLX5_CAP_DEBUG], cap)
1263 
1264 #define MLX5_CAP_PCAM_FEATURE(mdev, fld) \
1265 	MLX5_GET(pcam_reg, (mdev)->caps.pcam, feature_cap_mask.enhanced_features.fld)
1266 
1267 #define MLX5_CAP_PCAM_REG(mdev, reg) \
1268 	MLX5_GET(pcam_reg, (mdev)->caps.pcam, port_access_reg_cap_mask.regs_5000_to_507f.reg)
1269 
1270 #define MLX5_CAP_MCAM_REG(mdev, reg) \
1271 	MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_access_reg_cap_mask.access_regs.reg)
1272 
1273 #define MLX5_CAP_MCAM_FEATURE(mdev, fld) \
1274 	MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_feature_cap_mask.enhanced_features.fld)
1275 
1276 #define MLX5_CAP_QCAM_REG(mdev, fld) \
1277 	MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_access_reg_cap_mask.reg_cap.fld)
1278 
1279 #define MLX5_CAP_QCAM_FEATURE(mdev, fld) \
1280 	MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_feature_cap_mask.feature_cap.fld)
1281 
1282 #define MLX5_CAP_FPGA(mdev, cap) \
1283 	MLX5_GET(fpga_cap, (mdev)->caps.fpga, cap)
1284 
1285 #define MLX5_CAP64_FPGA(mdev, cap) \
1286 	MLX5_GET64(fpga_cap, (mdev)->caps.fpga, cap)
1287 
1288 #define MLX5_CAP_DEV_MEM(mdev, cap)\
1289 	MLX5_GET(device_mem_cap, mdev->caps.hca_cur[MLX5_CAP_DEV_MEM], cap)
1290 
1291 #define MLX5_CAP64_DEV_MEM(mdev, cap)\
1292 	MLX5_GET64(device_mem_cap, mdev->caps.hca_cur[MLX5_CAP_DEV_MEM], cap)
1293 
1294 #define MLX5_CAP_TLS(mdev, cap) \
1295 	MLX5_GET(tls_cap, (mdev)->caps.hca_cur[MLX5_CAP_TLS], cap)
1296 
1297 #define MLX5_CAP_DEV_EVENT(mdev, cap)\
1298 	MLX5_ADDR_OF(device_event_cap, (mdev)->caps.hca_cur[MLX5_CAP_DEV_EVENT], cap)
1299 
1300 enum {
1301 	MLX5_CMD_STAT_OK			= 0x0,
1302 	MLX5_CMD_STAT_INT_ERR			= 0x1,
1303 	MLX5_CMD_STAT_BAD_OP_ERR		= 0x2,
1304 	MLX5_CMD_STAT_BAD_PARAM_ERR		= 0x3,
1305 	MLX5_CMD_STAT_BAD_SYS_STATE_ERR		= 0x4,
1306 	MLX5_CMD_STAT_BAD_RES_ERR		= 0x5,
1307 	MLX5_CMD_STAT_RES_BUSY			= 0x6,
1308 	MLX5_CMD_STAT_LIM_ERR			= 0x8,
1309 	MLX5_CMD_STAT_BAD_RES_STATE_ERR		= 0x9,
1310 	MLX5_CMD_STAT_IX_ERR			= 0xa,
1311 	MLX5_CMD_STAT_NO_RES_ERR		= 0xf,
1312 	MLX5_CMD_STAT_BAD_INP_LEN_ERR		= 0x50,
1313 	MLX5_CMD_STAT_BAD_OUTP_LEN_ERR		= 0x51,
1314 	MLX5_CMD_STAT_BAD_QP_STATE_ERR		= 0x10,
1315 	MLX5_CMD_STAT_BAD_PKT_ERR		= 0x30,
1316 	MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR	= 0x40,
1317 };
1318 
1319 enum {
1320 	MLX5_IEEE_802_3_COUNTERS_GROUP	      = 0x0,
1321 	MLX5_RFC_2863_COUNTERS_GROUP	      = 0x1,
1322 	MLX5_RFC_2819_COUNTERS_GROUP	      = 0x2,
1323 	MLX5_RFC_3635_COUNTERS_GROUP	      = 0x3,
1324 	MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP = 0x5,
1325 	MLX5_PER_PRIORITY_COUNTERS_GROUP      = 0x10,
1326 	MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP = 0x11,
1327 	MLX5_PHYSICAL_LAYER_COUNTERS_GROUP    = 0x12,
1328 	MLX5_PER_TRAFFIC_CLASS_CONGESTION_GROUP = 0x13,
1329 	MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP = 0x16,
1330 	MLX5_INFINIBAND_PORT_COUNTERS_GROUP   = 0x20,
1331 };
1332 
1333 enum {
1334 	MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP       = 0x0,
1335 };
1336 
1337 static inline u16 mlx5_to_sw_pkey_sz(int pkey_sz)
1338 {
1339 	if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE)
1340 		return 0;
1341 	return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz;
1342 }
1343 
1344 #define MLX5_BY_PASS_NUM_REGULAR_PRIOS 16
1345 #define MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS 16
1346 #define MLX5_BY_PASS_NUM_MULTICAST_PRIOS 1
1347 #define MLX5_BY_PASS_NUM_PRIOS (MLX5_BY_PASS_NUM_REGULAR_PRIOS +\
1348 				MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS +\
1349 				MLX5_BY_PASS_NUM_MULTICAST_PRIOS)
1350 
1351 #endif /* MLX5_DEVICE_H */
1352