1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Definitions for the NVM Express interface 4 * Copyright (c) 2011-2014, Intel Corporation. 5 */ 6 7 #ifndef _LINUX_NVME_H 8 #define _LINUX_NVME_H 9 10 #include <linux/types.h> 11 #include <linux/uuid.h> 12 13 /* NQN names in commands fields specified one size */ 14 #define NVMF_NQN_FIELD_LEN 256 15 16 /* However the max length of a qualified name is another size */ 17 #define NVMF_NQN_SIZE 223 18 19 #define NVMF_TRSVCID_SIZE 32 20 #define NVMF_TRADDR_SIZE 256 21 #define NVMF_TSAS_SIZE 256 22 23 #define NVME_DISC_SUBSYS_NAME "nqn.2014-08.org.nvmexpress.discovery" 24 25 #define NVME_RDMA_IP_PORT 4420 26 27 #define NVME_NSID_ALL 0xffffffff 28 29 enum nvme_subsys_type { 30 NVME_NQN_DISC = 1, /* Discovery type target subsystem */ 31 NVME_NQN_NVME = 2, /* NVME type target subsystem */ 32 }; 33 34 /* Address Family codes for Discovery Log Page entry ADRFAM field */ 35 enum { 36 NVMF_ADDR_FAMILY_PCI = 0, /* PCIe */ 37 NVMF_ADDR_FAMILY_IP4 = 1, /* IP4 */ 38 NVMF_ADDR_FAMILY_IP6 = 2, /* IP6 */ 39 NVMF_ADDR_FAMILY_IB = 3, /* InfiniBand */ 40 NVMF_ADDR_FAMILY_FC = 4, /* Fibre Channel */ 41 }; 42 43 /* Transport Type codes for Discovery Log Page entry TRTYPE field */ 44 enum { 45 NVMF_TRTYPE_RDMA = 1, /* RDMA */ 46 NVMF_TRTYPE_FC = 2, /* Fibre Channel */ 47 NVMF_TRTYPE_TCP = 3, /* TCP/IP */ 48 NVMF_TRTYPE_LOOP = 254, /* Reserved for host usage */ 49 NVMF_TRTYPE_MAX, 50 }; 51 52 /* Transport Requirements codes for Discovery Log Page entry TREQ field */ 53 enum { 54 NVMF_TREQ_NOT_SPECIFIED = 0, /* Not specified */ 55 NVMF_TREQ_REQUIRED = 1, /* Required */ 56 NVMF_TREQ_NOT_REQUIRED = 2, /* Not Required */ 57 #define NVME_TREQ_SECURE_CHANNEL_MASK \ 58 (NVMF_TREQ_REQUIRED | NVMF_TREQ_NOT_REQUIRED) 59 60 NVMF_TREQ_DISABLE_SQFLOW = (1 << 2), /* Supports SQ flow control disable */ 61 }; 62 63 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS 64 * RDMA_QPTYPE field 65 */ 66 enum { 67 NVMF_RDMA_QPTYPE_CONNECTED = 1, /* Reliable Connected */ 68 NVMF_RDMA_QPTYPE_DATAGRAM = 2, /* Reliable Datagram */ 69 }; 70 71 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS 72 * RDMA_QPTYPE field 73 */ 74 enum { 75 NVMF_RDMA_PRTYPE_NOT_SPECIFIED = 1, /* No Provider Specified */ 76 NVMF_RDMA_PRTYPE_IB = 2, /* InfiniBand */ 77 NVMF_RDMA_PRTYPE_ROCE = 3, /* InfiniBand RoCE */ 78 NVMF_RDMA_PRTYPE_ROCEV2 = 4, /* InfiniBand RoCEV2 */ 79 NVMF_RDMA_PRTYPE_IWARP = 5, /* IWARP */ 80 }; 81 82 /* RDMA Connection Management Service Type codes for Discovery Log Page 83 * entry TSAS RDMA_CMS field 84 */ 85 enum { 86 NVMF_RDMA_CMS_RDMA_CM = 1, /* Sockets based endpoint addressing */ 87 }; 88 89 #define NVME_AQ_DEPTH 32 90 #define NVME_NR_AEN_COMMANDS 1 91 #define NVME_AQ_BLK_MQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS) 92 93 /* 94 * Subtract one to leave an empty queue entry for 'Full Queue' condition. See 95 * NVM-Express 1.2 specification, section 4.1.2. 96 */ 97 #define NVME_AQ_MQ_TAG_DEPTH (NVME_AQ_BLK_MQ_DEPTH - 1) 98 99 enum { 100 NVME_REG_CAP = 0x0000, /* Controller Capabilities */ 101 NVME_REG_VS = 0x0008, /* Version */ 102 NVME_REG_INTMS = 0x000c, /* Interrupt Mask Set */ 103 NVME_REG_INTMC = 0x0010, /* Interrupt Mask Clear */ 104 NVME_REG_CC = 0x0014, /* Controller Configuration */ 105 NVME_REG_CSTS = 0x001c, /* Controller Status */ 106 NVME_REG_NSSR = 0x0020, /* NVM Subsystem Reset */ 107 NVME_REG_AQA = 0x0024, /* Admin Queue Attributes */ 108 NVME_REG_ASQ = 0x0028, /* Admin SQ Base Address */ 109 NVME_REG_ACQ = 0x0030, /* Admin CQ Base Address */ 110 NVME_REG_CMBLOC = 0x0038, /* Controller Memory Buffer Location */ 111 NVME_REG_CMBSZ = 0x003c, /* Controller Memory Buffer Size */ 112 NVME_REG_DBS = 0x1000, /* SQ 0 Tail Doorbell */ 113 }; 114 115 #define NVME_CAP_MQES(cap) ((cap) & 0xffff) 116 #define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff) 117 #define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf) 118 #define NVME_CAP_NSSRC(cap) (((cap) >> 36) & 0x1) 119 #define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf) 120 #define NVME_CAP_MPSMAX(cap) (((cap) >> 52) & 0xf) 121 122 #define NVME_CMB_BIR(cmbloc) ((cmbloc) & 0x7) 123 #define NVME_CMB_OFST(cmbloc) (((cmbloc) >> 12) & 0xfffff) 124 125 enum { 126 NVME_CMBSZ_SQS = 1 << 0, 127 NVME_CMBSZ_CQS = 1 << 1, 128 NVME_CMBSZ_LISTS = 1 << 2, 129 NVME_CMBSZ_RDS = 1 << 3, 130 NVME_CMBSZ_WDS = 1 << 4, 131 132 NVME_CMBSZ_SZ_SHIFT = 12, 133 NVME_CMBSZ_SZ_MASK = 0xfffff, 134 135 NVME_CMBSZ_SZU_SHIFT = 8, 136 NVME_CMBSZ_SZU_MASK = 0xf, 137 }; 138 139 /* 140 * Submission and Completion Queue Entry Sizes for the NVM command set. 141 * (In bytes and specified as a power of two (2^n)). 142 */ 143 #define NVME_ADM_SQES 6 144 #define NVME_NVM_IOSQES 6 145 #define NVME_NVM_IOCQES 4 146 147 enum { 148 NVME_CC_ENABLE = 1 << 0, 149 NVME_CC_CSS_NVM = 0 << 4, 150 NVME_CC_EN_SHIFT = 0, 151 NVME_CC_CSS_SHIFT = 4, 152 NVME_CC_MPS_SHIFT = 7, 153 NVME_CC_AMS_SHIFT = 11, 154 NVME_CC_SHN_SHIFT = 14, 155 NVME_CC_IOSQES_SHIFT = 16, 156 NVME_CC_IOCQES_SHIFT = 20, 157 NVME_CC_AMS_RR = 0 << NVME_CC_AMS_SHIFT, 158 NVME_CC_AMS_WRRU = 1 << NVME_CC_AMS_SHIFT, 159 NVME_CC_AMS_VS = 7 << NVME_CC_AMS_SHIFT, 160 NVME_CC_SHN_NONE = 0 << NVME_CC_SHN_SHIFT, 161 NVME_CC_SHN_NORMAL = 1 << NVME_CC_SHN_SHIFT, 162 NVME_CC_SHN_ABRUPT = 2 << NVME_CC_SHN_SHIFT, 163 NVME_CC_SHN_MASK = 3 << NVME_CC_SHN_SHIFT, 164 NVME_CC_IOSQES = NVME_NVM_IOSQES << NVME_CC_IOSQES_SHIFT, 165 NVME_CC_IOCQES = NVME_NVM_IOCQES << NVME_CC_IOCQES_SHIFT, 166 NVME_CSTS_RDY = 1 << 0, 167 NVME_CSTS_CFS = 1 << 1, 168 NVME_CSTS_NSSRO = 1 << 4, 169 NVME_CSTS_PP = 1 << 5, 170 NVME_CSTS_SHST_NORMAL = 0 << 2, 171 NVME_CSTS_SHST_OCCUR = 1 << 2, 172 NVME_CSTS_SHST_CMPLT = 2 << 2, 173 NVME_CSTS_SHST_MASK = 3 << 2, 174 }; 175 176 struct nvme_id_power_state { 177 __le16 max_power; /* centiwatts */ 178 __u8 rsvd2; 179 __u8 flags; 180 __le32 entry_lat; /* microseconds */ 181 __le32 exit_lat; /* microseconds */ 182 __u8 read_tput; 183 __u8 read_lat; 184 __u8 write_tput; 185 __u8 write_lat; 186 __le16 idle_power; 187 __u8 idle_scale; 188 __u8 rsvd19; 189 __le16 active_power; 190 __u8 active_work_scale; 191 __u8 rsvd23[9]; 192 }; 193 194 enum { 195 NVME_PS_FLAGS_MAX_POWER_SCALE = 1 << 0, 196 NVME_PS_FLAGS_NON_OP_STATE = 1 << 1, 197 }; 198 199 enum nvme_ctrl_attr { 200 NVME_CTRL_ATTR_HID_128_BIT = (1 << 0), 201 NVME_CTRL_ATTR_TBKAS = (1 << 6), 202 }; 203 204 struct nvme_id_ctrl { 205 __le16 vid; 206 __le16 ssvid; 207 char sn[20]; 208 char mn[40]; 209 char fr[8]; 210 __u8 rab; 211 __u8 ieee[3]; 212 __u8 cmic; 213 __u8 mdts; 214 __le16 cntlid; 215 __le32 ver; 216 __le32 rtd3r; 217 __le32 rtd3e; 218 __le32 oaes; 219 __le32 ctratt; 220 __u8 rsvd100[28]; 221 __le16 crdt1; 222 __le16 crdt2; 223 __le16 crdt3; 224 __u8 rsvd134[122]; 225 __le16 oacs; 226 __u8 acl; 227 __u8 aerl; 228 __u8 frmw; 229 __u8 lpa; 230 __u8 elpe; 231 __u8 npss; 232 __u8 avscc; 233 __u8 apsta; 234 __le16 wctemp; 235 __le16 cctemp; 236 __le16 mtfa; 237 __le32 hmpre; 238 __le32 hmmin; 239 __u8 tnvmcap[16]; 240 __u8 unvmcap[16]; 241 __le32 rpmbs; 242 __le16 edstt; 243 __u8 dsto; 244 __u8 fwug; 245 __le16 kas; 246 __le16 hctma; 247 __le16 mntmt; 248 __le16 mxtmt; 249 __le32 sanicap; 250 __le32 hmminds; 251 __le16 hmmaxd; 252 __u8 rsvd338[4]; 253 __u8 anatt; 254 __u8 anacap; 255 __le32 anagrpmax; 256 __le32 nanagrpid; 257 __u8 rsvd352[160]; 258 __u8 sqes; 259 __u8 cqes; 260 __le16 maxcmd; 261 __le32 nn; 262 __le16 oncs; 263 __le16 fuses; 264 __u8 fna; 265 __u8 vwc; 266 __le16 awun; 267 __le16 awupf; 268 __u8 nvscc; 269 __u8 nwpc; 270 __le16 acwu; 271 __u8 rsvd534[2]; 272 __le32 sgls; 273 __le32 mnan; 274 __u8 rsvd544[224]; 275 char subnqn[256]; 276 __u8 rsvd1024[768]; 277 __le32 ioccsz; 278 __le32 iorcsz; 279 __le16 icdoff; 280 __u8 ctrattr; 281 __u8 msdbd; 282 __u8 rsvd1804[244]; 283 struct nvme_id_power_state psd[32]; 284 __u8 vs[1024]; 285 }; 286 287 enum { 288 NVME_CTRL_ONCS_COMPARE = 1 << 0, 289 NVME_CTRL_ONCS_WRITE_UNCORRECTABLE = 1 << 1, 290 NVME_CTRL_ONCS_DSM = 1 << 2, 291 NVME_CTRL_ONCS_WRITE_ZEROES = 1 << 3, 292 NVME_CTRL_ONCS_TIMESTAMP = 1 << 6, 293 NVME_CTRL_VWC_PRESENT = 1 << 0, 294 NVME_CTRL_OACS_SEC_SUPP = 1 << 0, 295 NVME_CTRL_OACS_DIRECTIVES = 1 << 5, 296 NVME_CTRL_OACS_DBBUF_SUPP = 1 << 8, 297 NVME_CTRL_LPA_CMD_EFFECTS_LOG = 1 << 1, 298 }; 299 300 struct nvme_lbaf { 301 __le16 ms; 302 __u8 ds; 303 __u8 rp; 304 }; 305 306 struct nvme_id_ns { 307 __le64 nsze; 308 __le64 ncap; 309 __le64 nuse; 310 __u8 nsfeat; 311 __u8 nlbaf; 312 __u8 flbas; 313 __u8 mc; 314 __u8 dpc; 315 __u8 dps; 316 __u8 nmic; 317 __u8 rescap; 318 __u8 fpi; 319 __u8 dlfeat; 320 __le16 nawun; 321 __le16 nawupf; 322 __le16 nacwu; 323 __le16 nabsn; 324 __le16 nabo; 325 __le16 nabspf; 326 __le16 noiob; 327 __u8 nvmcap[16]; 328 __le16 npwg; 329 __le16 npwa; 330 __le16 npdg; 331 __le16 npda; 332 __le16 nows; 333 __u8 rsvd74[18]; 334 __le32 anagrpid; 335 __u8 rsvd96[3]; 336 __u8 nsattr; 337 __le16 nvmsetid; 338 __le16 endgid; 339 __u8 nguid[16]; 340 __u8 eui64[8]; 341 struct nvme_lbaf lbaf[16]; 342 __u8 rsvd192[192]; 343 __u8 vs[3712]; 344 }; 345 346 enum { 347 NVME_ID_CNS_NS = 0x00, 348 NVME_ID_CNS_CTRL = 0x01, 349 NVME_ID_CNS_NS_ACTIVE_LIST = 0x02, 350 NVME_ID_CNS_NS_DESC_LIST = 0x03, 351 NVME_ID_CNS_NS_PRESENT_LIST = 0x10, 352 NVME_ID_CNS_NS_PRESENT = 0x11, 353 NVME_ID_CNS_CTRL_NS_LIST = 0x12, 354 NVME_ID_CNS_CTRL_LIST = 0x13, 355 }; 356 357 enum { 358 NVME_DIR_IDENTIFY = 0x00, 359 NVME_DIR_STREAMS = 0x01, 360 NVME_DIR_SND_ID_OP_ENABLE = 0x01, 361 NVME_DIR_SND_ST_OP_REL_ID = 0x01, 362 NVME_DIR_SND_ST_OP_REL_RSC = 0x02, 363 NVME_DIR_RCV_ID_OP_PARAM = 0x01, 364 NVME_DIR_RCV_ST_OP_PARAM = 0x01, 365 NVME_DIR_RCV_ST_OP_STATUS = 0x02, 366 NVME_DIR_RCV_ST_OP_RESOURCE = 0x03, 367 NVME_DIR_ENDIR = 0x01, 368 }; 369 370 enum { 371 NVME_NS_FEAT_THIN = 1 << 0, 372 NVME_NS_FLBAS_LBA_MASK = 0xf, 373 NVME_NS_FLBAS_META_EXT = 0x10, 374 NVME_LBAF_RP_BEST = 0, 375 NVME_LBAF_RP_BETTER = 1, 376 NVME_LBAF_RP_GOOD = 2, 377 NVME_LBAF_RP_DEGRADED = 3, 378 NVME_NS_DPC_PI_LAST = 1 << 4, 379 NVME_NS_DPC_PI_FIRST = 1 << 3, 380 NVME_NS_DPC_PI_TYPE3 = 1 << 2, 381 NVME_NS_DPC_PI_TYPE2 = 1 << 1, 382 NVME_NS_DPC_PI_TYPE1 = 1 << 0, 383 NVME_NS_DPS_PI_FIRST = 1 << 3, 384 NVME_NS_DPS_PI_MASK = 0x7, 385 NVME_NS_DPS_PI_TYPE1 = 1, 386 NVME_NS_DPS_PI_TYPE2 = 2, 387 NVME_NS_DPS_PI_TYPE3 = 3, 388 }; 389 390 struct nvme_ns_id_desc { 391 __u8 nidt; 392 __u8 nidl; 393 __le16 reserved; 394 }; 395 396 #define NVME_NIDT_EUI64_LEN 8 397 #define NVME_NIDT_NGUID_LEN 16 398 #define NVME_NIDT_UUID_LEN 16 399 400 enum { 401 NVME_NIDT_EUI64 = 0x01, 402 NVME_NIDT_NGUID = 0x02, 403 NVME_NIDT_UUID = 0x03, 404 }; 405 406 struct nvme_smart_log { 407 __u8 critical_warning; 408 __u8 temperature[2]; 409 __u8 avail_spare; 410 __u8 spare_thresh; 411 __u8 percent_used; 412 __u8 rsvd6[26]; 413 __u8 data_units_read[16]; 414 __u8 data_units_written[16]; 415 __u8 host_reads[16]; 416 __u8 host_writes[16]; 417 __u8 ctrl_busy_time[16]; 418 __u8 power_cycles[16]; 419 __u8 power_on_hours[16]; 420 __u8 unsafe_shutdowns[16]; 421 __u8 media_errors[16]; 422 __u8 num_err_log_entries[16]; 423 __le32 warning_temp_time; 424 __le32 critical_comp_time; 425 __le16 temp_sensor[8]; 426 __u8 rsvd216[296]; 427 }; 428 429 struct nvme_fw_slot_info_log { 430 __u8 afi; 431 __u8 rsvd1[7]; 432 __le64 frs[7]; 433 __u8 rsvd64[448]; 434 }; 435 436 enum { 437 NVME_CMD_EFFECTS_CSUPP = 1 << 0, 438 NVME_CMD_EFFECTS_LBCC = 1 << 1, 439 NVME_CMD_EFFECTS_NCC = 1 << 2, 440 NVME_CMD_EFFECTS_NIC = 1 << 3, 441 NVME_CMD_EFFECTS_CCC = 1 << 4, 442 NVME_CMD_EFFECTS_CSE_MASK = 3 << 16, 443 }; 444 445 struct nvme_effects_log { 446 __le32 acs[256]; 447 __le32 iocs[256]; 448 __u8 resv[2048]; 449 }; 450 451 enum nvme_ana_state { 452 NVME_ANA_OPTIMIZED = 0x01, 453 NVME_ANA_NONOPTIMIZED = 0x02, 454 NVME_ANA_INACCESSIBLE = 0x03, 455 NVME_ANA_PERSISTENT_LOSS = 0x04, 456 NVME_ANA_CHANGE = 0x0f, 457 }; 458 459 struct nvme_ana_group_desc { 460 __le32 grpid; 461 __le32 nnsids; 462 __le64 chgcnt; 463 __u8 state; 464 __u8 rsvd17[15]; 465 __le32 nsids[]; 466 }; 467 468 /* flag for the log specific field of the ANA log */ 469 #define NVME_ANA_LOG_RGO (1 << 0) 470 471 struct nvme_ana_rsp_hdr { 472 __le64 chgcnt; 473 __le16 ngrps; 474 __le16 rsvd10[3]; 475 }; 476 477 enum { 478 NVME_SMART_CRIT_SPARE = 1 << 0, 479 NVME_SMART_CRIT_TEMPERATURE = 1 << 1, 480 NVME_SMART_CRIT_RELIABILITY = 1 << 2, 481 NVME_SMART_CRIT_MEDIA = 1 << 3, 482 NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4, 483 }; 484 485 enum { 486 NVME_AER_ERROR = 0, 487 NVME_AER_SMART = 1, 488 NVME_AER_NOTICE = 2, 489 NVME_AER_CSS = 6, 490 NVME_AER_VS = 7, 491 }; 492 493 enum { 494 NVME_AER_NOTICE_NS_CHANGED = 0x00, 495 NVME_AER_NOTICE_FW_ACT_STARTING = 0x01, 496 NVME_AER_NOTICE_ANA = 0x03, 497 NVME_AER_NOTICE_DISC_CHANGED = 0xf0, 498 }; 499 500 enum { 501 NVME_AEN_BIT_NS_ATTR = 8, 502 NVME_AEN_BIT_FW_ACT = 9, 503 NVME_AEN_BIT_ANA_CHANGE = 11, 504 NVME_AEN_BIT_DISC_CHANGE = 31, 505 }; 506 507 enum { 508 NVME_AEN_CFG_NS_ATTR = 1 << NVME_AEN_BIT_NS_ATTR, 509 NVME_AEN_CFG_FW_ACT = 1 << NVME_AEN_BIT_FW_ACT, 510 NVME_AEN_CFG_ANA_CHANGE = 1 << NVME_AEN_BIT_ANA_CHANGE, 511 NVME_AEN_CFG_DISC_CHANGE = 1 << NVME_AEN_BIT_DISC_CHANGE, 512 }; 513 514 struct nvme_lba_range_type { 515 __u8 type; 516 __u8 attributes; 517 __u8 rsvd2[14]; 518 __u64 slba; 519 __u64 nlb; 520 __u8 guid[16]; 521 __u8 rsvd48[16]; 522 }; 523 524 enum { 525 NVME_LBART_TYPE_FS = 0x01, 526 NVME_LBART_TYPE_RAID = 0x02, 527 NVME_LBART_TYPE_CACHE = 0x03, 528 NVME_LBART_TYPE_SWAP = 0x04, 529 530 NVME_LBART_ATTRIB_TEMP = 1 << 0, 531 NVME_LBART_ATTRIB_HIDE = 1 << 1, 532 }; 533 534 struct nvme_reservation_status { 535 __le32 gen; 536 __u8 rtype; 537 __u8 regctl[2]; 538 __u8 resv5[2]; 539 __u8 ptpls; 540 __u8 resv10[13]; 541 struct { 542 __le16 cntlid; 543 __u8 rcsts; 544 __u8 resv3[5]; 545 __le64 hostid; 546 __le64 rkey; 547 } regctl_ds[]; 548 }; 549 550 enum nvme_async_event_type { 551 NVME_AER_TYPE_ERROR = 0, 552 NVME_AER_TYPE_SMART = 1, 553 NVME_AER_TYPE_NOTICE = 2, 554 }; 555 556 /* I/O commands */ 557 558 enum nvme_opcode { 559 nvme_cmd_flush = 0x00, 560 nvme_cmd_write = 0x01, 561 nvme_cmd_read = 0x02, 562 nvme_cmd_write_uncor = 0x04, 563 nvme_cmd_compare = 0x05, 564 nvme_cmd_write_zeroes = 0x08, 565 nvme_cmd_dsm = 0x09, 566 nvme_cmd_resv_register = 0x0d, 567 nvme_cmd_resv_report = 0x0e, 568 nvme_cmd_resv_acquire = 0x11, 569 nvme_cmd_resv_release = 0x15, 570 }; 571 572 #define nvme_opcode_name(opcode) { opcode, #opcode } 573 #define show_nvm_opcode_name(val) \ 574 __print_symbolic(val, \ 575 nvme_opcode_name(nvme_cmd_flush), \ 576 nvme_opcode_name(nvme_cmd_write), \ 577 nvme_opcode_name(nvme_cmd_read), \ 578 nvme_opcode_name(nvme_cmd_write_uncor), \ 579 nvme_opcode_name(nvme_cmd_compare), \ 580 nvme_opcode_name(nvme_cmd_write_zeroes), \ 581 nvme_opcode_name(nvme_cmd_dsm), \ 582 nvme_opcode_name(nvme_cmd_resv_register), \ 583 nvme_opcode_name(nvme_cmd_resv_report), \ 584 nvme_opcode_name(nvme_cmd_resv_acquire), \ 585 nvme_opcode_name(nvme_cmd_resv_release)) 586 587 588 /* 589 * Descriptor subtype - lower 4 bits of nvme_(keyed_)sgl_desc identifier 590 * 591 * @NVME_SGL_FMT_ADDRESS: absolute address of the data block 592 * @NVME_SGL_FMT_OFFSET: relative offset of the in-capsule data block 593 * @NVME_SGL_FMT_TRANSPORT_A: transport defined format, value 0xA 594 * @NVME_SGL_FMT_INVALIDATE: RDMA transport specific remote invalidation 595 * request subtype 596 */ 597 enum { 598 NVME_SGL_FMT_ADDRESS = 0x00, 599 NVME_SGL_FMT_OFFSET = 0x01, 600 NVME_SGL_FMT_TRANSPORT_A = 0x0A, 601 NVME_SGL_FMT_INVALIDATE = 0x0f, 602 }; 603 604 /* 605 * Descriptor type - upper 4 bits of nvme_(keyed_)sgl_desc identifier 606 * 607 * For struct nvme_sgl_desc: 608 * @NVME_SGL_FMT_DATA_DESC: data block descriptor 609 * @NVME_SGL_FMT_SEG_DESC: sgl segment descriptor 610 * @NVME_SGL_FMT_LAST_SEG_DESC: last sgl segment descriptor 611 * 612 * For struct nvme_keyed_sgl_desc: 613 * @NVME_KEY_SGL_FMT_DATA_DESC: keyed data block descriptor 614 * 615 * Transport-specific SGL types: 616 * @NVME_TRANSPORT_SGL_DATA_DESC: Transport SGL data dlock descriptor 617 */ 618 enum { 619 NVME_SGL_FMT_DATA_DESC = 0x00, 620 NVME_SGL_FMT_SEG_DESC = 0x02, 621 NVME_SGL_FMT_LAST_SEG_DESC = 0x03, 622 NVME_KEY_SGL_FMT_DATA_DESC = 0x04, 623 NVME_TRANSPORT_SGL_DATA_DESC = 0x05, 624 }; 625 626 struct nvme_sgl_desc { 627 __le64 addr; 628 __le32 length; 629 __u8 rsvd[3]; 630 __u8 type; 631 }; 632 633 struct nvme_keyed_sgl_desc { 634 __le64 addr; 635 __u8 length[3]; 636 __u8 key[4]; 637 __u8 type; 638 }; 639 640 union nvme_data_ptr { 641 struct { 642 __le64 prp1; 643 __le64 prp2; 644 }; 645 struct nvme_sgl_desc sgl; 646 struct nvme_keyed_sgl_desc ksgl; 647 }; 648 649 /* 650 * Lowest two bits of our flags field (FUSE field in the spec): 651 * 652 * @NVME_CMD_FUSE_FIRST: Fused Operation, first command 653 * @NVME_CMD_FUSE_SECOND: Fused Operation, second command 654 * 655 * Highest two bits in our flags field (PSDT field in the spec): 656 * 657 * @NVME_CMD_PSDT_SGL_METABUF: Use SGLS for this transfer, 658 * If used, MPTR contains addr of single physical buffer (byte aligned). 659 * @NVME_CMD_PSDT_SGL_METASEG: Use SGLS for this transfer, 660 * If used, MPTR contains an address of an SGL segment containing 661 * exactly 1 SGL descriptor (qword aligned). 662 */ 663 enum { 664 NVME_CMD_FUSE_FIRST = (1 << 0), 665 NVME_CMD_FUSE_SECOND = (1 << 1), 666 667 NVME_CMD_SGL_METABUF = (1 << 6), 668 NVME_CMD_SGL_METASEG = (1 << 7), 669 NVME_CMD_SGL_ALL = NVME_CMD_SGL_METABUF | NVME_CMD_SGL_METASEG, 670 }; 671 672 struct nvme_common_command { 673 __u8 opcode; 674 __u8 flags; 675 __u16 command_id; 676 __le32 nsid; 677 __le32 cdw2[2]; 678 __le64 metadata; 679 union nvme_data_ptr dptr; 680 __le32 cdw10; 681 __le32 cdw11; 682 __le32 cdw12; 683 __le32 cdw13; 684 __le32 cdw14; 685 __le32 cdw15; 686 }; 687 688 struct nvme_rw_command { 689 __u8 opcode; 690 __u8 flags; 691 __u16 command_id; 692 __le32 nsid; 693 __u64 rsvd2; 694 __le64 metadata; 695 union nvme_data_ptr dptr; 696 __le64 slba; 697 __le16 length; 698 __le16 control; 699 __le32 dsmgmt; 700 __le32 reftag; 701 __le16 apptag; 702 __le16 appmask; 703 }; 704 705 enum { 706 NVME_RW_LR = 1 << 15, 707 NVME_RW_FUA = 1 << 14, 708 NVME_RW_DSM_FREQ_UNSPEC = 0, 709 NVME_RW_DSM_FREQ_TYPICAL = 1, 710 NVME_RW_DSM_FREQ_RARE = 2, 711 NVME_RW_DSM_FREQ_READS = 3, 712 NVME_RW_DSM_FREQ_WRITES = 4, 713 NVME_RW_DSM_FREQ_RW = 5, 714 NVME_RW_DSM_FREQ_ONCE = 6, 715 NVME_RW_DSM_FREQ_PREFETCH = 7, 716 NVME_RW_DSM_FREQ_TEMP = 8, 717 NVME_RW_DSM_LATENCY_NONE = 0 << 4, 718 NVME_RW_DSM_LATENCY_IDLE = 1 << 4, 719 NVME_RW_DSM_LATENCY_NORM = 2 << 4, 720 NVME_RW_DSM_LATENCY_LOW = 3 << 4, 721 NVME_RW_DSM_SEQ_REQ = 1 << 6, 722 NVME_RW_DSM_COMPRESSED = 1 << 7, 723 NVME_RW_PRINFO_PRCHK_REF = 1 << 10, 724 NVME_RW_PRINFO_PRCHK_APP = 1 << 11, 725 NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12, 726 NVME_RW_PRINFO_PRACT = 1 << 13, 727 NVME_RW_DTYPE_STREAMS = 1 << 4, 728 }; 729 730 struct nvme_dsm_cmd { 731 __u8 opcode; 732 __u8 flags; 733 __u16 command_id; 734 __le32 nsid; 735 __u64 rsvd2[2]; 736 union nvme_data_ptr dptr; 737 __le32 nr; 738 __le32 attributes; 739 __u32 rsvd12[4]; 740 }; 741 742 enum { 743 NVME_DSMGMT_IDR = 1 << 0, 744 NVME_DSMGMT_IDW = 1 << 1, 745 NVME_DSMGMT_AD = 1 << 2, 746 }; 747 748 #define NVME_DSM_MAX_RANGES 256 749 750 struct nvme_dsm_range { 751 __le32 cattr; 752 __le32 nlb; 753 __le64 slba; 754 }; 755 756 struct nvme_write_zeroes_cmd { 757 __u8 opcode; 758 __u8 flags; 759 __u16 command_id; 760 __le32 nsid; 761 __u64 rsvd2; 762 __le64 metadata; 763 union nvme_data_ptr dptr; 764 __le64 slba; 765 __le16 length; 766 __le16 control; 767 __le32 dsmgmt; 768 __le32 reftag; 769 __le16 apptag; 770 __le16 appmask; 771 }; 772 773 /* Features */ 774 775 struct nvme_feat_auto_pst { 776 __le64 entries[32]; 777 }; 778 779 enum { 780 NVME_HOST_MEM_ENABLE = (1 << 0), 781 NVME_HOST_MEM_RETURN = (1 << 1), 782 }; 783 784 struct nvme_feat_host_behavior { 785 __u8 acre; 786 __u8 resv1[511]; 787 }; 788 789 enum { 790 NVME_ENABLE_ACRE = 1, 791 }; 792 793 /* Admin commands */ 794 795 enum nvme_admin_opcode { 796 nvme_admin_delete_sq = 0x00, 797 nvme_admin_create_sq = 0x01, 798 nvme_admin_get_log_page = 0x02, 799 nvme_admin_delete_cq = 0x04, 800 nvme_admin_create_cq = 0x05, 801 nvme_admin_identify = 0x06, 802 nvme_admin_abort_cmd = 0x08, 803 nvme_admin_set_features = 0x09, 804 nvme_admin_get_features = 0x0a, 805 nvme_admin_async_event = 0x0c, 806 nvme_admin_ns_mgmt = 0x0d, 807 nvme_admin_activate_fw = 0x10, 808 nvme_admin_download_fw = 0x11, 809 nvme_admin_ns_attach = 0x15, 810 nvme_admin_keep_alive = 0x18, 811 nvme_admin_directive_send = 0x19, 812 nvme_admin_directive_recv = 0x1a, 813 nvme_admin_dbbuf = 0x7C, 814 nvme_admin_format_nvm = 0x80, 815 nvme_admin_security_send = 0x81, 816 nvme_admin_security_recv = 0x82, 817 nvme_admin_sanitize_nvm = 0x84, 818 nvme_admin_get_lba_status = 0x86, 819 }; 820 821 #define nvme_admin_opcode_name(opcode) { opcode, #opcode } 822 #define show_admin_opcode_name(val) \ 823 __print_symbolic(val, \ 824 nvme_admin_opcode_name(nvme_admin_delete_sq), \ 825 nvme_admin_opcode_name(nvme_admin_create_sq), \ 826 nvme_admin_opcode_name(nvme_admin_get_log_page), \ 827 nvme_admin_opcode_name(nvme_admin_delete_cq), \ 828 nvme_admin_opcode_name(nvme_admin_create_cq), \ 829 nvme_admin_opcode_name(nvme_admin_identify), \ 830 nvme_admin_opcode_name(nvme_admin_abort_cmd), \ 831 nvme_admin_opcode_name(nvme_admin_set_features), \ 832 nvme_admin_opcode_name(nvme_admin_get_features), \ 833 nvme_admin_opcode_name(nvme_admin_async_event), \ 834 nvme_admin_opcode_name(nvme_admin_ns_mgmt), \ 835 nvme_admin_opcode_name(nvme_admin_activate_fw), \ 836 nvme_admin_opcode_name(nvme_admin_download_fw), \ 837 nvme_admin_opcode_name(nvme_admin_ns_attach), \ 838 nvme_admin_opcode_name(nvme_admin_keep_alive), \ 839 nvme_admin_opcode_name(nvme_admin_directive_send), \ 840 nvme_admin_opcode_name(nvme_admin_directive_recv), \ 841 nvme_admin_opcode_name(nvme_admin_dbbuf), \ 842 nvme_admin_opcode_name(nvme_admin_format_nvm), \ 843 nvme_admin_opcode_name(nvme_admin_security_send), \ 844 nvme_admin_opcode_name(nvme_admin_security_recv), \ 845 nvme_admin_opcode_name(nvme_admin_sanitize_nvm), \ 846 nvme_admin_opcode_name(nvme_admin_get_lba_status)) 847 848 enum { 849 NVME_QUEUE_PHYS_CONTIG = (1 << 0), 850 NVME_CQ_IRQ_ENABLED = (1 << 1), 851 NVME_SQ_PRIO_URGENT = (0 << 1), 852 NVME_SQ_PRIO_HIGH = (1 << 1), 853 NVME_SQ_PRIO_MEDIUM = (2 << 1), 854 NVME_SQ_PRIO_LOW = (3 << 1), 855 NVME_FEAT_ARBITRATION = 0x01, 856 NVME_FEAT_POWER_MGMT = 0x02, 857 NVME_FEAT_LBA_RANGE = 0x03, 858 NVME_FEAT_TEMP_THRESH = 0x04, 859 NVME_FEAT_ERR_RECOVERY = 0x05, 860 NVME_FEAT_VOLATILE_WC = 0x06, 861 NVME_FEAT_NUM_QUEUES = 0x07, 862 NVME_FEAT_IRQ_COALESCE = 0x08, 863 NVME_FEAT_IRQ_CONFIG = 0x09, 864 NVME_FEAT_WRITE_ATOMIC = 0x0a, 865 NVME_FEAT_ASYNC_EVENT = 0x0b, 866 NVME_FEAT_AUTO_PST = 0x0c, 867 NVME_FEAT_HOST_MEM_BUF = 0x0d, 868 NVME_FEAT_TIMESTAMP = 0x0e, 869 NVME_FEAT_KATO = 0x0f, 870 NVME_FEAT_HCTM = 0x10, 871 NVME_FEAT_NOPSC = 0x11, 872 NVME_FEAT_RRL = 0x12, 873 NVME_FEAT_PLM_CONFIG = 0x13, 874 NVME_FEAT_PLM_WINDOW = 0x14, 875 NVME_FEAT_HOST_BEHAVIOR = 0x16, 876 NVME_FEAT_SW_PROGRESS = 0x80, 877 NVME_FEAT_HOST_ID = 0x81, 878 NVME_FEAT_RESV_MASK = 0x82, 879 NVME_FEAT_RESV_PERSIST = 0x83, 880 NVME_FEAT_WRITE_PROTECT = 0x84, 881 NVME_LOG_ERROR = 0x01, 882 NVME_LOG_SMART = 0x02, 883 NVME_LOG_FW_SLOT = 0x03, 884 NVME_LOG_CHANGED_NS = 0x04, 885 NVME_LOG_CMD_EFFECTS = 0x05, 886 NVME_LOG_ANA = 0x0c, 887 NVME_LOG_DISC = 0x70, 888 NVME_LOG_RESERVATION = 0x80, 889 NVME_FWACT_REPL = (0 << 3), 890 NVME_FWACT_REPL_ACTV = (1 << 3), 891 NVME_FWACT_ACTV = (2 << 3), 892 }; 893 894 /* NVMe Namespace Write Protect State */ 895 enum { 896 NVME_NS_NO_WRITE_PROTECT = 0, 897 NVME_NS_WRITE_PROTECT, 898 NVME_NS_WRITE_PROTECT_POWER_CYCLE, 899 NVME_NS_WRITE_PROTECT_PERMANENT, 900 }; 901 902 #define NVME_MAX_CHANGED_NAMESPACES 1024 903 904 struct nvme_identify { 905 __u8 opcode; 906 __u8 flags; 907 __u16 command_id; 908 __le32 nsid; 909 __u64 rsvd2[2]; 910 union nvme_data_ptr dptr; 911 __u8 cns; 912 __u8 rsvd3; 913 __le16 ctrlid; 914 __u32 rsvd11[5]; 915 }; 916 917 #define NVME_IDENTIFY_DATA_SIZE 4096 918 919 struct nvme_features { 920 __u8 opcode; 921 __u8 flags; 922 __u16 command_id; 923 __le32 nsid; 924 __u64 rsvd2[2]; 925 union nvme_data_ptr dptr; 926 __le32 fid; 927 __le32 dword11; 928 __le32 dword12; 929 __le32 dword13; 930 __le32 dword14; 931 __le32 dword15; 932 }; 933 934 struct nvme_host_mem_buf_desc { 935 __le64 addr; 936 __le32 size; 937 __u32 rsvd; 938 }; 939 940 struct nvme_create_cq { 941 __u8 opcode; 942 __u8 flags; 943 __u16 command_id; 944 __u32 rsvd1[5]; 945 __le64 prp1; 946 __u64 rsvd8; 947 __le16 cqid; 948 __le16 qsize; 949 __le16 cq_flags; 950 __le16 irq_vector; 951 __u32 rsvd12[4]; 952 }; 953 954 struct nvme_create_sq { 955 __u8 opcode; 956 __u8 flags; 957 __u16 command_id; 958 __u32 rsvd1[5]; 959 __le64 prp1; 960 __u64 rsvd8; 961 __le16 sqid; 962 __le16 qsize; 963 __le16 sq_flags; 964 __le16 cqid; 965 __u32 rsvd12[4]; 966 }; 967 968 struct nvme_delete_queue { 969 __u8 opcode; 970 __u8 flags; 971 __u16 command_id; 972 __u32 rsvd1[9]; 973 __le16 qid; 974 __u16 rsvd10; 975 __u32 rsvd11[5]; 976 }; 977 978 struct nvme_abort_cmd { 979 __u8 opcode; 980 __u8 flags; 981 __u16 command_id; 982 __u32 rsvd1[9]; 983 __le16 sqid; 984 __u16 cid; 985 __u32 rsvd11[5]; 986 }; 987 988 struct nvme_download_firmware { 989 __u8 opcode; 990 __u8 flags; 991 __u16 command_id; 992 __u32 rsvd1[5]; 993 union nvme_data_ptr dptr; 994 __le32 numd; 995 __le32 offset; 996 __u32 rsvd12[4]; 997 }; 998 999 struct nvme_format_cmd { 1000 __u8 opcode; 1001 __u8 flags; 1002 __u16 command_id; 1003 __le32 nsid; 1004 __u64 rsvd2[4]; 1005 __le32 cdw10; 1006 __u32 rsvd11[5]; 1007 }; 1008 1009 struct nvme_get_log_page_command { 1010 __u8 opcode; 1011 __u8 flags; 1012 __u16 command_id; 1013 __le32 nsid; 1014 __u64 rsvd2[2]; 1015 union nvme_data_ptr dptr; 1016 __u8 lid; 1017 __u8 lsp; /* upper 4 bits reserved */ 1018 __le16 numdl; 1019 __le16 numdu; 1020 __u16 rsvd11; 1021 union { 1022 struct { 1023 __le32 lpol; 1024 __le32 lpou; 1025 }; 1026 __le64 lpo; 1027 }; 1028 __u32 rsvd14[2]; 1029 }; 1030 1031 struct nvme_directive_cmd { 1032 __u8 opcode; 1033 __u8 flags; 1034 __u16 command_id; 1035 __le32 nsid; 1036 __u64 rsvd2[2]; 1037 union nvme_data_ptr dptr; 1038 __le32 numd; 1039 __u8 doper; 1040 __u8 dtype; 1041 __le16 dspec; 1042 __u8 endir; 1043 __u8 tdtype; 1044 __u16 rsvd15; 1045 1046 __u32 rsvd16[3]; 1047 }; 1048 1049 /* 1050 * Fabrics subcommands. 1051 */ 1052 enum nvmf_fabrics_opcode { 1053 nvme_fabrics_command = 0x7f, 1054 }; 1055 1056 enum nvmf_capsule_command { 1057 nvme_fabrics_type_property_set = 0x00, 1058 nvme_fabrics_type_connect = 0x01, 1059 nvme_fabrics_type_property_get = 0x04, 1060 }; 1061 1062 #define nvme_fabrics_type_name(type) { type, #type } 1063 #define show_fabrics_type_name(type) \ 1064 __print_symbolic(type, \ 1065 nvme_fabrics_type_name(nvme_fabrics_type_property_set), \ 1066 nvme_fabrics_type_name(nvme_fabrics_type_connect), \ 1067 nvme_fabrics_type_name(nvme_fabrics_type_property_get)) 1068 1069 /* 1070 * If not fabrics command, fctype will be ignored. 1071 */ 1072 #define show_opcode_name(qid, opcode, fctype) \ 1073 ((opcode) == nvme_fabrics_command ? \ 1074 show_fabrics_type_name(fctype) : \ 1075 ((qid) ? \ 1076 show_nvm_opcode_name(opcode) : \ 1077 show_admin_opcode_name(opcode))) 1078 1079 struct nvmf_common_command { 1080 __u8 opcode; 1081 __u8 resv1; 1082 __u16 command_id; 1083 __u8 fctype; 1084 __u8 resv2[35]; 1085 __u8 ts[24]; 1086 }; 1087 1088 /* 1089 * The legal cntlid range a NVMe Target will provide. 1090 * Note that cntlid of value 0 is considered illegal in the fabrics world. 1091 * Devices based on earlier specs did not have the subsystem concept; 1092 * therefore, those devices had their cntlid value set to 0 as a result. 1093 */ 1094 #define NVME_CNTLID_MIN 1 1095 #define NVME_CNTLID_MAX 0xffef 1096 #define NVME_CNTLID_DYNAMIC 0xffff 1097 1098 #define MAX_DISC_LOGS 255 1099 1100 /* Discovery log page entry */ 1101 struct nvmf_disc_rsp_page_entry { 1102 __u8 trtype; 1103 __u8 adrfam; 1104 __u8 subtype; 1105 __u8 treq; 1106 __le16 portid; 1107 __le16 cntlid; 1108 __le16 asqsz; 1109 __u8 resv8[22]; 1110 char trsvcid[NVMF_TRSVCID_SIZE]; 1111 __u8 resv64[192]; 1112 char subnqn[NVMF_NQN_FIELD_LEN]; 1113 char traddr[NVMF_TRADDR_SIZE]; 1114 union tsas { 1115 char common[NVMF_TSAS_SIZE]; 1116 struct rdma { 1117 __u8 qptype; 1118 __u8 prtype; 1119 __u8 cms; 1120 __u8 resv3[5]; 1121 __u16 pkey; 1122 __u8 resv10[246]; 1123 } rdma; 1124 } tsas; 1125 }; 1126 1127 /* Discovery log page header */ 1128 struct nvmf_disc_rsp_page_hdr { 1129 __le64 genctr; 1130 __le64 numrec; 1131 __le16 recfmt; 1132 __u8 resv14[1006]; 1133 struct nvmf_disc_rsp_page_entry entries[0]; 1134 }; 1135 1136 enum { 1137 NVME_CONNECT_DISABLE_SQFLOW = (1 << 2), 1138 }; 1139 1140 struct nvmf_connect_command { 1141 __u8 opcode; 1142 __u8 resv1; 1143 __u16 command_id; 1144 __u8 fctype; 1145 __u8 resv2[19]; 1146 union nvme_data_ptr dptr; 1147 __le16 recfmt; 1148 __le16 qid; 1149 __le16 sqsize; 1150 __u8 cattr; 1151 __u8 resv3; 1152 __le32 kato; 1153 __u8 resv4[12]; 1154 }; 1155 1156 struct nvmf_connect_data { 1157 uuid_t hostid; 1158 __le16 cntlid; 1159 char resv4[238]; 1160 char subsysnqn[NVMF_NQN_FIELD_LEN]; 1161 char hostnqn[NVMF_NQN_FIELD_LEN]; 1162 char resv5[256]; 1163 }; 1164 1165 struct nvmf_property_set_command { 1166 __u8 opcode; 1167 __u8 resv1; 1168 __u16 command_id; 1169 __u8 fctype; 1170 __u8 resv2[35]; 1171 __u8 attrib; 1172 __u8 resv3[3]; 1173 __le32 offset; 1174 __le64 value; 1175 __u8 resv4[8]; 1176 }; 1177 1178 struct nvmf_property_get_command { 1179 __u8 opcode; 1180 __u8 resv1; 1181 __u16 command_id; 1182 __u8 fctype; 1183 __u8 resv2[35]; 1184 __u8 attrib; 1185 __u8 resv3[3]; 1186 __le32 offset; 1187 __u8 resv4[16]; 1188 }; 1189 1190 struct nvme_dbbuf { 1191 __u8 opcode; 1192 __u8 flags; 1193 __u16 command_id; 1194 __u32 rsvd1[5]; 1195 __le64 prp1; 1196 __le64 prp2; 1197 __u32 rsvd12[6]; 1198 }; 1199 1200 struct streams_directive_params { 1201 __le16 msl; 1202 __le16 nssa; 1203 __le16 nsso; 1204 __u8 rsvd[10]; 1205 __le32 sws; 1206 __le16 sgs; 1207 __le16 nsa; 1208 __le16 nso; 1209 __u8 rsvd2[6]; 1210 }; 1211 1212 struct nvme_command { 1213 union { 1214 struct nvme_common_command common; 1215 struct nvme_rw_command rw; 1216 struct nvme_identify identify; 1217 struct nvme_features features; 1218 struct nvme_create_cq create_cq; 1219 struct nvme_create_sq create_sq; 1220 struct nvme_delete_queue delete_queue; 1221 struct nvme_download_firmware dlfw; 1222 struct nvme_format_cmd format; 1223 struct nvme_dsm_cmd dsm; 1224 struct nvme_write_zeroes_cmd write_zeroes; 1225 struct nvme_abort_cmd abort; 1226 struct nvme_get_log_page_command get_log_page; 1227 struct nvmf_common_command fabrics; 1228 struct nvmf_connect_command connect; 1229 struct nvmf_property_set_command prop_set; 1230 struct nvmf_property_get_command prop_get; 1231 struct nvme_dbbuf dbbuf; 1232 struct nvme_directive_cmd directive; 1233 }; 1234 }; 1235 1236 static inline bool nvme_is_fabrics(struct nvme_command *cmd) 1237 { 1238 return cmd->common.opcode == nvme_fabrics_command; 1239 } 1240 1241 struct nvme_error_slot { 1242 __le64 error_count; 1243 __le16 sqid; 1244 __le16 cmdid; 1245 __le16 status_field; 1246 __le16 param_error_location; 1247 __le64 lba; 1248 __le32 nsid; 1249 __u8 vs; 1250 __u8 resv[3]; 1251 __le64 cs; 1252 __u8 resv2[24]; 1253 }; 1254 1255 static inline bool nvme_is_write(struct nvme_command *cmd) 1256 { 1257 /* 1258 * What a mess... 1259 * 1260 * Why can't we simply have a Fabrics In and Fabrics out command? 1261 */ 1262 if (unlikely(nvme_is_fabrics(cmd))) 1263 return cmd->fabrics.fctype & 1; 1264 return cmd->common.opcode & 1; 1265 } 1266 1267 enum { 1268 /* 1269 * Generic Command Status: 1270 */ 1271 NVME_SC_SUCCESS = 0x0, 1272 NVME_SC_INVALID_OPCODE = 0x1, 1273 NVME_SC_INVALID_FIELD = 0x2, 1274 NVME_SC_CMDID_CONFLICT = 0x3, 1275 NVME_SC_DATA_XFER_ERROR = 0x4, 1276 NVME_SC_POWER_LOSS = 0x5, 1277 NVME_SC_INTERNAL = 0x6, 1278 NVME_SC_ABORT_REQ = 0x7, 1279 NVME_SC_ABORT_QUEUE = 0x8, 1280 NVME_SC_FUSED_FAIL = 0x9, 1281 NVME_SC_FUSED_MISSING = 0xa, 1282 NVME_SC_INVALID_NS = 0xb, 1283 NVME_SC_CMD_SEQ_ERROR = 0xc, 1284 NVME_SC_SGL_INVALID_LAST = 0xd, 1285 NVME_SC_SGL_INVALID_COUNT = 0xe, 1286 NVME_SC_SGL_INVALID_DATA = 0xf, 1287 NVME_SC_SGL_INVALID_METADATA = 0x10, 1288 NVME_SC_SGL_INVALID_TYPE = 0x11, 1289 1290 NVME_SC_SGL_INVALID_OFFSET = 0x16, 1291 NVME_SC_SGL_INVALID_SUBTYPE = 0x17, 1292 1293 NVME_SC_NS_WRITE_PROTECTED = 0x20, 1294 1295 NVME_SC_LBA_RANGE = 0x80, 1296 NVME_SC_CAP_EXCEEDED = 0x81, 1297 NVME_SC_NS_NOT_READY = 0x82, 1298 NVME_SC_RESERVATION_CONFLICT = 0x83, 1299 1300 /* 1301 * Command Specific Status: 1302 */ 1303 NVME_SC_CQ_INVALID = 0x100, 1304 NVME_SC_QID_INVALID = 0x101, 1305 NVME_SC_QUEUE_SIZE = 0x102, 1306 NVME_SC_ABORT_LIMIT = 0x103, 1307 NVME_SC_ABORT_MISSING = 0x104, 1308 NVME_SC_ASYNC_LIMIT = 0x105, 1309 NVME_SC_FIRMWARE_SLOT = 0x106, 1310 NVME_SC_FIRMWARE_IMAGE = 0x107, 1311 NVME_SC_INVALID_VECTOR = 0x108, 1312 NVME_SC_INVALID_LOG_PAGE = 0x109, 1313 NVME_SC_INVALID_FORMAT = 0x10a, 1314 NVME_SC_FW_NEEDS_CONV_RESET = 0x10b, 1315 NVME_SC_INVALID_QUEUE = 0x10c, 1316 NVME_SC_FEATURE_NOT_SAVEABLE = 0x10d, 1317 NVME_SC_FEATURE_NOT_CHANGEABLE = 0x10e, 1318 NVME_SC_FEATURE_NOT_PER_NS = 0x10f, 1319 NVME_SC_FW_NEEDS_SUBSYS_RESET = 0x110, 1320 NVME_SC_FW_NEEDS_RESET = 0x111, 1321 NVME_SC_FW_NEEDS_MAX_TIME = 0x112, 1322 NVME_SC_FW_ACTIVATE_PROHIBITED = 0x113, 1323 NVME_SC_OVERLAPPING_RANGE = 0x114, 1324 NVME_SC_NS_INSUFFICIENT_CAP = 0x115, 1325 NVME_SC_NS_ID_UNAVAILABLE = 0x116, 1326 NVME_SC_NS_ALREADY_ATTACHED = 0x118, 1327 NVME_SC_NS_IS_PRIVATE = 0x119, 1328 NVME_SC_NS_NOT_ATTACHED = 0x11a, 1329 NVME_SC_THIN_PROV_NOT_SUPP = 0x11b, 1330 NVME_SC_CTRL_LIST_INVALID = 0x11c, 1331 1332 /* 1333 * I/O Command Set Specific - NVM commands: 1334 */ 1335 NVME_SC_BAD_ATTRIBUTES = 0x180, 1336 NVME_SC_INVALID_PI = 0x181, 1337 NVME_SC_READ_ONLY = 0x182, 1338 NVME_SC_ONCS_NOT_SUPPORTED = 0x183, 1339 1340 /* 1341 * I/O Command Set Specific - Fabrics commands: 1342 */ 1343 NVME_SC_CONNECT_FORMAT = 0x180, 1344 NVME_SC_CONNECT_CTRL_BUSY = 0x181, 1345 NVME_SC_CONNECT_INVALID_PARAM = 0x182, 1346 NVME_SC_CONNECT_RESTART_DISC = 0x183, 1347 NVME_SC_CONNECT_INVALID_HOST = 0x184, 1348 1349 NVME_SC_DISCOVERY_RESTART = 0x190, 1350 NVME_SC_AUTH_REQUIRED = 0x191, 1351 1352 /* 1353 * Media and Data Integrity Errors: 1354 */ 1355 NVME_SC_WRITE_FAULT = 0x280, 1356 NVME_SC_READ_ERROR = 0x281, 1357 NVME_SC_GUARD_CHECK = 0x282, 1358 NVME_SC_APPTAG_CHECK = 0x283, 1359 NVME_SC_REFTAG_CHECK = 0x284, 1360 NVME_SC_COMPARE_FAILED = 0x285, 1361 NVME_SC_ACCESS_DENIED = 0x286, 1362 NVME_SC_UNWRITTEN_BLOCK = 0x287, 1363 1364 /* 1365 * Path-related Errors: 1366 */ 1367 NVME_SC_ANA_PERSISTENT_LOSS = 0x301, 1368 NVME_SC_ANA_INACCESSIBLE = 0x302, 1369 NVME_SC_ANA_TRANSITION = 0x303, 1370 NVME_SC_HOST_PATH_ERROR = 0x370, 1371 1372 NVME_SC_CRD = 0x1800, 1373 NVME_SC_DNR = 0x4000, 1374 }; 1375 1376 struct nvme_completion { 1377 /* 1378 * Used by Admin and Fabrics commands to return data: 1379 */ 1380 union nvme_result { 1381 __le16 u16; 1382 __le32 u32; 1383 __le64 u64; 1384 } result; 1385 __le16 sq_head; /* how much of this queue may be reclaimed */ 1386 __le16 sq_id; /* submission queue that generated this entry */ 1387 __u16 command_id; /* of the command which completed */ 1388 __le16 status; /* did the command fail, and if so, why? */ 1389 }; 1390 1391 #define NVME_VS(major, minor, tertiary) \ 1392 (((major) << 16) | ((minor) << 8) | (tertiary)) 1393 1394 #define NVME_MAJOR(ver) ((ver) >> 16) 1395 #define NVME_MINOR(ver) (((ver) >> 8) & 0xff) 1396 #define NVME_TERTIARY(ver) ((ver) & 0xff) 1397 1398 #endif /* _LINUX_NVME_H */ 1399