17bedaa55SRussell King #ifndef __LINUX_OMAP_DMA_H 27bedaa55SRussell King #define __LINUX_OMAP_DMA_H 3ee526d51SBalaji T K #include <linux/omap-dmaengine.h> 47bedaa55SRussell King 545c3eb7dSTony Lindgren /* 645c3eb7dSTony Lindgren * Legacy OMAP DMA handling defines and functions 745c3eb7dSTony Lindgren * 845c3eb7dSTony Lindgren * NOTE: Do not use these any longer. 945c3eb7dSTony Lindgren * 1045c3eb7dSTony Lindgren * Use the generic dmaengine functions as defined in 1145c3eb7dSTony Lindgren * include/linux/dmaengine.h. 1245c3eb7dSTony Lindgren * 1345c3eb7dSTony Lindgren * Copyright (C) 2003 Nokia Corporation 1445c3eb7dSTony Lindgren * Author: Juha Yrjölä <juha.yrjola@nokia.com> 1545c3eb7dSTony Lindgren * 1645c3eb7dSTony Lindgren */ 1745c3eb7dSTony Lindgren 1845c3eb7dSTony Lindgren #include <linux/platform_device.h> 1945c3eb7dSTony Lindgren 20*1bd5dfe4SAaro Koskinen #define INT_DMA_LCD (NR_IRQS_LEGACY + 25) 2145c3eb7dSTony Lindgren 2245c3eb7dSTony Lindgren #define OMAP1_DMA_TOUT_IRQ (1 << 0) 2345c3eb7dSTony Lindgren #define OMAP_DMA_DROP_IRQ (1 << 1) 2445c3eb7dSTony Lindgren #define OMAP_DMA_HALF_IRQ (1 << 2) 2545c3eb7dSTony Lindgren #define OMAP_DMA_FRAME_IRQ (1 << 3) 2645c3eb7dSTony Lindgren #define OMAP_DMA_LAST_IRQ (1 << 4) 2745c3eb7dSTony Lindgren #define OMAP_DMA_BLOCK_IRQ (1 << 5) 2845c3eb7dSTony Lindgren #define OMAP1_DMA_SYNC_IRQ (1 << 6) 2945c3eb7dSTony Lindgren #define OMAP2_DMA_PKT_IRQ (1 << 7) 3045c3eb7dSTony Lindgren #define OMAP2_DMA_TRANS_ERR_IRQ (1 << 8) 3145c3eb7dSTony Lindgren #define OMAP2_DMA_SECURE_ERR_IRQ (1 << 9) 3245c3eb7dSTony Lindgren #define OMAP2_DMA_SUPERVISOR_ERR_IRQ (1 << 10) 3345c3eb7dSTony Lindgren #define OMAP2_DMA_MISALIGNED_ERR_IRQ (1 << 11) 3445c3eb7dSTony Lindgren 3545c3eb7dSTony Lindgren #define OMAP_DMA_CCR_EN (1 << 7) 3645c3eb7dSTony Lindgren #define OMAP_DMA_CCR_RD_ACTIVE (1 << 9) 3745c3eb7dSTony Lindgren #define OMAP_DMA_CCR_WR_ACTIVE (1 << 10) 3845c3eb7dSTony Lindgren #define OMAP_DMA_CCR_SEL_SRC_DST_SYNC (1 << 24) 3945c3eb7dSTony Lindgren #define OMAP_DMA_CCR_BUFFERING_DISABLE (1 << 25) 4045c3eb7dSTony Lindgren 4145c3eb7dSTony Lindgren #define OMAP_DMA_DATA_TYPE_S8 0x00 4245c3eb7dSTony Lindgren #define OMAP_DMA_DATA_TYPE_S16 0x01 4345c3eb7dSTony Lindgren #define OMAP_DMA_DATA_TYPE_S32 0x02 4445c3eb7dSTony Lindgren 4545c3eb7dSTony Lindgren #define OMAP_DMA_SYNC_ELEMENT 0x00 4645c3eb7dSTony Lindgren #define OMAP_DMA_SYNC_FRAME 0x01 4745c3eb7dSTony Lindgren #define OMAP_DMA_SYNC_BLOCK 0x02 4845c3eb7dSTony Lindgren #define OMAP_DMA_SYNC_PACKET 0x03 4945c3eb7dSTony Lindgren 5045c3eb7dSTony Lindgren #define OMAP_DMA_DST_SYNC_PREFETCH 0x02 5145c3eb7dSTony Lindgren #define OMAP_DMA_SRC_SYNC 0x01 5245c3eb7dSTony Lindgren #define OMAP_DMA_DST_SYNC 0x00 5345c3eb7dSTony Lindgren 5445c3eb7dSTony Lindgren #define OMAP_DMA_PORT_EMIFF 0x00 5545c3eb7dSTony Lindgren #define OMAP_DMA_PORT_EMIFS 0x01 5645c3eb7dSTony Lindgren #define OMAP_DMA_PORT_OCP_T1 0x02 5745c3eb7dSTony Lindgren #define OMAP_DMA_PORT_TIPB 0x03 5845c3eb7dSTony Lindgren #define OMAP_DMA_PORT_OCP_T2 0x04 5945c3eb7dSTony Lindgren #define OMAP_DMA_PORT_MPUI 0x05 6045c3eb7dSTony Lindgren 6145c3eb7dSTony Lindgren #define OMAP_DMA_AMODE_CONSTANT 0x00 6245c3eb7dSTony Lindgren #define OMAP_DMA_AMODE_POST_INC 0x01 6345c3eb7dSTony Lindgren #define OMAP_DMA_AMODE_SINGLE_IDX 0x02 6445c3eb7dSTony Lindgren #define OMAP_DMA_AMODE_DOUBLE_IDX 0x03 6545c3eb7dSTony Lindgren 6645c3eb7dSTony Lindgren #define DMA_DEFAULT_FIFO_DEPTH 0x10 6745c3eb7dSTony Lindgren #define DMA_DEFAULT_ARB_RATE 0x01 6845c3eb7dSTony Lindgren /* Pass THREAD_RESERVE ORed with THREAD_FIFO for tparams */ 6945c3eb7dSTony Lindgren #define DMA_THREAD_RESERVE_NORM (0x00 << 12) /* Def */ 7045c3eb7dSTony Lindgren #define DMA_THREAD_RESERVE_ONET (0x01 << 12) 7145c3eb7dSTony Lindgren #define DMA_THREAD_RESERVE_TWOT (0x02 << 12) 7245c3eb7dSTony Lindgren #define DMA_THREAD_RESERVE_THREET (0x03 << 12) 7345c3eb7dSTony Lindgren #define DMA_THREAD_FIFO_NONE (0x00 << 14) /* Def */ 7445c3eb7dSTony Lindgren #define DMA_THREAD_FIFO_75 (0x01 << 14) 7545c3eb7dSTony Lindgren #define DMA_THREAD_FIFO_25 (0x02 << 14) 7645c3eb7dSTony Lindgren #define DMA_THREAD_FIFO_50 (0x03 << 14) 7745c3eb7dSTony Lindgren 7845c3eb7dSTony Lindgren /* DMA4_OCP_SYSCONFIG bits */ 7945c3eb7dSTony Lindgren #define DMA_SYSCONFIG_MIDLEMODE_MASK (3 << 12) 8045c3eb7dSTony Lindgren #define DMA_SYSCONFIG_CLOCKACTIVITY_MASK (3 << 8) 8145c3eb7dSTony Lindgren #define DMA_SYSCONFIG_EMUFREE (1 << 5) 8245c3eb7dSTony Lindgren #define DMA_SYSCONFIG_SIDLEMODE_MASK (3 << 3) 8345c3eb7dSTony Lindgren #define DMA_SYSCONFIG_SOFTRESET (1 << 2) 8445c3eb7dSTony Lindgren #define DMA_SYSCONFIG_AUTOIDLE (1 << 0) 8545c3eb7dSTony Lindgren 8645c3eb7dSTony Lindgren #define DMA_SYSCONFIG_MIDLEMODE(n) ((n) << 12) 8745c3eb7dSTony Lindgren #define DMA_SYSCONFIG_SIDLEMODE(n) ((n) << 3) 8845c3eb7dSTony Lindgren 8945c3eb7dSTony Lindgren #define DMA_IDLEMODE_SMARTIDLE 0x2 9045c3eb7dSTony Lindgren #define DMA_IDLEMODE_NO_IDLE 0x1 9145c3eb7dSTony Lindgren #define DMA_IDLEMODE_FORCE_IDLE 0x0 9245c3eb7dSTony Lindgren 9345c3eb7dSTony Lindgren /* Chaining modes*/ 9445c3eb7dSTony Lindgren #ifndef CONFIG_ARCH_OMAP1 9545c3eb7dSTony Lindgren #define OMAP_DMA_STATIC_CHAIN 0x1 9645c3eb7dSTony Lindgren #define OMAP_DMA_DYNAMIC_CHAIN 0x2 9745c3eb7dSTony Lindgren #define OMAP_DMA_CHAIN_ACTIVE 0x1 9845c3eb7dSTony Lindgren #define OMAP_DMA_CHAIN_INACTIVE 0x0 997bedaa55SRussell King #endif 10045c3eb7dSTony Lindgren 10145c3eb7dSTony Lindgren #define DMA_CH_PRIO_HIGH 0x1 10245c3eb7dSTony Lindgren #define DMA_CH_PRIO_LOW 0x0 /* Def */ 10345c3eb7dSTony Lindgren 10445c3eb7dSTony Lindgren /* Errata handling */ 10545c3eb7dSTony Lindgren #define IS_DMA_ERRATA(id) (errata & (id)) 10645c3eb7dSTony Lindgren #define SET_DMA_ERRATA(id) (errata |= (id)) 10745c3eb7dSTony Lindgren 10845c3eb7dSTony Lindgren #define DMA_ERRATA_IFRAME_BUFFERING BIT(0x0) 10945c3eb7dSTony Lindgren #define DMA_ERRATA_PARALLEL_CHANNELS BIT(0x1) 11045c3eb7dSTony Lindgren #define DMA_ERRATA_i378 BIT(0x2) 11145c3eb7dSTony Lindgren #define DMA_ERRATA_i541 BIT(0x3) 11245c3eb7dSTony Lindgren #define DMA_ERRATA_i88 BIT(0x4) 11345c3eb7dSTony Lindgren #define DMA_ERRATA_3_3 BIT(0x5) 11445c3eb7dSTony Lindgren #define DMA_ROMCODE_BUG BIT(0x6) 11545c3eb7dSTony Lindgren 11645c3eb7dSTony Lindgren /* Attributes for OMAP DMA Contrller */ 11745c3eb7dSTony Lindgren #define DMA_LINKED_LCH BIT(0x0) 11845c3eb7dSTony Lindgren #define GLOBAL_PRIORITY BIT(0x1) 11945c3eb7dSTony Lindgren #define RESERVE_CHANNEL BIT(0x2) 12045c3eb7dSTony Lindgren #define IS_CSSA_32 BIT(0x3) 12145c3eb7dSTony Lindgren #define IS_CDSA_32 BIT(0x4) 12245c3eb7dSTony Lindgren #define IS_RW_PRIORITY BIT(0x5) 12345c3eb7dSTony Lindgren #define ENABLE_1510_MODE BIT(0x6) 12445c3eb7dSTony Lindgren #define SRC_PORT BIT(0x7) 12545c3eb7dSTony Lindgren #define DST_PORT BIT(0x8) 12645c3eb7dSTony Lindgren #define SRC_INDEX BIT(0x9) 12745c3eb7dSTony Lindgren #define DST_INDEX BIT(0xa) 12845c3eb7dSTony Lindgren #define IS_BURST_ONLY4 BIT(0xb) 12945c3eb7dSTony Lindgren #define CLEAR_CSR_ON_READ BIT(0xc) 13045c3eb7dSTony Lindgren #define IS_WORD_16 BIT(0xd) 13145c3eb7dSTony Lindgren #define ENABLE_16XX_MODE BIT(0xe) 13245c3eb7dSTony Lindgren #define HS_CHANNELS_RESERVED BIT(0xf) 13376be4a54SNishanth Menon #define DMA_ENGINE_HANDLE_IRQ BIT(0x10) 13445c3eb7dSTony Lindgren 13545c3eb7dSTony Lindgren /* Defines for DMA Capabilities */ 13645c3eb7dSTony Lindgren #define DMA_HAS_TRANSPARENT_CAPS (0x1 << 18) 13745c3eb7dSTony Lindgren #define DMA_HAS_CONSTANT_FILL_CAPS (0x1 << 19) 13845c3eb7dSTony Lindgren #define DMA_HAS_DESCRIPTOR_CAPS (0x3 << 20) 13945c3eb7dSTony Lindgren 14045c3eb7dSTony Lindgren enum omap_reg_offsets { 14145c3eb7dSTony Lindgren 14245c3eb7dSTony Lindgren GCR, GSCR, GRST1, HW_ID, 14345c3eb7dSTony Lindgren PCH2_ID, PCH0_ID, PCH1_ID, PCHG_ID, 14445c3eb7dSTony Lindgren PCHD_ID, CAPS_0, CAPS_1, CAPS_2, 14545c3eb7dSTony Lindgren CAPS_3, CAPS_4, PCH2_SR, PCH0_SR, 14645c3eb7dSTony Lindgren PCH1_SR, PCHD_SR, REVISION, IRQSTATUS_L0, 14745c3eb7dSTony Lindgren IRQSTATUS_L1, IRQSTATUS_L2, IRQSTATUS_L3, IRQENABLE_L0, 14845c3eb7dSTony Lindgren IRQENABLE_L1, IRQENABLE_L2, IRQENABLE_L3, SYSSTATUS, 14945c3eb7dSTony Lindgren OCP_SYSCONFIG, 15045c3eb7dSTony Lindgren 15145c3eb7dSTony Lindgren /* omap1+ specific */ 15245c3eb7dSTony Lindgren CPC, CCR2, LCH_CTRL, 15345c3eb7dSTony Lindgren 15445c3eb7dSTony Lindgren /* Common registers for all omap's */ 15545c3eb7dSTony Lindgren CSDP, CCR, CICR, CSR, 15645c3eb7dSTony Lindgren CEN, CFN, CSFI, CSEI, 15745c3eb7dSTony Lindgren CSAC, CDAC, CDEI, 15845c3eb7dSTony Lindgren CDFI, CLNK_CTRL, 15945c3eb7dSTony Lindgren 16045c3eb7dSTony Lindgren /* Channel specific registers */ 16145c3eb7dSTony Lindgren CSSA, CDSA, COLOR, 16245c3eb7dSTony Lindgren CCEN, CCFN, 16345c3eb7dSTony Lindgren 16445c3eb7dSTony Lindgren /* omap3630 and omap4 specific */ 16545c3eb7dSTony Lindgren CDP, CNDP, CCDN, 16645c3eb7dSTony Lindgren 16745c3eb7dSTony Lindgren }; 16845c3eb7dSTony Lindgren 16945c3eb7dSTony Lindgren enum omap_dma_burst_mode { 17045c3eb7dSTony Lindgren OMAP_DMA_DATA_BURST_DIS = 0, 17145c3eb7dSTony Lindgren OMAP_DMA_DATA_BURST_4, 17245c3eb7dSTony Lindgren OMAP_DMA_DATA_BURST_8, 17345c3eb7dSTony Lindgren OMAP_DMA_DATA_BURST_16, 17445c3eb7dSTony Lindgren }; 17545c3eb7dSTony Lindgren 17645c3eb7dSTony Lindgren enum end_type { 17745c3eb7dSTony Lindgren OMAP_DMA_LITTLE_ENDIAN = 0, 17845c3eb7dSTony Lindgren OMAP_DMA_BIG_ENDIAN 17945c3eb7dSTony Lindgren }; 18045c3eb7dSTony Lindgren 18145c3eb7dSTony Lindgren enum omap_dma_color_mode { 18245c3eb7dSTony Lindgren OMAP_DMA_COLOR_DIS = 0, 18345c3eb7dSTony Lindgren OMAP_DMA_CONSTANT_FILL, 18445c3eb7dSTony Lindgren OMAP_DMA_TRANSPARENT_COPY 18545c3eb7dSTony Lindgren }; 18645c3eb7dSTony Lindgren 18745c3eb7dSTony Lindgren enum omap_dma_write_mode { 18845c3eb7dSTony Lindgren OMAP_DMA_WRITE_NON_POSTED = 0, 18945c3eb7dSTony Lindgren OMAP_DMA_WRITE_POSTED, 19045c3eb7dSTony Lindgren OMAP_DMA_WRITE_LAST_NON_POSTED 19145c3eb7dSTony Lindgren }; 19245c3eb7dSTony Lindgren 19345c3eb7dSTony Lindgren enum omap_dma_channel_mode { 19445c3eb7dSTony Lindgren OMAP_DMA_LCH_2D = 0, 19545c3eb7dSTony Lindgren OMAP_DMA_LCH_G, 19645c3eb7dSTony Lindgren OMAP_DMA_LCH_P, 19745c3eb7dSTony Lindgren OMAP_DMA_LCH_PD 19845c3eb7dSTony Lindgren }; 19945c3eb7dSTony Lindgren 20045c3eb7dSTony Lindgren struct omap_dma_channel_params { 20145c3eb7dSTony Lindgren int data_type; /* data type 8,16,32 */ 20245c3eb7dSTony Lindgren int elem_count; /* number of elements in a frame */ 20345c3eb7dSTony Lindgren int frame_count; /* number of frames in a element */ 20445c3eb7dSTony Lindgren 20545c3eb7dSTony Lindgren int src_port; /* Only on OMAP1 REVISIT: Is this needed? */ 20645c3eb7dSTony Lindgren int src_amode; /* constant, post increment, indexed, 20745c3eb7dSTony Lindgren double indexed */ 20845c3eb7dSTony Lindgren unsigned long src_start; /* source address : physical */ 20945c3eb7dSTony Lindgren int src_ei; /* source element index */ 21045c3eb7dSTony Lindgren int src_fi; /* source frame index */ 21145c3eb7dSTony Lindgren 21245c3eb7dSTony Lindgren int dst_port; /* Only on OMAP1 REVISIT: Is this needed? */ 21345c3eb7dSTony Lindgren int dst_amode; /* constant, post increment, indexed, 21445c3eb7dSTony Lindgren double indexed */ 21545c3eb7dSTony Lindgren unsigned long dst_start; /* source address : physical */ 21645c3eb7dSTony Lindgren int dst_ei; /* source element index */ 21745c3eb7dSTony Lindgren int dst_fi; /* source frame index */ 21845c3eb7dSTony Lindgren 21945c3eb7dSTony Lindgren int trigger; /* trigger attached if the channel is 22045c3eb7dSTony Lindgren synchronized */ 22145c3eb7dSTony Lindgren int sync_mode; /* sycn on element, frame , block or packet */ 22245c3eb7dSTony Lindgren int src_or_dst_synch; /* source synch(1) or destination synch(0) */ 22345c3eb7dSTony Lindgren 22445c3eb7dSTony Lindgren int ie; /* interrupt enabled */ 22545c3eb7dSTony Lindgren 22645c3eb7dSTony Lindgren unsigned char read_prio;/* read priority */ 22745c3eb7dSTony Lindgren unsigned char write_prio;/* write priority */ 22845c3eb7dSTony Lindgren 22945c3eb7dSTony Lindgren #ifndef CONFIG_ARCH_OMAP1 23045c3eb7dSTony Lindgren enum omap_dma_burst_mode burst_mode; /* Burst mode 4/8/16 words */ 23145c3eb7dSTony Lindgren #endif 23245c3eb7dSTony Lindgren }; 23345c3eb7dSTony Lindgren 23445c3eb7dSTony Lindgren struct omap_dma_lch { 23545c3eb7dSTony Lindgren int next_lch; 23645c3eb7dSTony Lindgren int dev_id; 23745c3eb7dSTony Lindgren u16 saved_csr; 23845c3eb7dSTony Lindgren u16 enabled_irqs; 23945c3eb7dSTony Lindgren const char *dev_name; 24045c3eb7dSTony Lindgren void (*callback)(int lch, u16 ch_status, void *data); 24145c3eb7dSTony Lindgren void *data; 24245c3eb7dSTony Lindgren long flags; 24345c3eb7dSTony Lindgren /* required for Dynamic chaining */ 24445c3eb7dSTony Lindgren int prev_linked_ch; 24545c3eb7dSTony Lindgren int next_linked_ch; 24645c3eb7dSTony Lindgren int state; 24745c3eb7dSTony Lindgren int chain_id; 24845c3eb7dSTony Lindgren int status; 24945c3eb7dSTony Lindgren }; 25045c3eb7dSTony Lindgren 25145c3eb7dSTony Lindgren struct omap_dma_dev_attr { 25245c3eb7dSTony Lindgren u32 dev_caps; 25345c3eb7dSTony Lindgren u16 lch_count; 25445c3eb7dSTony Lindgren u16 chan_count; 25545c3eb7dSTony Lindgren }; 25645c3eb7dSTony Lindgren 25764a2dc3dSRussell King enum { 25864a2dc3dSRussell King OMAP_DMA_REG_NONE, 25964a2dc3dSRussell King OMAP_DMA_REG_16BIT, 26064a2dc3dSRussell King OMAP_DMA_REG_2X16BIT, 26164a2dc3dSRussell King OMAP_DMA_REG_32BIT, 26264a2dc3dSRussell King }; 26364a2dc3dSRussell King 26464a2dc3dSRussell King struct omap_dma_reg { 26564a2dc3dSRussell King u16 offset; 26664a2dc3dSRussell King u8 stride; 26764a2dc3dSRussell King u8 type; 26864a2dc3dSRussell King }; 26964a2dc3dSRussell King 27045c3eb7dSTony Lindgren /* System DMA platform data structure */ 27145c3eb7dSTony Lindgren struct omap_system_dma_plat_info { 272596c471bSRussell King const struct omap_dma_reg *reg_map; 273596c471bSRussell King unsigned channel_stride; 27445c3eb7dSTony Lindgren struct omap_dma_dev_attr *dma_attr; 27545c3eb7dSTony Lindgren u32 errata; 27645c3eb7dSTony Lindgren void (*show_dma_caps)(void); 27745c3eb7dSTony Lindgren void (*clear_lch_regs)(int lch); 27845c3eb7dSTony Lindgren void (*clear_dma)(int lch); 27945c3eb7dSTony Lindgren void (*dma_write)(u32 val, int reg, int lch); 28045c3eb7dSTony Lindgren u32 (*dma_read)(int reg, int lch); 28145c3eb7dSTony Lindgren }; 28245c3eb7dSTony Lindgren 28345c3eb7dSTony Lindgren #ifdef CONFIG_ARCH_OMAP2PLUS 28445c3eb7dSTony Lindgren #define dma_omap2plus() 1 28545c3eb7dSTony Lindgren #else 28645c3eb7dSTony Lindgren #define dma_omap2plus() 0 28745c3eb7dSTony Lindgren #endif 28845c3eb7dSTony Lindgren #define dma_omap1() (!dma_omap2plus()) 289b9e97822SRussell King #define __dma_omap15xx(d) (dma_omap1() && (d)->dev_caps & ENABLE_1510_MODE) 290b9e97822SRussell King #define __dma_omap16xx(d) (dma_omap1() && (d)->dev_caps & ENABLE_16XX_MODE) 291b9e97822SRussell King #define dma_omap15xx() __dma_omap15xx(d) 292b9e97822SRussell King #define dma_omap16xx() __dma_omap16xx(d) 29345c3eb7dSTony Lindgren 2941b416c4bSRussell King extern struct omap_system_dma_plat_info *omap_get_plat_info(void); 2951b416c4bSRussell King 29645c3eb7dSTony Lindgren extern void omap_set_dma_priority(int lch, int dst_port, int priority); 29745c3eb7dSTony Lindgren extern int omap_request_dma(int dev_id, const char *dev_name, 29845c3eb7dSTony Lindgren void (*callback)(int lch, u16 ch_status, void *data), 29945c3eb7dSTony Lindgren void *data, int *dma_ch); 30045c3eb7dSTony Lindgren extern void omap_enable_dma_irq(int ch, u16 irq_bits); 30145c3eb7dSTony Lindgren extern void omap_disable_dma_irq(int ch, u16 irq_bits); 30245c3eb7dSTony Lindgren extern void omap_free_dma(int ch); 30345c3eb7dSTony Lindgren extern void omap_start_dma(int lch); 30445c3eb7dSTony Lindgren extern void omap_stop_dma(int lch); 30545c3eb7dSTony Lindgren extern void omap_set_dma_transfer_params(int lch, int data_type, 30645c3eb7dSTony Lindgren int elem_count, int frame_count, 30745c3eb7dSTony Lindgren int sync_mode, 30845c3eb7dSTony Lindgren int dma_trigger, int src_or_dst_synch); 30945c3eb7dSTony Lindgren extern void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode); 31045c3eb7dSTony Lindgren extern void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode); 31145c3eb7dSTony Lindgren 31245c3eb7dSTony Lindgren extern void omap_set_dma_src_params(int lch, int src_port, int src_amode, 31345c3eb7dSTony Lindgren unsigned long src_start, 31445c3eb7dSTony Lindgren int src_ei, int src_fi); 31545c3eb7dSTony Lindgren extern void omap_set_dma_src_data_pack(int lch, int enable); 31645c3eb7dSTony Lindgren extern void omap_set_dma_src_burst_mode(int lch, 31745c3eb7dSTony Lindgren enum omap_dma_burst_mode burst_mode); 31845c3eb7dSTony Lindgren 31945c3eb7dSTony Lindgren extern void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode, 32045c3eb7dSTony Lindgren unsigned long dest_start, 32145c3eb7dSTony Lindgren int dst_ei, int dst_fi); 32245c3eb7dSTony Lindgren extern void omap_set_dma_dest_data_pack(int lch, int enable); 32345c3eb7dSTony Lindgren extern void omap_set_dma_dest_burst_mode(int lch, 32445c3eb7dSTony Lindgren enum omap_dma_burst_mode burst_mode); 32545c3eb7dSTony Lindgren 32645c3eb7dSTony Lindgren extern void omap_set_dma_params(int lch, 32745c3eb7dSTony Lindgren struct omap_dma_channel_params *params); 32845c3eb7dSTony Lindgren 32945c3eb7dSTony Lindgren extern void omap_dma_link_lch(int lch_head, int lch_queue); 33045c3eb7dSTony Lindgren 33145c3eb7dSTony Lindgren extern int omap_set_dma_callback(int lch, 33245c3eb7dSTony Lindgren void (*callback)(int lch, u16 ch_status, void *data), 33345c3eb7dSTony Lindgren void *data); 33445c3eb7dSTony Lindgren extern dma_addr_t omap_get_dma_src_pos(int lch); 33545c3eb7dSTony Lindgren extern dma_addr_t omap_get_dma_dst_pos(int lch); 33645c3eb7dSTony Lindgren extern int omap_get_dma_active_status(int lch); 33745c3eb7dSTony Lindgren extern int omap_dma_running(void); 33845c3eb7dSTony Lindgren extern void omap_dma_set_global_params(int arb_rate, int max_fifo_depth, 33945c3eb7dSTony Lindgren int tparams); 34045c3eb7dSTony Lindgren void omap_dma_global_context_save(void); 34145c3eb7dSTony Lindgren void omap_dma_global_context_restore(void); 34245c3eb7dSTony Lindgren 34381c44c2bSArnd Bergmann #if defined(CONFIG_ARCH_OMAP1) && IS_ENABLED(CONFIG_FB_OMAP) 34445c3eb7dSTony Lindgren #include <mach/lcd_dma.h> 34545c3eb7dSTony Lindgren #else 34645c3eb7dSTony Lindgren static inline int omap_lcd_dma_running(void) 34745c3eb7dSTony Lindgren { 34845c3eb7dSTony Lindgren return 0; 34945c3eb7dSTony Lindgren } 35045c3eb7dSTony Lindgren #endif 35145c3eb7dSTony Lindgren 35245c3eb7dSTony Lindgren #endif /* __LINUX_OMAP_DMA_H */ 353