1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * pci.h 4 * 5 * PCI defines and function prototypes 6 * Copyright 1994, Drew Eckhardt 7 * Copyright 1997--1999 Martin Mares <mj@ucw.cz> 8 * 9 * PCI Express ASPM defines and function prototypes 10 * Copyright (c) 2007 Intel Corp. 11 * Zhang Yanmin (yanmin.zhang@intel.com) 12 * Shaohua Li (shaohua.li@intel.com) 13 * 14 * For more information, please consult the following manuals (look at 15 * http://www.pcisig.com/ for how to get them): 16 * 17 * PCI BIOS Specification 18 * PCI Local Bus Specification 19 * PCI to PCI Bridge Specification 20 * PCI Express Specification 21 * PCI System Design Guide 22 */ 23 #ifndef LINUX_PCI_H 24 #define LINUX_PCI_H 25 26 27 #include <linux/mod_devicetable.h> 28 29 #include <linux/types.h> 30 #include <linux/init.h> 31 #include <linux/ioport.h> 32 #include <linux/list.h> 33 #include <linux/compiler.h> 34 #include <linux/errno.h> 35 #include <linux/kobject.h> 36 #include <linux/atomic.h> 37 #include <linux/device.h> 38 #include <linux/interrupt.h> 39 #include <linux/io.h> 40 #include <linux/resource_ext.h> 41 #include <linux/msi_api.h> 42 #include <uapi/linux/pci.h> 43 44 #include <linux/pci_ids.h> 45 46 #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \ 47 PCI_STATUS_SIG_SYSTEM_ERROR | \ 48 PCI_STATUS_REC_MASTER_ABORT | \ 49 PCI_STATUS_REC_TARGET_ABORT | \ 50 PCI_STATUS_SIG_TARGET_ABORT | \ 51 PCI_STATUS_PARITY) 52 53 /* Number of reset methods used in pci_reset_fn_methods array in pci.c */ 54 #define PCI_NUM_RESET_METHODS 7 55 56 #define PCI_RESET_PROBE true 57 #define PCI_RESET_DO_RESET false 58 59 /* 60 * The PCI interface treats multi-function devices as independent 61 * devices. The slot/function address of each device is encoded 62 * in a single byte as follows: 63 * 64 * 7:3 = slot 65 * 2:0 = function 66 * 67 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h. 68 * In the interest of not exposing interfaces to user-space unnecessarily, 69 * the following kernel-only defines are being added here. 70 */ 71 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn)) 72 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */ 73 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff) 74 75 /* pci_slot represents a physical slot */ 76 struct pci_slot { 77 struct pci_bus *bus; /* Bus this slot is on */ 78 struct list_head list; /* Node in list of slots */ 79 struct hotplug_slot *hotplug; /* Hotplug info (move here) */ 80 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */ 81 struct kobject kobj; 82 }; 83 84 static inline const char *pci_slot_name(const struct pci_slot *slot) 85 { 86 return kobject_name(&slot->kobj); 87 } 88 89 /* File state for mmap()s on /proc/bus/pci/X/Y */ 90 enum pci_mmap_state { 91 pci_mmap_io, 92 pci_mmap_mem 93 }; 94 95 /* For PCI devices, the region numbers are assigned this way: */ 96 enum { 97 /* #0-5: standard PCI resources */ 98 PCI_STD_RESOURCES, 99 PCI_STD_RESOURCE_END = PCI_STD_RESOURCES + PCI_STD_NUM_BARS - 1, 100 101 /* #6: expansion ROM resource */ 102 PCI_ROM_RESOURCE, 103 104 /* Device-specific resources */ 105 #ifdef CONFIG_PCI_IOV 106 PCI_IOV_RESOURCES, 107 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1, 108 #endif 109 110 /* PCI-to-PCI (P2P) bridge windows */ 111 #define PCI_BRIDGE_IO_WINDOW (PCI_BRIDGE_RESOURCES + 0) 112 #define PCI_BRIDGE_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 1) 113 #define PCI_BRIDGE_PREF_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 2) 114 115 /* CardBus bridge windows */ 116 #define PCI_CB_BRIDGE_IO_0_WINDOW (PCI_BRIDGE_RESOURCES + 0) 117 #define PCI_CB_BRIDGE_IO_1_WINDOW (PCI_BRIDGE_RESOURCES + 1) 118 #define PCI_CB_BRIDGE_MEM_0_WINDOW (PCI_BRIDGE_RESOURCES + 2) 119 #define PCI_CB_BRIDGE_MEM_1_WINDOW (PCI_BRIDGE_RESOURCES + 3) 120 121 /* Total number of bridge resources for P2P and CardBus */ 122 #define PCI_BRIDGE_RESOURCE_NUM 4 123 124 /* Resources assigned to buses behind the bridge */ 125 PCI_BRIDGE_RESOURCES, 126 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES + 127 PCI_BRIDGE_RESOURCE_NUM - 1, 128 129 /* Total resources associated with a PCI device */ 130 PCI_NUM_RESOURCES, 131 132 /* Preserve this for compatibility */ 133 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES, 134 }; 135 136 /** 137 * enum pci_interrupt_pin - PCI INTx interrupt values 138 * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt 139 * @PCI_INTERRUPT_INTA: PCI INTA pin 140 * @PCI_INTERRUPT_INTB: PCI INTB pin 141 * @PCI_INTERRUPT_INTC: PCI INTC pin 142 * @PCI_INTERRUPT_INTD: PCI INTD pin 143 * 144 * Corresponds to values for legacy PCI INTx interrupts, as can be found in the 145 * PCI_INTERRUPT_PIN register. 146 */ 147 enum pci_interrupt_pin { 148 PCI_INTERRUPT_UNKNOWN, 149 PCI_INTERRUPT_INTA, 150 PCI_INTERRUPT_INTB, 151 PCI_INTERRUPT_INTC, 152 PCI_INTERRUPT_INTD, 153 }; 154 155 /* The number of legacy PCI INTx interrupts */ 156 #define PCI_NUM_INTX 4 157 158 /* 159 * Reading from a device that doesn't respond typically returns ~0. A 160 * successful read from a device may also return ~0, so you need additional 161 * information to reliably identify errors. 162 */ 163 #define PCI_ERROR_RESPONSE (~0ULL) 164 #define PCI_SET_ERROR_RESPONSE(val) (*(val) = ((typeof(*(val))) PCI_ERROR_RESPONSE)) 165 #define PCI_POSSIBLE_ERROR(val) ((val) == ((typeof(val)) PCI_ERROR_RESPONSE)) 166 167 /* 168 * pci_power_t values must match the bits in the Capabilities PME_Support 169 * and Control/Status PowerState fields in the Power Management capability. 170 */ 171 typedef int __bitwise pci_power_t; 172 173 #define PCI_D0 ((pci_power_t __force) 0) 174 #define PCI_D1 ((pci_power_t __force) 1) 175 #define PCI_D2 ((pci_power_t __force) 2) 176 #define PCI_D3hot ((pci_power_t __force) 3) 177 #define PCI_D3cold ((pci_power_t __force) 4) 178 #define PCI_UNKNOWN ((pci_power_t __force) 5) 179 #define PCI_POWER_ERROR ((pci_power_t __force) -1) 180 181 /* Remember to update this when the list above changes! */ 182 extern const char *pci_power_names[]; 183 184 static inline const char *pci_power_name(pci_power_t state) 185 { 186 return pci_power_names[1 + (__force int) state]; 187 } 188 189 /** 190 * typedef pci_channel_state_t 191 * 192 * The pci_channel state describes connectivity between the CPU and 193 * the PCI device. If some PCI bus between here and the PCI device 194 * has crashed or locked up, this info is reflected here. 195 */ 196 typedef unsigned int __bitwise pci_channel_state_t; 197 198 enum { 199 /* I/O channel is in normal state */ 200 pci_channel_io_normal = (__force pci_channel_state_t) 1, 201 202 /* I/O to channel is blocked */ 203 pci_channel_io_frozen = (__force pci_channel_state_t) 2, 204 205 /* PCI card is dead */ 206 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3, 207 }; 208 209 typedef unsigned int __bitwise pcie_reset_state_t; 210 211 enum pcie_reset_state { 212 /* Reset is NOT asserted (Use to deassert reset) */ 213 pcie_deassert_reset = (__force pcie_reset_state_t) 1, 214 215 /* Use #PERST to reset PCIe device */ 216 pcie_warm_reset = (__force pcie_reset_state_t) 2, 217 218 /* Use PCIe Hot Reset to reset device */ 219 pcie_hot_reset = (__force pcie_reset_state_t) 3 220 }; 221 222 typedef unsigned short __bitwise pci_dev_flags_t; 223 enum pci_dev_flags { 224 /* INTX_DISABLE in PCI_COMMAND register disables MSI too */ 225 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0), 226 /* Device configuration is irrevocably lost if disabled into D3 */ 227 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1), 228 /* Provide indication device is assigned by a Virtual Machine Manager */ 229 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2), 230 /* Flag for quirk use to store if quirk-specific ACS is enabled */ 231 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3), 232 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */ 233 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5), 234 /* Do not use bus resets for device */ 235 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6), 236 /* Do not use PM reset even if device advertises NoSoftRst- */ 237 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7), 238 /* Get VPD from function 0 VPD */ 239 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8), 240 /* A non-root bridge where translation occurs, stop alias search here */ 241 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9), 242 /* Do not use FLR even if device advertises PCI_AF_CAP */ 243 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10), 244 /* Don't use Relaxed Ordering for TLPs directed at this device */ 245 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11), 246 /* Device does honor MSI masking despite saying otherwise */ 247 PCI_DEV_FLAGS_HAS_MSI_MASKING = (__force pci_dev_flags_t) (1 << 12), 248 }; 249 250 enum pci_irq_reroute_variant { 251 INTEL_IRQ_REROUTE_VARIANT = 1, 252 MAX_IRQ_REROUTE_VARIANTS = 3 253 }; 254 255 typedef unsigned short __bitwise pci_bus_flags_t; 256 enum pci_bus_flags { 257 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, 258 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, 259 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4, 260 PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8, 261 }; 262 263 /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */ 264 enum pcie_link_width { 265 PCIE_LNK_WIDTH_RESRV = 0x00, 266 PCIE_LNK_X1 = 0x01, 267 PCIE_LNK_X2 = 0x02, 268 PCIE_LNK_X4 = 0x04, 269 PCIE_LNK_X8 = 0x08, 270 PCIE_LNK_X12 = 0x0c, 271 PCIE_LNK_X16 = 0x10, 272 PCIE_LNK_X32 = 0x20, 273 PCIE_LNK_WIDTH_UNKNOWN = 0xff, 274 }; 275 276 /* See matching string table in pci_speed_string() */ 277 enum pci_bus_speed { 278 PCI_SPEED_33MHz = 0x00, 279 PCI_SPEED_66MHz = 0x01, 280 PCI_SPEED_66MHz_PCIX = 0x02, 281 PCI_SPEED_100MHz_PCIX = 0x03, 282 PCI_SPEED_133MHz_PCIX = 0x04, 283 PCI_SPEED_66MHz_PCIX_ECC = 0x05, 284 PCI_SPEED_100MHz_PCIX_ECC = 0x06, 285 PCI_SPEED_133MHz_PCIX_ECC = 0x07, 286 PCI_SPEED_66MHz_PCIX_266 = 0x09, 287 PCI_SPEED_100MHz_PCIX_266 = 0x0a, 288 PCI_SPEED_133MHz_PCIX_266 = 0x0b, 289 AGP_UNKNOWN = 0x0c, 290 AGP_1X = 0x0d, 291 AGP_2X = 0x0e, 292 AGP_4X = 0x0f, 293 AGP_8X = 0x10, 294 PCI_SPEED_66MHz_PCIX_533 = 0x11, 295 PCI_SPEED_100MHz_PCIX_533 = 0x12, 296 PCI_SPEED_133MHz_PCIX_533 = 0x13, 297 PCIE_SPEED_2_5GT = 0x14, 298 PCIE_SPEED_5_0GT = 0x15, 299 PCIE_SPEED_8_0GT = 0x16, 300 PCIE_SPEED_16_0GT = 0x17, 301 PCIE_SPEED_32_0GT = 0x18, 302 PCIE_SPEED_64_0GT = 0x19, 303 PCI_SPEED_UNKNOWN = 0xff, 304 }; 305 306 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev); 307 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev); 308 309 struct pci_vpd { 310 struct mutex lock; 311 unsigned int len; 312 u8 cap; 313 }; 314 315 struct irq_affinity; 316 struct pcie_link_state; 317 struct pci_sriov; 318 struct pci_p2pdma; 319 struct rcec_ea; 320 321 /* The pci_dev structure describes PCI devices */ 322 struct pci_dev { 323 struct list_head bus_list; /* Node in per-bus list */ 324 struct pci_bus *bus; /* Bus this device is on */ 325 struct pci_bus *subordinate; /* Bus this device bridges to */ 326 327 void *sysdata; /* Hook for sys-specific extension */ 328 struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */ 329 struct pci_slot *slot; /* Physical slot this device is in */ 330 331 unsigned int devfn; /* Encoded device & function index */ 332 unsigned short vendor; 333 unsigned short device; 334 unsigned short subsystem_vendor; 335 unsigned short subsystem_device; 336 unsigned int class; /* 3 bytes: (base,sub,prog-if) */ 337 u8 revision; /* PCI revision, low byte of class word */ 338 u8 hdr_type; /* PCI header type (`multi' flag masked out) */ 339 #ifdef CONFIG_PCIEAER 340 u16 aer_cap; /* AER capability offset */ 341 struct aer_stats *aer_stats; /* AER stats for this device */ 342 #endif 343 #ifdef CONFIG_PCIEPORTBUS 344 struct rcec_ea *rcec_ea; /* RCEC cached endpoint association */ 345 struct pci_dev *rcec; /* Associated RCEC device */ 346 #endif 347 u32 devcap; /* PCIe Device Capabilities */ 348 u8 pcie_cap; /* PCIe capability offset */ 349 u8 msi_cap; /* MSI capability offset */ 350 u8 msix_cap; /* MSI-X capability offset */ 351 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */ 352 u8 rom_base_reg; /* Config register controlling ROM */ 353 u8 pin; /* Interrupt pin this device uses */ 354 u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */ 355 unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */ 356 357 struct pci_driver *driver; /* Driver bound to this device */ 358 u64 dma_mask; /* Mask of the bits of bus address this 359 device implements. Normally this is 360 0xffffffff. You only need to change 361 this if your device has broken DMA 362 or supports 64-bit transfers. */ 363 364 struct device_dma_parameters dma_parms; 365 366 pci_power_t current_state; /* Current operating state. In ACPI, 367 this is D0-D3, D0 being fully 368 functional, and D3 being off. */ 369 unsigned int imm_ready:1; /* Supports Immediate Readiness */ 370 u8 pm_cap; /* PM capability offset */ 371 unsigned int pme_support:5; /* Bitmask of states from which PME# 372 can be generated */ 373 unsigned int pme_poll:1; /* Poll device's PME status bit */ 374 unsigned int d1_support:1; /* Low power state D1 is supported */ 375 unsigned int d2_support:1; /* Low power state D2 is supported */ 376 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */ 377 unsigned int no_d3cold:1; /* D3cold is forbidden */ 378 unsigned int bridge_d3:1; /* Allow D3 for bridge */ 379 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */ 380 unsigned int mmio_always_on:1; /* Disallow turning off io/mem 381 decoding during BAR sizing */ 382 unsigned int wakeup_prepared:1; 383 unsigned int skip_bus_pm:1; /* Internal: Skip bus-level PM */ 384 unsigned int ignore_hotplug:1; /* Ignore hotplug events */ 385 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators 386 controlled exclusively by 387 user sysfs */ 388 unsigned int clear_retrain_link:1; /* Need to clear Retrain Link 389 bit manually */ 390 unsigned int d3hot_delay; /* D3hot->D0 transition time in ms */ 391 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */ 392 393 #ifdef CONFIG_PCIEASPM 394 struct pcie_link_state *link_state; /* ASPM link state */ 395 unsigned int ltr_path:1; /* Latency Tolerance Reporting 396 supported from root to here */ 397 u16 l1ss; /* L1SS Capability pointer */ 398 #endif 399 unsigned int pasid_no_tlp:1; /* PASID works without TLP Prefix */ 400 unsigned int eetlp_prefix_path:1; /* End-to-End TLP Prefix */ 401 402 pci_channel_state_t error_state; /* Current connectivity state */ 403 struct device dev; /* Generic device interface */ 404 405 int cfg_size; /* Size of config space */ 406 407 /* 408 * Instead of touching interrupt line and base address registers 409 * directly, use the values stored here. They might be different! 410 */ 411 unsigned int irq; 412 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ 413 struct resource driver_exclusive_resource; /* driver exclusive resource ranges */ 414 415 bool match_driver; /* Skip attaching driver */ 416 417 unsigned int transparent:1; /* Subtractive decode bridge */ 418 unsigned int io_window:1; /* Bridge has I/O window */ 419 unsigned int pref_window:1; /* Bridge has pref mem window */ 420 unsigned int pref_64_window:1; /* Pref mem window is 64-bit */ 421 unsigned int multifunction:1; /* Multi-function device */ 422 423 unsigned int is_busmaster:1; /* Is busmaster */ 424 unsigned int no_msi:1; /* May not use MSI */ 425 unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */ 426 unsigned int block_cfg_access:1; /* Config space access blocked */ 427 unsigned int broken_parity_status:1; /* Generates false positive parity */ 428 unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */ 429 unsigned int msi_enabled:1; 430 unsigned int msix_enabled:1; 431 unsigned int ari_enabled:1; /* ARI forwarding */ 432 unsigned int ats_enabled:1; /* Address Translation Svc */ 433 unsigned int pasid_enabled:1; /* Process Address Space ID */ 434 unsigned int pri_enabled:1; /* Page Request Interface */ 435 unsigned int is_managed:1; /* Managed via devres */ 436 unsigned int is_msi_managed:1; /* MSI release via devres installed */ 437 unsigned int needs_freset:1; /* Requires fundamental reset */ 438 unsigned int state_saved:1; 439 unsigned int is_physfn:1; 440 unsigned int is_virtfn:1; 441 unsigned int is_hotplug_bridge:1; 442 unsigned int shpc_managed:1; /* SHPC owned by shpchp */ 443 unsigned int is_thunderbolt:1; /* Thunderbolt controller */ 444 /* 445 * Devices marked being untrusted are the ones that can potentially 446 * execute DMA attacks and similar. They are typically connected 447 * through external ports such as Thunderbolt but not limited to 448 * that. When an IOMMU is enabled they should be getting full 449 * mappings to make sure they cannot access arbitrary memory. 450 */ 451 unsigned int untrusted:1; 452 /* 453 * Info from the platform, e.g., ACPI or device tree, may mark a 454 * device as "external-facing". An external-facing device is 455 * itself internal but devices downstream from it are external. 456 */ 457 unsigned int external_facing:1; 458 unsigned int broken_intx_masking:1; /* INTx masking can't be used */ 459 unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */ 460 unsigned int irq_managed:1; 461 unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */ 462 unsigned int is_probed:1; /* Device probing in progress */ 463 unsigned int link_active_reporting:1;/* Device capable of reporting link active */ 464 unsigned int no_vf_scan:1; /* Don't scan for VFs after IOV enablement */ 465 unsigned int no_command_memory:1; /* No PCI_COMMAND_MEMORY */ 466 unsigned int rom_bar_overlap:1; /* ROM BAR disable broken */ 467 pci_dev_flags_t dev_flags; 468 atomic_t enable_cnt; /* pci_enable_device has been called */ 469 470 u32 saved_config_space[16]; /* Config space saved at suspend time */ 471 struct hlist_head saved_cap_space; 472 int rom_attr_enabled; /* Display of ROM attribute enabled? */ 473 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ 474 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */ 475 476 #ifdef CONFIG_HOTPLUG_PCI_PCIE 477 unsigned int broken_cmd_compl:1; /* No compl for some cmds */ 478 #endif 479 #ifdef CONFIG_PCIE_PTM 480 u16 ptm_cap; /* PTM Capability */ 481 unsigned int ptm_root:1; 482 unsigned int ptm_enabled:1; 483 u8 ptm_granularity; 484 #endif 485 #ifdef CONFIG_PCI_MSI 486 void __iomem *msix_base; 487 raw_spinlock_t msi_lock; 488 #endif 489 struct pci_vpd vpd; 490 #ifdef CONFIG_PCIE_DPC 491 u16 dpc_cap; 492 unsigned int dpc_rp_extensions:1; 493 u8 dpc_rp_log_size; 494 #endif 495 #ifdef CONFIG_PCI_ATS 496 union { 497 struct pci_sriov *sriov; /* PF: SR-IOV info */ 498 struct pci_dev *physfn; /* VF: related PF */ 499 }; 500 u16 ats_cap; /* ATS Capability offset */ 501 u8 ats_stu; /* ATS Smallest Translation Unit */ 502 #endif 503 #ifdef CONFIG_PCI_PRI 504 u16 pri_cap; /* PRI Capability offset */ 505 u32 pri_reqs_alloc; /* Number of PRI requests allocated */ 506 unsigned int pasid_required:1; /* PRG Response PASID Required */ 507 #endif 508 #ifdef CONFIG_PCI_PASID 509 u16 pasid_cap; /* PASID Capability offset */ 510 u16 pasid_features; 511 #endif 512 #ifdef CONFIG_PCI_P2PDMA 513 struct pci_p2pdma __rcu *p2pdma; 514 #endif 515 u16 acs_cap; /* ACS Capability offset */ 516 phys_addr_t rom; /* Physical address if not from BAR */ 517 size_t romlen; /* Length if not from BAR */ 518 /* 519 * Driver name to force a match. Do not set directly, because core 520 * frees it. Use driver_set_override() to set or clear it. 521 */ 522 const char *driver_override; 523 524 unsigned long priv_flags; /* Private flags for the PCI driver */ 525 526 /* These methods index pci_reset_fn_methods[] */ 527 u8 reset_methods[PCI_NUM_RESET_METHODS]; /* In priority order */ 528 }; 529 530 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 531 { 532 #ifdef CONFIG_PCI_IOV 533 if (dev->is_virtfn) 534 dev = dev->physfn; 535 #endif 536 return dev; 537 } 538 539 struct pci_dev *pci_alloc_dev(struct pci_bus *bus); 540 541 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 542 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) 543 544 static inline int pci_channel_offline(struct pci_dev *pdev) 545 { 546 return (pdev->error_state != pci_channel_io_normal); 547 } 548 549 /* 550 * Currently in ACPI spec, for each PCI host bridge, PCI Segment 551 * Group number is limited to a 16-bit value, therefore (int)-1 is 552 * not a valid PCI domain number, and can be used as a sentinel 553 * value indicating ->domain_nr is not set by the driver (and 554 * CONFIG_PCI_DOMAINS_GENERIC=y archs will set it with 555 * pci_bus_find_domain_nr()). 556 */ 557 #define PCI_DOMAIN_NR_NOT_SET (-1) 558 559 struct pci_host_bridge { 560 struct device dev; 561 struct pci_bus *bus; /* Root bus */ 562 struct pci_ops *ops; 563 struct pci_ops *child_ops; 564 void *sysdata; 565 int busnr; 566 int domain_nr; 567 struct list_head windows; /* resource_entry */ 568 struct list_head dma_ranges; /* dma ranges resource list */ 569 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */ 570 int (*map_irq)(const struct pci_dev *, u8, u8); 571 void (*release_fn)(struct pci_host_bridge *); 572 void *release_data; 573 unsigned int ignore_reset_delay:1; /* For entire hierarchy */ 574 unsigned int no_ext_tags:1; /* No Extended Tags */ 575 unsigned int native_aer:1; /* OS may use PCIe AER */ 576 unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */ 577 unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */ 578 unsigned int native_pme:1; /* OS may use PCIe PME */ 579 unsigned int native_ltr:1; /* OS may use PCIe LTR */ 580 unsigned int native_dpc:1; /* OS may use PCIe DPC */ 581 unsigned int preserve_config:1; /* Preserve FW resource setup */ 582 unsigned int size_windows:1; /* Enable root bus sizing */ 583 unsigned int msi_domain:1; /* Bridge wants MSI domain */ 584 585 /* Resource alignment requirements */ 586 resource_size_t (*align_resource)(struct pci_dev *dev, 587 const struct resource *res, 588 resource_size_t start, 589 resource_size_t size, 590 resource_size_t align); 591 unsigned long private[] ____cacheline_aligned; 592 }; 593 594 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev) 595 596 static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge) 597 { 598 return (void *)bridge->private; 599 } 600 601 static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv) 602 { 603 return container_of(priv, struct pci_host_bridge, private); 604 } 605 606 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv); 607 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev, 608 size_t priv); 609 void pci_free_host_bridge(struct pci_host_bridge *bridge); 610 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus); 611 612 void pci_set_host_bridge_release(struct pci_host_bridge *bridge, 613 void (*release_fn)(struct pci_host_bridge *), 614 void *release_data); 615 616 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge); 617 618 /* 619 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond 620 * to P2P or CardBus bridge windows) go in a table. Additional ones (for 621 * buses below host bridges or subtractive decode bridges) go in the list. 622 * Use pci_bus_for_each_resource() to iterate through all the resources. 623 */ 624 625 /* 626 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly 627 * and there's no way to program the bridge with the details of the window. 628 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive- 629 * decode bit set, because they are explicit and can be programmed with _SRS. 630 */ 631 #define PCI_SUBTRACTIVE_DECODE 0x1 632 633 struct pci_bus_resource { 634 struct list_head list; 635 struct resource *res; 636 unsigned int flags; 637 }; 638 639 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ 640 641 struct pci_bus { 642 struct list_head node; /* Node in list of buses */ 643 struct pci_bus *parent; /* Parent bus this bridge is on */ 644 struct list_head children; /* List of child buses */ 645 struct list_head devices; /* List of devices on this bus */ 646 struct pci_dev *self; /* Bridge device as seen by parent */ 647 struct list_head slots; /* List of slots on this bus; 648 protected by pci_slot_mutex */ 649 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM]; 650 struct list_head resources; /* Address space routed to this bus */ 651 struct resource busn_res; /* Bus numbers routed to this bus */ 652 653 struct pci_ops *ops; /* Configuration access functions */ 654 void *sysdata; /* Hook for sys-specific extension */ 655 struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */ 656 657 unsigned char number; /* Bus number */ 658 unsigned char primary; /* Number of primary bridge */ 659 unsigned char max_bus_speed; /* enum pci_bus_speed */ 660 unsigned char cur_bus_speed; /* enum pci_bus_speed */ 661 #ifdef CONFIG_PCI_DOMAINS_GENERIC 662 int domain_nr; 663 #endif 664 665 char name[48]; 666 667 unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */ 668 pci_bus_flags_t bus_flags; /* Inherited by child buses */ 669 struct device *bridge; 670 struct device dev; 671 struct bin_attribute *legacy_io; /* Legacy I/O for this bus */ 672 struct bin_attribute *legacy_mem; /* Legacy mem */ 673 unsigned int is_added:1; 674 unsigned int unsafe_warn:1; /* warned about RW1C config write */ 675 }; 676 677 #define to_pci_bus(n) container_of(n, struct pci_bus, dev) 678 679 static inline u16 pci_dev_id(struct pci_dev *dev) 680 { 681 return PCI_DEVID(dev->bus->number, dev->devfn); 682 } 683 684 /* 685 * Returns true if the PCI bus is root (behind host-PCI bridge), 686 * false otherwise 687 * 688 * Some code assumes that "bus->self == NULL" means that bus is a root bus. 689 * This is incorrect because "virtual" buses added for SR-IOV (via 690 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses. 691 */ 692 static inline bool pci_is_root_bus(struct pci_bus *pbus) 693 { 694 return !(pbus->parent); 695 } 696 697 /** 698 * pci_is_bridge - check if the PCI device is a bridge 699 * @dev: PCI device 700 * 701 * Return true if the PCI device is bridge whether it has subordinate 702 * or not. 703 */ 704 static inline bool pci_is_bridge(struct pci_dev *dev) 705 { 706 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || 707 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS; 708 } 709 710 #define for_each_pci_bridge(dev, bus) \ 711 list_for_each_entry(dev, &bus->devices, bus_list) \ 712 if (!pci_is_bridge(dev)) {} else 713 714 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev) 715 { 716 dev = pci_physfn(dev); 717 if (pci_is_root_bus(dev->bus)) 718 return NULL; 719 720 return dev->bus->self; 721 } 722 723 #ifdef CONFIG_PCI_MSI 724 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) 725 { 726 return pci_dev->msi_enabled || pci_dev->msix_enabled; 727 } 728 #else 729 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; } 730 #endif 731 732 /* Error values that may be returned by PCI functions */ 733 #define PCIBIOS_SUCCESSFUL 0x00 734 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 735 #define PCIBIOS_BAD_VENDOR_ID 0x83 736 #define PCIBIOS_DEVICE_NOT_FOUND 0x86 737 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87 738 #define PCIBIOS_SET_FAILED 0x88 739 #define PCIBIOS_BUFFER_TOO_SMALL 0x89 740 741 /* Translate above to generic errno for passing back through non-PCI code */ 742 static inline int pcibios_err_to_errno(int err) 743 { 744 if (err <= PCIBIOS_SUCCESSFUL) 745 return err; /* Assume already errno */ 746 747 switch (err) { 748 case PCIBIOS_FUNC_NOT_SUPPORTED: 749 return -ENOENT; 750 case PCIBIOS_BAD_VENDOR_ID: 751 return -ENOTTY; 752 case PCIBIOS_DEVICE_NOT_FOUND: 753 return -ENODEV; 754 case PCIBIOS_BAD_REGISTER_NUMBER: 755 return -EFAULT; 756 case PCIBIOS_SET_FAILED: 757 return -EIO; 758 case PCIBIOS_BUFFER_TOO_SMALL: 759 return -ENOSPC; 760 } 761 762 return -ERANGE; 763 } 764 765 /* Low-level architecture-dependent routines */ 766 767 struct pci_ops { 768 int (*add_bus)(struct pci_bus *bus); 769 void (*remove_bus)(struct pci_bus *bus); 770 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where); 771 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); 772 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); 773 }; 774 775 /* 776 * ACPI needs to be able to access PCI config space before we've done a 777 * PCI bus scan and created pci_bus structures. 778 */ 779 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn, 780 int reg, int len, u32 *val); 781 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn, 782 int reg, int len, u32 val); 783 784 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 785 typedef u64 pci_bus_addr_t; 786 #else 787 typedef u32 pci_bus_addr_t; 788 #endif 789 790 struct pci_bus_region { 791 pci_bus_addr_t start; 792 pci_bus_addr_t end; 793 }; 794 795 struct pci_dynids { 796 spinlock_t lock; /* Protects list, index */ 797 struct list_head list; /* For IDs added at runtime */ 798 }; 799 800 801 /* 802 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides 803 * a set of callbacks in struct pci_error_handlers, that device driver 804 * will be notified of PCI bus errors, and will be driven to recovery 805 * when an error occurs. 806 */ 807 808 typedef unsigned int __bitwise pci_ers_result_t; 809 810 enum pci_ers_result { 811 /* No result/none/not supported in device driver */ 812 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1, 813 814 /* Device driver can recover without slot reset */ 815 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2, 816 817 /* Device driver wants slot to be reset */ 818 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3, 819 820 /* Device has completely failed, is unrecoverable */ 821 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4, 822 823 /* Device driver is fully recovered and operational */ 824 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5, 825 826 /* No AER capabilities registered for the driver */ 827 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6, 828 }; 829 830 /* PCI bus error event callbacks */ 831 struct pci_error_handlers { 832 /* PCI bus error detected on this device */ 833 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 834 pci_channel_state_t error); 835 836 /* MMIO has been re-enabled, but not DMA */ 837 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 838 839 /* PCI slot has been reset */ 840 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 841 842 /* PCI function reset prepare or completed */ 843 void (*reset_prepare)(struct pci_dev *dev); 844 void (*reset_done)(struct pci_dev *dev); 845 846 /* Device driver may resume normal operations */ 847 void (*resume)(struct pci_dev *dev); 848 849 /* Allow device driver to record more details of a correctable error */ 850 void (*cor_error_detected)(struct pci_dev *dev); 851 }; 852 853 854 struct module; 855 856 /** 857 * struct pci_driver - PCI driver structure 858 * @node: List of driver structures. 859 * @name: Driver name. 860 * @id_table: Pointer to table of device IDs the driver is 861 * interested in. Most drivers should export this 862 * table using MODULE_DEVICE_TABLE(pci,...). 863 * @probe: This probing function gets called (during execution 864 * of pci_register_driver() for already existing 865 * devices or later if a new device gets inserted) for 866 * all PCI devices which match the ID table and are not 867 * "owned" by the other drivers yet. This function gets 868 * passed a "struct pci_dev \*" for each device whose 869 * entry in the ID table matches the device. The probe 870 * function returns zero when the driver chooses to 871 * take "ownership" of the device or an error code 872 * (negative number) otherwise. 873 * The probe function always gets called from process 874 * context, so it can sleep. 875 * @remove: The remove() function gets called whenever a device 876 * being handled by this driver is removed (either during 877 * deregistration of the driver or when it's manually 878 * pulled out of a hot-pluggable slot). 879 * The remove function always gets called from process 880 * context, so it can sleep. 881 * @suspend: Put device into low power state. 882 * @resume: Wake device from low power state. 883 * (Please see Documentation/power/pci.rst for descriptions 884 * of PCI Power Management and the related functions.) 885 * @shutdown: Hook into reboot_notifier_list (kernel/sys.c). 886 * Intended to stop any idling DMA operations. 887 * Useful for enabling wake-on-lan (NIC) or changing 888 * the power state of a device before reboot. 889 * e.g. drivers/net/e100.c. 890 * @sriov_configure: Optional driver callback to allow configuration of 891 * number of VFs to enable via sysfs "sriov_numvfs" file. 892 * @sriov_set_msix_vec_count: PF Driver callback to change number of MSI-X 893 * vectors on a VF. Triggered via sysfs "sriov_vf_msix_count". 894 * This will change MSI-X Table Size in the VF Message Control 895 * registers. 896 * @sriov_get_vf_total_msix: PF driver callback to get the total number of 897 * MSI-X vectors available for distribution to the VFs. 898 * @err_handler: See Documentation/PCI/pci-error-recovery.rst 899 * @groups: Sysfs attribute groups. 900 * @dev_groups: Attributes attached to the device that will be 901 * created once it is bound to the driver. 902 * @driver: Driver model structure. 903 * @dynids: List of dynamically added device IDs. 904 * @driver_managed_dma: Device driver doesn't use kernel DMA API for DMA. 905 * For most device drivers, no need to care about this flag 906 * as long as all DMAs are handled through the kernel DMA API. 907 * For some special ones, for example VFIO drivers, they know 908 * how to manage the DMA themselves and set this flag so that 909 * the IOMMU layer will allow them to setup and manage their 910 * own I/O address space. 911 */ 912 struct pci_driver { 913 struct list_head node; 914 const char *name; 915 const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */ 916 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */ 917 void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */ 918 int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */ 919 int (*resume)(struct pci_dev *dev); /* Device woken up */ 920 void (*shutdown)(struct pci_dev *dev); 921 int (*sriov_configure)(struct pci_dev *dev, int num_vfs); /* On PF */ 922 int (*sriov_set_msix_vec_count)(struct pci_dev *vf, int msix_vec_count); /* On PF */ 923 u32 (*sriov_get_vf_total_msix)(struct pci_dev *pf); 924 const struct pci_error_handlers *err_handler; 925 const struct attribute_group **groups; 926 const struct attribute_group **dev_groups; 927 struct device_driver driver; 928 struct pci_dynids dynids; 929 bool driver_managed_dma; 930 }; 931 932 static inline struct pci_driver *to_pci_driver(struct device_driver *drv) 933 { 934 return drv ? container_of(drv, struct pci_driver, driver) : NULL; 935 } 936 937 /** 938 * PCI_DEVICE - macro used to describe a specific PCI device 939 * @vend: the 16 bit PCI Vendor ID 940 * @dev: the 16 bit PCI Device ID 941 * 942 * This macro is used to create a struct pci_device_id that matches a 943 * specific device. The subvendor and subdevice fields will be set to 944 * PCI_ANY_ID. 945 */ 946 #define PCI_DEVICE(vend,dev) \ 947 .vendor = (vend), .device = (dev), \ 948 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 949 950 /** 951 * PCI_DEVICE_DRIVER_OVERRIDE - macro used to describe a PCI device with 952 * override_only flags. 953 * @vend: the 16 bit PCI Vendor ID 954 * @dev: the 16 bit PCI Device ID 955 * @driver_override: the 32 bit PCI Device override_only 956 * 957 * This macro is used to create a struct pci_device_id that matches only a 958 * driver_override device. The subvendor and subdevice fields will be set to 959 * PCI_ANY_ID. 960 */ 961 #define PCI_DEVICE_DRIVER_OVERRIDE(vend, dev, driver_override) \ 962 .vendor = (vend), .device = (dev), .subvendor = PCI_ANY_ID, \ 963 .subdevice = PCI_ANY_ID, .override_only = (driver_override) 964 965 /** 966 * PCI_DRIVER_OVERRIDE_DEVICE_VFIO - macro used to describe a VFIO 967 * "driver_override" PCI device. 968 * @vend: the 16 bit PCI Vendor ID 969 * @dev: the 16 bit PCI Device ID 970 * 971 * This macro is used to create a struct pci_device_id that matches a 972 * specific device. The subvendor and subdevice fields will be set to 973 * PCI_ANY_ID and the driver_override will be set to 974 * PCI_ID_F_VFIO_DRIVER_OVERRIDE. 975 */ 976 #define PCI_DRIVER_OVERRIDE_DEVICE_VFIO(vend, dev) \ 977 PCI_DEVICE_DRIVER_OVERRIDE(vend, dev, PCI_ID_F_VFIO_DRIVER_OVERRIDE) 978 979 /** 980 * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem 981 * @vend: the 16 bit PCI Vendor ID 982 * @dev: the 16 bit PCI Device ID 983 * @subvend: the 16 bit PCI Subvendor ID 984 * @subdev: the 16 bit PCI Subdevice ID 985 * 986 * This macro is used to create a struct pci_device_id that matches a 987 * specific device with subsystem information. 988 */ 989 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \ 990 .vendor = (vend), .device = (dev), \ 991 .subvendor = (subvend), .subdevice = (subdev) 992 993 /** 994 * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class 995 * @dev_class: the class, subclass, prog-if triple for this device 996 * @dev_class_mask: the class mask for this device 997 * 998 * This macro is used to create a struct pci_device_id that matches a 999 * specific PCI class. The vendor, device, subvendor, and subdevice 1000 * fields will be set to PCI_ANY_ID. 1001 */ 1002 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \ 1003 .class = (dev_class), .class_mask = (dev_class_mask), \ 1004 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ 1005 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 1006 1007 /** 1008 * PCI_VDEVICE - macro used to describe a specific PCI device in short form 1009 * @vend: the vendor name 1010 * @dev: the 16 bit PCI Device ID 1011 * 1012 * This macro is used to create a struct pci_device_id that matches a 1013 * specific PCI device. The subvendor, and subdevice fields will be set 1014 * to PCI_ANY_ID. The macro allows the next field to follow as the device 1015 * private data. 1016 */ 1017 #define PCI_VDEVICE(vend, dev) \ 1018 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \ 1019 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0 1020 1021 /** 1022 * PCI_DEVICE_DATA - macro used to describe a specific PCI device in very short form 1023 * @vend: the vendor name (without PCI_VENDOR_ID_ prefix) 1024 * @dev: the device name (without PCI_DEVICE_ID_<vend>_ prefix) 1025 * @data: the driver data to be filled 1026 * 1027 * This macro is used to create a struct pci_device_id that matches a 1028 * specific PCI device. The subvendor, and subdevice fields will be set 1029 * to PCI_ANY_ID. 1030 */ 1031 #define PCI_DEVICE_DATA(vend, dev, data) \ 1032 .vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \ 1033 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \ 1034 .driver_data = (kernel_ulong_t)(data) 1035 1036 enum { 1037 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */ 1038 PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */ 1039 PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */ 1040 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */ 1041 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */ 1042 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */ 1043 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */ 1044 }; 1045 1046 #define PCI_IRQ_LEGACY (1 << 0) /* Allow legacy interrupts */ 1047 #define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */ 1048 #define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */ 1049 #define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */ 1050 1051 /* These external functions are only available when PCI support is enabled */ 1052 #ifdef CONFIG_PCI 1053 1054 extern unsigned int pci_flags; 1055 1056 static inline void pci_set_flags(int flags) { pci_flags = flags; } 1057 static inline void pci_add_flags(int flags) { pci_flags |= flags; } 1058 static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; } 1059 static inline int pci_has_flag(int flag) { return pci_flags & flag; } 1060 1061 void pcie_bus_configure_settings(struct pci_bus *bus); 1062 1063 enum pcie_bus_config_types { 1064 PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */ 1065 PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */ 1066 PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */ 1067 PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */ 1068 PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */ 1069 }; 1070 1071 extern enum pcie_bus_config_types pcie_bus_config; 1072 1073 extern struct bus_type pci_bus_type; 1074 1075 /* Do NOT directly access these two variables, unless you are arch-specific PCI 1076 * code, or PCI core code. */ 1077 extern struct list_head pci_root_buses; /* List of all known PCI buses */ 1078 /* Some device drivers need know if PCI is initiated */ 1079 int no_pci_devices(void); 1080 1081 void pcibios_resource_survey_bus(struct pci_bus *bus); 1082 void pcibios_bus_add_device(struct pci_dev *pdev); 1083 void pcibios_add_bus(struct pci_bus *bus); 1084 void pcibios_remove_bus(struct pci_bus *bus); 1085 void pcibios_fixup_bus(struct pci_bus *); 1086 int __must_check pcibios_enable_device(struct pci_dev *, int mask); 1087 /* Architecture-specific versions may override this (weak) */ 1088 char *pcibios_setup(char *str); 1089 1090 /* Used only when drivers/pci/setup.c is used */ 1091 resource_size_t pcibios_align_resource(void *, const struct resource *, 1092 resource_size_t, 1093 resource_size_t); 1094 1095 /* Weak but can be overridden by arch */ 1096 void pci_fixup_cardbus(struct pci_bus *); 1097 1098 /* Generic PCI functions used internally */ 1099 1100 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region, 1101 struct resource *res); 1102 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res, 1103 struct pci_bus_region *region); 1104 void pcibios_scan_specific_bus(int busn); 1105 struct pci_bus *pci_find_bus(int domain, int busnr); 1106 void pci_bus_add_devices(const struct pci_bus *bus); 1107 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata); 1108 struct pci_bus *pci_create_root_bus(struct device *parent, int bus, 1109 struct pci_ops *ops, void *sysdata, 1110 struct list_head *resources); 1111 int pci_host_probe(struct pci_host_bridge *bridge); 1112 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax); 1113 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax); 1114 void pci_bus_release_busn_res(struct pci_bus *b); 1115 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, 1116 struct pci_ops *ops, void *sysdata, 1117 struct list_head *resources); 1118 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge); 1119 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, 1120 int busnr); 1121 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr, 1122 const char *name, 1123 struct hotplug_slot *hotplug); 1124 void pci_destroy_slot(struct pci_slot *slot); 1125 #ifdef CONFIG_SYSFS 1126 void pci_dev_assign_slot(struct pci_dev *dev); 1127 #else 1128 static inline void pci_dev_assign_slot(struct pci_dev *dev) { } 1129 #endif 1130 int pci_scan_slot(struct pci_bus *bus, int devfn); 1131 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn); 1132 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus); 1133 unsigned int pci_scan_child_bus(struct pci_bus *bus); 1134 void pci_bus_add_device(struct pci_dev *dev); 1135 void pci_read_bridge_bases(struct pci_bus *child); 1136 struct resource *pci_find_parent_resource(const struct pci_dev *dev, 1137 struct resource *res); 1138 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin); 1139 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge); 1140 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp); 1141 struct pci_dev *pci_dev_get(struct pci_dev *dev); 1142 void pci_dev_put(struct pci_dev *dev); 1143 void pci_remove_bus(struct pci_bus *b); 1144 void pci_stop_and_remove_bus_device(struct pci_dev *dev); 1145 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev); 1146 void pci_stop_root_bus(struct pci_bus *bus); 1147 void pci_remove_root_bus(struct pci_bus *bus); 1148 void pci_setup_cardbus(struct pci_bus *bus); 1149 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type); 1150 void pci_sort_breadthfirst(void); 1151 #define dev_is_pci(d) ((d)->bus == &pci_bus_type) 1152 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false)) 1153 1154 /* Generic PCI functions exported to card drivers */ 1155 1156 u8 pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap); 1157 u8 pci_find_capability(struct pci_dev *dev, int cap); 1158 u8 pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap); 1159 u8 pci_find_ht_capability(struct pci_dev *dev, int ht_cap); 1160 u8 pci_find_next_ht_capability(struct pci_dev *dev, u8 pos, int ht_cap); 1161 u16 pci_find_ext_capability(struct pci_dev *dev, int cap); 1162 u16 pci_find_next_ext_capability(struct pci_dev *dev, u16 pos, int cap); 1163 struct pci_bus *pci_find_next_bus(const struct pci_bus *from); 1164 u16 pci_find_vsec_capability(struct pci_dev *dev, u16 vendor, int cap); 1165 u16 pci_find_dvsec_capability(struct pci_dev *dev, u16 vendor, u16 dvsec); 1166 1167 u64 pci_get_dsn(struct pci_dev *dev); 1168 1169 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device, 1170 struct pci_dev *from); 1171 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device, 1172 unsigned int ss_vendor, unsigned int ss_device, 1173 struct pci_dev *from); 1174 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn); 1175 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus, 1176 unsigned int devfn); 1177 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from); 1178 int pci_dev_present(const struct pci_device_id *ids); 1179 1180 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, 1181 int where, u8 *val); 1182 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, 1183 int where, u16 *val); 1184 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn, 1185 int where, u32 *val); 1186 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, 1187 int where, u8 val); 1188 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, 1189 int where, u16 val); 1190 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn, 1191 int where, u32 val); 1192 1193 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn, 1194 int where, int size, u32 *val); 1195 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn, 1196 int where, int size, u32 val); 1197 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn, 1198 int where, int size, u32 *val); 1199 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn, 1200 int where, int size, u32 val); 1201 1202 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops); 1203 1204 int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val); 1205 int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val); 1206 int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val); 1207 int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val); 1208 int pci_write_config_word(const struct pci_dev *dev, int where, u16 val); 1209 int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val); 1210 1211 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val); 1212 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val); 1213 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val); 1214 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val); 1215 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos, 1216 u16 clear, u16 set); 1217 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos, 1218 u32 clear, u32 set); 1219 1220 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos, 1221 u16 set) 1222 { 1223 return pcie_capability_clear_and_set_word(dev, pos, 0, set); 1224 } 1225 1226 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos, 1227 u32 set) 1228 { 1229 return pcie_capability_clear_and_set_dword(dev, pos, 0, set); 1230 } 1231 1232 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos, 1233 u16 clear) 1234 { 1235 return pcie_capability_clear_and_set_word(dev, pos, clear, 0); 1236 } 1237 1238 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos, 1239 u32 clear) 1240 { 1241 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0); 1242 } 1243 1244 /* User-space driven config access */ 1245 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val); 1246 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val); 1247 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val); 1248 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val); 1249 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val); 1250 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val); 1251 1252 int __must_check pci_enable_device(struct pci_dev *dev); 1253 int __must_check pci_enable_device_io(struct pci_dev *dev); 1254 int __must_check pci_enable_device_mem(struct pci_dev *dev); 1255 int __must_check pci_reenable_device(struct pci_dev *); 1256 int __must_check pcim_enable_device(struct pci_dev *pdev); 1257 void pcim_pin_device(struct pci_dev *pdev); 1258 1259 static inline bool pci_intx_mask_supported(struct pci_dev *pdev) 1260 { 1261 /* 1262 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is 1263 * writable and no quirk has marked the feature broken. 1264 */ 1265 return !pdev->broken_intx_masking; 1266 } 1267 1268 static inline int pci_is_enabled(struct pci_dev *pdev) 1269 { 1270 return (atomic_read(&pdev->enable_cnt) > 0); 1271 } 1272 1273 static inline int pci_is_managed(struct pci_dev *pdev) 1274 { 1275 return pdev->is_managed; 1276 } 1277 1278 void pci_disable_device(struct pci_dev *dev); 1279 1280 extern unsigned int pcibios_max_latency; 1281 void pci_set_master(struct pci_dev *dev); 1282 void pci_clear_master(struct pci_dev *dev); 1283 1284 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state); 1285 int pci_set_cacheline_size(struct pci_dev *dev); 1286 int __must_check pci_set_mwi(struct pci_dev *dev); 1287 int __must_check pcim_set_mwi(struct pci_dev *dev); 1288 int pci_try_set_mwi(struct pci_dev *dev); 1289 void pci_clear_mwi(struct pci_dev *dev); 1290 void pci_disable_parity(struct pci_dev *dev); 1291 void pci_intx(struct pci_dev *dev, int enable); 1292 bool pci_check_and_mask_intx(struct pci_dev *dev); 1293 bool pci_check_and_unmask_intx(struct pci_dev *dev); 1294 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask); 1295 int pci_wait_for_pending_transaction(struct pci_dev *dev); 1296 int pcix_get_max_mmrbc(struct pci_dev *dev); 1297 int pcix_get_mmrbc(struct pci_dev *dev); 1298 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc); 1299 int pcie_get_readrq(struct pci_dev *dev); 1300 int pcie_set_readrq(struct pci_dev *dev, int rq); 1301 int pcie_get_mps(struct pci_dev *dev); 1302 int pcie_set_mps(struct pci_dev *dev, int mps); 1303 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev, 1304 enum pci_bus_speed *speed, 1305 enum pcie_link_width *width); 1306 void pcie_print_link_status(struct pci_dev *dev); 1307 int pcie_reset_flr(struct pci_dev *dev, bool probe); 1308 int pcie_flr(struct pci_dev *dev); 1309 int __pci_reset_function_locked(struct pci_dev *dev); 1310 int pci_reset_function(struct pci_dev *dev); 1311 int pci_reset_function_locked(struct pci_dev *dev); 1312 int pci_try_reset_function(struct pci_dev *dev); 1313 int pci_probe_reset_slot(struct pci_slot *slot); 1314 int pci_probe_reset_bus(struct pci_bus *bus); 1315 int pci_reset_bus(struct pci_dev *dev); 1316 void pci_reset_secondary_bus(struct pci_dev *dev); 1317 void pcibios_reset_secondary_bus(struct pci_dev *dev); 1318 void pci_update_resource(struct pci_dev *dev, int resno); 1319 int __must_check pci_assign_resource(struct pci_dev *dev, int i); 1320 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align); 1321 void pci_release_resource(struct pci_dev *dev, int resno); 1322 static inline int pci_rebar_bytes_to_size(u64 bytes) 1323 { 1324 bytes = roundup_pow_of_two(bytes); 1325 1326 /* Return BAR size as defined in the resizable BAR specification */ 1327 return max(ilog2(bytes), 20) - 20; 1328 } 1329 1330 u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar); 1331 int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size); 1332 int pci_select_bars(struct pci_dev *dev, unsigned long flags); 1333 bool pci_device_is_present(struct pci_dev *pdev); 1334 void pci_ignore_hotplug(struct pci_dev *dev); 1335 struct pci_dev *pci_real_dma_dev(struct pci_dev *dev); 1336 int pci_status_get_and_clear_errors(struct pci_dev *pdev); 1337 1338 int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr, 1339 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id, 1340 const char *fmt, ...); 1341 void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id); 1342 1343 /* ROM control related routines */ 1344 int pci_enable_rom(struct pci_dev *pdev); 1345 void pci_disable_rom(struct pci_dev *pdev); 1346 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size); 1347 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom); 1348 1349 /* Power management related routines */ 1350 int pci_save_state(struct pci_dev *dev); 1351 void pci_restore_state(struct pci_dev *dev); 1352 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev); 1353 int pci_load_saved_state(struct pci_dev *dev, 1354 struct pci_saved_state *state); 1355 int pci_load_and_free_saved_state(struct pci_dev *dev, 1356 struct pci_saved_state **state); 1357 int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state); 1358 int pci_set_power_state(struct pci_dev *dev, pci_power_t state); 1359 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state); 1360 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state); 1361 void pci_pme_active(struct pci_dev *dev, bool enable); 1362 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable); 1363 int pci_wake_from_d3(struct pci_dev *dev, bool enable); 1364 int pci_prepare_to_sleep(struct pci_dev *dev); 1365 int pci_back_from_sleep(struct pci_dev *dev); 1366 bool pci_dev_run_wake(struct pci_dev *dev); 1367 void pci_d3cold_enable(struct pci_dev *dev); 1368 void pci_d3cold_disable(struct pci_dev *dev); 1369 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev); 1370 void pci_resume_bus(struct pci_bus *bus); 1371 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state); 1372 1373 /* For use by arch with custom probe code */ 1374 void set_pcie_port_type(struct pci_dev *pdev); 1375 void set_pcie_hotplug_bridge(struct pci_dev *pdev); 1376 1377 /* Functions for PCI Hotplug drivers to use */ 1378 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge); 1379 unsigned int pci_rescan_bus(struct pci_bus *bus); 1380 void pci_lock_rescan_remove(void); 1381 void pci_unlock_rescan_remove(void); 1382 1383 /* Vital Product Data routines */ 1384 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf); 1385 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); 1386 ssize_t pci_read_vpd_any(struct pci_dev *dev, loff_t pos, size_t count, void *buf); 1387 ssize_t pci_write_vpd_any(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); 1388 1389 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */ 1390 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx); 1391 void pci_bus_assign_resources(const struct pci_bus *bus); 1392 void pci_bus_claim_resources(struct pci_bus *bus); 1393 void pci_bus_size_bridges(struct pci_bus *bus); 1394 int pci_claim_resource(struct pci_dev *, int); 1395 int pci_claim_bridge_resource(struct pci_dev *bridge, int i); 1396 void pci_assign_unassigned_resources(void); 1397 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge); 1398 void pci_assign_unassigned_bus_resources(struct pci_bus *bus); 1399 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus); 1400 int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type); 1401 void pdev_enable_device(struct pci_dev *); 1402 int pci_enable_resources(struct pci_dev *, int mask); 1403 void pci_assign_irq(struct pci_dev *dev); 1404 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res); 1405 #define HAVE_PCI_REQ_REGIONS 2 1406 int __must_check pci_request_regions(struct pci_dev *, const char *); 1407 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *); 1408 void pci_release_regions(struct pci_dev *); 1409 int __must_check pci_request_region(struct pci_dev *, int, const char *); 1410 void pci_release_region(struct pci_dev *, int); 1411 int pci_request_selected_regions(struct pci_dev *, int, const char *); 1412 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *); 1413 void pci_release_selected_regions(struct pci_dev *, int); 1414 1415 static inline __must_check struct resource * 1416 pci_request_config_region_exclusive(struct pci_dev *pdev, unsigned int offset, 1417 unsigned int len, const char *name) 1418 { 1419 return __request_region(&pdev->driver_exclusive_resource, offset, len, 1420 name, IORESOURCE_EXCLUSIVE); 1421 } 1422 1423 static inline void pci_release_config_region(struct pci_dev *pdev, 1424 unsigned int offset, 1425 unsigned int len) 1426 { 1427 __release_region(&pdev->driver_exclusive_resource, offset, len); 1428 } 1429 1430 /* drivers/pci/bus.c */ 1431 void pci_add_resource(struct list_head *resources, struct resource *res); 1432 void pci_add_resource_offset(struct list_head *resources, struct resource *res, 1433 resource_size_t offset); 1434 void pci_free_resource_list(struct list_head *resources); 1435 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, 1436 unsigned int flags); 1437 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n); 1438 void pci_bus_remove_resources(struct pci_bus *bus); 1439 int devm_request_pci_bus_resources(struct device *dev, 1440 struct list_head *resources); 1441 1442 /* Temporary until new and working PCI SBR API in place */ 1443 int pci_bridge_secondary_bus_reset(struct pci_dev *dev); 1444 1445 #define pci_bus_for_each_resource(bus, res, i) \ 1446 for (i = 0; \ 1447 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \ 1448 i++) 1449 1450 int __must_check pci_bus_alloc_resource(struct pci_bus *bus, 1451 struct resource *res, resource_size_t size, 1452 resource_size_t align, resource_size_t min, 1453 unsigned long type_mask, 1454 resource_size_t (*alignf)(void *, 1455 const struct resource *, 1456 resource_size_t, 1457 resource_size_t), 1458 void *alignf_data); 1459 1460 1461 int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr, 1462 resource_size_t size); 1463 unsigned long pci_address_to_pio(phys_addr_t addr); 1464 phys_addr_t pci_pio_to_address(unsigned long pio); 1465 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr); 1466 int devm_pci_remap_iospace(struct device *dev, const struct resource *res, 1467 phys_addr_t phys_addr); 1468 void pci_unmap_iospace(struct resource *res); 1469 void __iomem *devm_pci_remap_cfgspace(struct device *dev, 1470 resource_size_t offset, 1471 resource_size_t size); 1472 void __iomem *devm_pci_remap_cfg_resource(struct device *dev, 1473 struct resource *res); 1474 1475 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar) 1476 { 1477 struct pci_bus_region region; 1478 1479 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]); 1480 return region.start; 1481 } 1482 1483 /* Proper probing supporting hot-pluggable devices */ 1484 int __must_check __pci_register_driver(struct pci_driver *, struct module *, 1485 const char *mod_name); 1486 1487 /* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */ 1488 #define pci_register_driver(driver) \ 1489 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME) 1490 1491 void pci_unregister_driver(struct pci_driver *dev); 1492 1493 /** 1494 * module_pci_driver() - Helper macro for registering a PCI driver 1495 * @__pci_driver: pci_driver struct 1496 * 1497 * Helper macro for PCI drivers which do not do anything special in module 1498 * init/exit. This eliminates a lot of boilerplate. Each module may only 1499 * use this macro once, and calling it replaces module_init() and module_exit() 1500 */ 1501 #define module_pci_driver(__pci_driver) \ 1502 module_driver(__pci_driver, pci_register_driver, pci_unregister_driver) 1503 1504 /** 1505 * builtin_pci_driver() - Helper macro for registering a PCI driver 1506 * @__pci_driver: pci_driver struct 1507 * 1508 * Helper macro for PCI drivers which do not do anything special in their 1509 * init code. This eliminates a lot of boilerplate. Each driver may only 1510 * use this macro once, and calling it replaces device_initcall(...) 1511 */ 1512 #define builtin_pci_driver(__pci_driver) \ 1513 builtin_driver(__pci_driver, pci_register_driver) 1514 1515 struct pci_driver *pci_dev_driver(const struct pci_dev *dev); 1516 int pci_add_dynid(struct pci_driver *drv, 1517 unsigned int vendor, unsigned int device, 1518 unsigned int subvendor, unsigned int subdevice, 1519 unsigned int class, unsigned int class_mask, 1520 unsigned long driver_data); 1521 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, 1522 struct pci_dev *dev); 1523 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, 1524 int pass); 1525 1526 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *), 1527 void *userdata); 1528 int pci_cfg_space_size(struct pci_dev *dev); 1529 unsigned char pci_bus_max_busnr(struct pci_bus *bus); 1530 void pci_setup_bridge(struct pci_bus *bus); 1531 resource_size_t pcibios_window_alignment(struct pci_bus *bus, 1532 unsigned long type); 1533 1534 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0) 1535 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1) 1536 1537 int pci_set_vga_state(struct pci_dev *pdev, bool decode, 1538 unsigned int command_bits, u32 flags); 1539 1540 /* 1541 * Virtual interrupts allow for more interrupts to be allocated 1542 * than the device has interrupts for. These are not programmed 1543 * into the device's MSI-X table and must be handled by some 1544 * other driver means. 1545 */ 1546 #define PCI_IRQ_VIRTUAL (1 << 4) 1547 1548 #define PCI_IRQ_ALL_TYPES \ 1549 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX) 1550 1551 #include <linux/dmapool.h> 1552 1553 struct msix_entry { 1554 u32 vector; /* Kernel uses to write allocated vector */ 1555 u16 entry; /* Driver uses to specify entry, OS writes */ 1556 }; 1557 1558 #ifdef CONFIG_PCI_MSI 1559 int pci_msi_vec_count(struct pci_dev *dev); 1560 void pci_disable_msi(struct pci_dev *dev); 1561 int pci_msix_vec_count(struct pci_dev *dev); 1562 void pci_disable_msix(struct pci_dev *dev); 1563 void pci_restore_msi_state(struct pci_dev *dev); 1564 int pci_msi_enabled(void); 1565 int pci_enable_msi(struct pci_dev *dev); 1566 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 1567 int minvec, int maxvec); 1568 static inline int pci_enable_msix_exact(struct pci_dev *dev, 1569 struct msix_entry *entries, int nvec) 1570 { 1571 int rc = pci_enable_msix_range(dev, entries, nvec, nvec); 1572 if (rc < 0) 1573 return rc; 1574 return 0; 1575 } 1576 int pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, 1577 unsigned int max_vecs, unsigned int flags); 1578 int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 1579 unsigned int max_vecs, unsigned int flags, 1580 struct irq_affinity *affd); 1581 1582 bool pci_msix_can_alloc_dyn(struct pci_dev *dev); 1583 struct msi_map pci_msix_alloc_irq_at(struct pci_dev *dev, unsigned int index, 1584 const struct irq_affinity_desc *affdesc); 1585 void pci_msix_free_irq(struct pci_dev *pdev, struct msi_map map); 1586 1587 void pci_free_irq_vectors(struct pci_dev *dev); 1588 int pci_irq_vector(struct pci_dev *dev, unsigned int nr); 1589 const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec); 1590 1591 #else 1592 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1593 static inline void pci_disable_msi(struct pci_dev *dev) { } 1594 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1595 static inline void pci_disable_msix(struct pci_dev *dev) { } 1596 static inline void pci_restore_msi_state(struct pci_dev *dev) { } 1597 static inline int pci_msi_enabled(void) { return 0; } 1598 static inline int pci_enable_msi(struct pci_dev *dev) 1599 { return -ENOSYS; } 1600 static inline int pci_enable_msix_range(struct pci_dev *dev, 1601 struct msix_entry *entries, int minvec, int maxvec) 1602 { return -ENOSYS; } 1603 static inline int pci_enable_msix_exact(struct pci_dev *dev, 1604 struct msix_entry *entries, int nvec) 1605 { return -ENOSYS; } 1606 1607 static inline int 1608 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 1609 unsigned int max_vecs, unsigned int flags, 1610 struct irq_affinity *aff_desc) 1611 { 1612 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq) 1613 return 1; 1614 return -ENOSPC; 1615 } 1616 static inline int 1617 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, 1618 unsigned int max_vecs, unsigned int flags) 1619 { 1620 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, 1621 flags, NULL); 1622 } 1623 1624 static inline void pci_free_irq_vectors(struct pci_dev *dev) 1625 { 1626 } 1627 1628 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr) 1629 { 1630 if (WARN_ON_ONCE(nr > 0)) 1631 return -EINVAL; 1632 return dev->irq; 1633 } 1634 static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, 1635 int vec) 1636 { 1637 return cpu_possible_mask; 1638 } 1639 #endif 1640 1641 /** 1642 * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq 1643 * @d: the INTx IRQ domain 1644 * @node: the DT node for the device whose interrupt we're translating 1645 * @intspec: the interrupt specifier data from the DT 1646 * @intsize: the number of entries in @intspec 1647 * @out_hwirq: pointer at which to write the hwirq number 1648 * @out_type: pointer at which to write the interrupt type 1649 * 1650 * Translate a PCI INTx interrupt number from device tree in the range 1-4, as 1651 * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range 1652 * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the 1653 * INTx value to obtain the hwirq number. 1654 * 1655 * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range. 1656 */ 1657 static inline int pci_irqd_intx_xlate(struct irq_domain *d, 1658 struct device_node *node, 1659 const u32 *intspec, 1660 unsigned int intsize, 1661 unsigned long *out_hwirq, 1662 unsigned int *out_type) 1663 { 1664 const u32 intx = intspec[0]; 1665 1666 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD) 1667 return -EINVAL; 1668 1669 *out_hwirq = intx - PCI_INTERRUPT_INTA; 1670 return 0; 1671 } 1672 1673 #ifdef CONFIG_PCIEPORTBUS 1674 extern bool pcie_ports_disabled; 1675 extern bool pcie_ports_native; 1676 #else 1677 #define pcie_ports_disabled true 1678 #define pcie_ports_native false 1679 #endif 1680 1681 #define PCIE_LINK_STATE_L0S BIT(0) 1682 #define PCIE_LINK_STATE_L1 BIT(1) 1683 #define PCIE_LINK_STATE_CLKPM BIT(2) 1684 #define PCIE_LINK_STATE_L1_1 BIT(3) 1685 #define PCIE_LINK_STATE_L1_2 BIT(4) 1686 #define PCIE_LINK_STATE_L1_1_PCIPM BIT(5) 1687 #define PCIE_LINK_STATE_L1_2_PCIPM BIT(6) 1688 1689 #ifdef CONFIG_PCIEASPM 1690 int pci_disable_link_state(struct pci_dev *pdev, int state); 1691 int pci_disable_link_state_locked(struct pci_dev *pdev, int state); 1692 void pcie_no_aspm(void); 1693 bool pcie_aspm_support_enabled(void); 1694 bool pcie_aspm_enabled(struct pci_dev *pdev); 1695 #else 1696 static inline int pci_disable_link_state(struct pci_dev *pdev, int state) 1697 { return 0; } 1698 static inline int pci_disable_link_state_locked(struct pci_dev *pdev, int state) 1699 { return 0; } 1700 static inline void pcie_no_aspm(void) { } 1701 static inline bool pcie_aspm_support_enabled(void) { return false; } 1702 static inline bool pcie_aspm_enabled(struct pci_dev *pdev) { return false; } 1703 #endif 1704 1705 #ifdef CONFIG_PCIEAER 1706 bool pci_aer_available(void); 1707 #else 1708 static inline bool pci_aer_available(void) { return false; } 1709 #endif 1710 1711 bool pci_ats_disabled(void); 1712 1713 #ifdef CONFIG_PCIE_PTM 1714 int pci_enable_ptm(struct pci_dev *dev, u8 *granularity); 1715 void pci_disable_ptm(struct pci_dev *dev); 1716 bool pcie_ptm_enabled(struct pci_dev *dev); 1717 #else 1718 static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity) 1719 { return -EINVAL; } 1720 static inline void pci_disable_ptm(struct pci_dev *dev) { } 1721 static inline bool pcie_ptm_enabled(struct pci_dev *dev) 1722 { return false; } 1723 #endif 1724 1725 void pci_cfg_access_lock(struct pci_dev *dev); 1726 bool pci_cfg_access_trylock(struct pci_dev *dev); 1727 void pci_cfg_access_unlock(struct pci_dev *dev); 1728 1729 void pci_dev_lock(struct pci_dev *dev); 1730 int pci_dev_trylock(struct pci_dev *dev); 1731 void pci_dev_unlock(struct pci_dev *dev); 1732 1733 /* 1734 * PCI domain support. Sometimes called PCI segment (eg by ACPI), 1735 * a PCI domain is defined to be a set of PCI buses which share 1736 * configuration space. 1737 */ 1738 #ifdef CONFIG_PCI_DOMAINS 1739 extern int pci_domains_supported; 1740 #else 1741 enum { pci_domains_supported = 0 }; 1742 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 1743 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; } 1744 #endif /* CONFIG_PCI_DOMAINS */ 1745 1746 /* 1747 * Generic implementation for PCI domain support. If your 1748 * architecture does not need custom management of PCI 1749 * domains then this implementation will be used 1750 */ 1751 #ifdef CONFIG_PCI_DOMAINS_GENERIC 1752 static inline int pci_domain_nr(struct pci_bus *bus) 1753 { 1754 return bus->domain_nr; 1755 } 1756 #ifdef CONFIG_ACPI 1757 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus); 1758 #else 1759 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus) 1760 { return 0; } 1761 #endif 1762 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent); 1763 #endif 1764 1765 /* Some architectures require additional setup to direct VGA traffic */ 1766 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode, 1767 unsigned int command_bits, u32 flags); 1768 void pci_register_set_vga_state(arch_set_vga_state_t func); 1769 1770 static inline int 1771 pci_request_io_regions(struct pci_dev *pdev, const char *name) 1772 { 1773 return pci_request_selected_regions(pdev, 1774 pci_select_bars(pdev, IORESOURCE_IO), name); 1775 } 1776 1777 static inline void 1778 pci_release_io_regions(struct pci_dev *pdev) 1779 { 1780 return pci_release_selected_regions(pdev, 1781 pci_select_bars(pdev, IORESOURCE_IO)); 1782 } 1783 1784 static inline int 1785 pci_request_mem_regions(struct pci_dev *pdev, const char *name) 1786 { 1787 return pci_request_selected_regions(pdev, 1788 pci_select_bars(pdev, IORESOURCE_MEM), name); 1789 } 1790 1791 static inline void 1792 pci_release_mem_regions(struct pci_dev *pdev) 1793 { 1794 return pci_release_selected_regions(pdev, 1795 pci_select_bars(pdev, IORESOURCE_MEM)); 1796 } 1797 1798 #else /* CONFIG_PCI is not enabled */ 1799 1800 static inline void pci_set_flags(int flags) { } 1801 static inline void pci_add_flags(int flags) { } 1802 static inline void pci_clear_flags(int flags) { } 1803 static inline int pci_has_flag(int flag) { return 0; } 1804 1805 /* 1806 * If the system does not have PCI, clearly these return errors. Define 1807 * these as simple inline functions to avoid hair in drivers. 1808 */ 1809 #define _PCI_NOP(o, s, t) \ 1810 static inline int pci_##o##_config_##s(struct pci_dev *dev, \ 1811 int where, t val) \ 1812 { return PCIBIOS_FUNC_NOT_SUPPORTED; } 1813 1814 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \ 1815 _PCI_NOP(o, word, u16 x) \ 1816 _PCI_NOP(o, dword, u32 x) 1817 _PCI_NOP_ALL(read, *) 1818 _PCI_NOP_ALL(write,) 1819 1820 static inline struct pci_dev *pci_get_device(unsigned int vendor, 1821 unsigned int device, 1822 struct pci_dev *from) 1823 { return NULL; } 1824 1825 static inline struct pci_dev *pci_get_subsys(unsigned int vendor, 1826 unsigned int device, 1827 unsigned int ss_vendor, 1828 unsigned int ss_device, 1829 struct pci_dev *from) 1830 { return NULL; } 1831 1832 static inline struct pci_dev *pci_get_class(unsigned int class, 1833 struct pci_dev *from) 1834 { return NULL; } 1835 1836 1837 static inline int pci_dev_present(const struct pci_device_id *ids) 1838 { return 0; } 1839 1840 #define no_pci_devices() (1) 1841 #define pci_dev_put(dev) do { } while (0) 1842 1843 static inline void pci_set_master(struct pci_dev *dev) { } 1844 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; } 1845 static inline void pci_disable_device(struct pci_dev *dev) { } 1846 static inline int pcim_enable_device(struct pci_dev *pdev) { return -EIO; } 1847 static inline int pci_assign_resource(struct pci_dev *dev, int i) 1848 { return -EBUSY; } 1849 static inline int __must_check __pci_register_driver(struct pci_driver *drv, 1850 struct module *owner, 1851 const char *mod_name) 1852 { return 0; } 1853 static inline int pci_register_driver(struct pci_driver *drv) 1854 { return 0; } 1855 static inline void pci_unregister_driver(struct pci_driver *drv) { } 1856 static inline u8 pci_find_capability(struct pci_dev *dev, int cap) 1857 { return 0; } 1858 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post, 1859 int cap) 1860 { return 0; } 1861 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap) 1862 { return 0; } 1863 1864 static inline u64 pci_get_dsn(struct pci_dev *dev) 1865 { return 0; } 1866 1867 /* Power management related routines */ 1868 static inline int pci_save_state(struct pci_dev *dev) { return 0; } 1869 static inline void pci_restore_state(struct pci_dev *dev) { } 1870 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) 1871 { return 0; } 1872 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable) 1873 { return 0; } 1874 static inline pci_power_t pci_choose_state(struct pci_dev *dev, 1875 pm_message_t state) 1876 { return PCI_D0; } 1877 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, 1878 int enable) 1879 { return 0; } 1880 1881 static inline struct resource *pci_find_resource(struct pci_dev *dev, 1882 struct resource *res) 1883 { return NULL; } 1884 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name) 1885 { return -EIO; } 1886 static inline void pci_release_regions(struct pci_dev *dev) { } 1887 1888 static inline int pci_register_io_range(struct fwnode_handle *fwnode, 1889 phys_addr_t addr, resource_size_t size) 1890 { return -EINVAL; } 1891 1892 static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; } 1893 1894 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from) 1895 { return NULL; } 1896 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus, 1897 unsigned int devfn) 1898 { return NULL; } 1899 static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain, 1900 unsigned int bus, unsigned int devfn) 1901 { return NULL; } 1902 1903 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 1904 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; } 1905 1906 #define dev_is_pci(d) (false) 1907 #define dev_is_pf(d) (false) 1908 static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags) 1909 { return false; } 1910 static inline int pci_irqd_intx_xlate(struct irq_domain *d, 1911 struct device_node *node, 1912 const u32 *intspec, 1913 unsigned int intsize, 1914 unsigned long *out_hwirq, 1915 unsigned int *out_type) 1916 { return -EINVAL; } 1917 1918 static inline const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, 1919 struct pci_dev *dev) 1920 { return NULL; } 1921 static inline bool pci_ats_disabled(void) { return true; } 1922 1923 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr) 1924 { 1925 return -EINVAL; 1926 } 1927 1928 static inline int 1929 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 1930 unsigned int max_vecs, unsigned int flags, 1931 struct irq_affinity *aff_desc) 1932 { 1933 return -ENOSPC; 1934 } 1935 static inline int 1936 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, 1937 unsigned int max_vecs, unsigned int flags) 1938 { 1939 return -ENOSPC; 1940 } 1941 #endif /* CONFIG_PCI */ 1942 1943 /* Include architecture-dependent settings and functions */ 1944 1945 #include <asm/pci.h> 1946 1947 /* 1948 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff 1949 * is expected to be an offset within that region. 1950 * 1951 */ 1952 int pci_mmap_resource_range(struct pci_dev *dev, int bar, 1953 struct vm_area_struct *vma, 1954 enum pci_mmap_state mmap_state, int write_combine); 1955 1956 #ifndef arch_can_pci_mmap_wc 1957 #define arch_can_pci_mmap_wc() 0 1958 #endif 1959 1960 #ifndef arch_can_pci_mmap_io 1961 #define arch_can_pci_mmap_io() 0 1962 #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL) 1963 #else 1964 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma); 1965 #endif 1966 1967 #ifndef pci_root_bus_fwnode 1968 #define pci_root_bus_fwnode(bus) NULL 1969 #endif 1970 1971 /* 1972 * These helpers provide future and backwards compatibility 1973 * for accessing popular PCI BAR info 1974 */ 1975 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) 1976 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end) 1977 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags) 1978 #define pci_resource_len(dev,bar) \ 1979 ((pci_resource_end((dev), (bar)) == 0) ? 0 : \ 1980 \ 1981 (pci_resource_end((dev), (bar)) - \ 1982 pci_resource_start((dev), (bar)) + 1)) 1983 1984 /* 1985 * Similar to the helpers above, these manipulate per-pci_dev 1986 * driver-specific data. They are really just a wrapper around 1987 * the generic device structure functions of these calls. 1988 */ 1989 static inline void *pci_get_drvdata(struct pci_dev *pdev) 1990 { 1991 return dev_get_drvdata(&pdev->dev); 1992 } 1993 1994 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data) 1995 { 1996 dev_set_drvdata(&pdev->dev, data); 1997 } 1998 1999 static inline const char *pci_name(const struct pci_dev *pdev) 2000 { 2001 return dev_name(&pdev->dev); 2002 } 2003 2004 void pci_resource_to_user(const struct pci_dev *dev, int bar, 2005 const struct resource *rsrc, 2006 resource_size_t *start, resource_size_t *end); 2007 2008 /* 2009 * The world is not perfect and supplies us with broken PCI devices. 2010 * For at least a part of these bugs we need a work-around, so both 2011 * generic (drivers/pci/quirks.c) and per-architecture code can define 2012 * fixup hooks to be called for particular buggy devices. 2013 */ 2014 2015 struct pci_fixup { 2016 u16 vendor; /* Or PCI_ANY_ID */ 2017 u16 device; /* Or PCI_ANY_ID */ 2018 u32 class; /* Or PCI_ANY_ID */ 2019 unsigned int class_shift; /* should be 0, 8, 16 */ 2020 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS 2021 int hook_offset; 2022 #else 2023 void (*hook)(struct pci_dev *dev); 2024 #endif 2025 }; 2026 2027 enum pci_fixup_pass { 2028 pci_fixup_early, /* Before probing BARs */ 2029 pci_fixup_header, /* After reading configuration header */ 2030 pci_fixup_final, /* Final phase of device fixups */ 2031 pci_fixup_enable, /* pci_enable_device() time */ 2032 pci_fixup_resume, /* pci_device_resume() */ 2033 pci_fixup_suspend, /* pci_device_suspend() */ 2034 pci_fixup_resume_early, /* pci_device_resume_early() */ 2035 pci_fixup_suspend_late, /* pci_device_suspend_late() */ 2036 }; 2037 2038 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS 2039 #define ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2040 class_shift, hook) \ 2041 __ADDRESSABLE(hook) \ 2042 asm(".section " #sec ", \"a\" \n" \ 2043 ".balign 16 \n" \ 2044 ".short " #vendor ", " #device " \n" \ 2045 ".long " #class ", " #class_shift " \n" \ 2046 ".long " #hook " - . \n" \ 2047 ".previous \n"); 2048 2049 /* 2050 * Clang's LTO may rename static functions in C, but has no way to 2051 * handle such renamings when referenced from inline asm. To work 2052 * around this, create global C stubs for these cases. 2053 */ 2054 #ifdef CONFIG_LTO_CLANG 2055 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2056 class_shift, hook, stub) \ 2057 void stub(struct pci_dev *dev); \ 2058 void stub(struct pci_dev *dev) \ 2059 { \ 2060 hook(dev); \ 2061 } \ 2062 ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2063 class_shift, stub) 2064 #else 2065 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2066 class_shift, hook, stub) \ 2067 ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2068 class_shift, hook) 2069 #endif 2070 2071 #define DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2072 class_shift, hook) \ 2073 __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2074 class_shift, hook, __UNIQUE_ID(hook)) 2075 #else 2076 /* Anonymous variables would be nice... */ 2077 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \ 2078 class_shift, hook) \ 2079 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \ 2080 __attribute__((__section__(#section), aligned((sizeof(void *))))) \ 2081 = { vendor, device, class, class_shift, hook }; 2082 #endif 2083 2084 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \ 2085 class_shift, hook) \ 2086 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 2087 hook, vendor, device, class, class_shift, hook) 2088 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \ 2089 class_shift, hook) \ 2090 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 2091 hook, vendor, device, class, class_shift, hook) 2092 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \ 2093 class_shift, hook) \ 2094 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 2095 hook, vendor, device, class, class_shift, hook) 2096 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \ 2097 class_shift, hook) \ 2098 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 2099 hook, vendor, device, class, class_shift, hook) 2100 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \ 2101 class_shift, hook) \ 2102 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 2103 resume##hook, vendor, device, class, class_shift, hook) 2104 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \ 2105 class_shift, hook) \ 2106 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 2107 resume_early##hook, vendor, device, class, class_shift, hook) 2108 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \ 2109 class_shift, hook) \ 2110 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 2111 suspend##hook, vendor, device, class, class_shift, hook) 2112 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \ 2113 class_shift, hook) \ 2114 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 2115 suspend_late##hook, vendor, device, class, class_shift, hook) 2116 2117 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \ 2118 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 2119 hook, vendor, device, PCI_ANY_ID, 0, hook) 2120 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \ 2121 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 2122 hook, vendor, device, PCI_ANY_ID, 0, hook) 2123 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \ 2124 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 2125 hook, vendor, device, PCI_ANY_ID, 0, hook) 2126 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \ 2127 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 2128 hook, vendor, device, PCI_ANY_ID, 0, hook) 2129 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \ 2130 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 2131 resume##hook, vendor, device, PCI_ANY_ID, 0, hook) 2132 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \ 2133 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 2134 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook) 2135 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \ 2136 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 2137 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook) 2138 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \ 2139 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 2140 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook) 2141 2142 #ifdef CONFIG_PCI_QUIRKS 2143 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev); 2144 #else 2145 static inline void pci_fixup_device(enum pci_fixup_pass pass, 2146 struct pci_dev *dev) { } 2147 #endif 2148 2149 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen); 2150 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr); 2151 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev); 2152 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name); 2153 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask, 2154 const char *name); 2155 void pcim_iounmap_regions(struct pci_dev *pdev, int mask); 2156 2157 extern int pci_pci_problems; 2158 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */ 2159 #define PCIPCI_TRITON 2 2160 #define PCIPCI_NATOMA 4 2161 #define PCIPCI_VIAETBF 8 2162 #define PCIPCI_VSFX 16 2163 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */ 2164 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */ 2165 2166 extern unsigned long pci_cardbus_io_size; 2167 extern unsigned long pci_cardbus_mem_size; 2168 extern u8 pci_dfl_cache_line_size; 2169 extern u8 pci_cache_line_size; 2170 2171 /* Architecture-specific versions may override these (weak) */ 2172 void pcibios_disable_device(struct pci_dev *dev); 2173 void pcibios_set_master(struct pci_dev *dev); 2174 int pcibios_set_pcie_reset_state(struct pci_dev *dev, 2175 enum pcie_reset_state state); 2176 int pcibios_device_add(struct pci_dev *dev); 2177 void pcibios_release_device(struct pci_dev *dev); 2178 #ifdef CONFIG_PCI 2179 void pcibios_penalize_isa_irq(int irq, int active); 2180 #else 2181 static inline void pcibios_penalize_isa_irq(int irq, int active) {} 2182 #endif 2183 int pcibios_alloc_irq(struct pci_dev *dev); 2184 void pcibios_free_irq(struct pci_dev *dev); 2185 resource_size_t pcibios_default_alignment(void); 2186 2187 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG) 2188 void __init pci_mmcfg_early_init(void); 2189 void __init pci_mmcfg_late_init(void); 2190 #else 2191 static inline void pci_mmcfg_early_init(void) { } 2192 static inline void pci_mmcfg_late_init(void) { } 2193 #endif 2194 2195 int pci_ext_cfg_avail(void); 2196 2197 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar); 2198 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar); 2199 2200 #ifdef CONFIG_PCI_IOV 2201 int pci_iov_virtfn_bus(struct pci_dev *dev, int id); 2202 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id); 2203 int pci_iov_vf_id(struct pci_dev *dev); 2204 void *pci_iov_get_pf_drvdata(struct pci_dev *dev, struct pci_driver *pf_driver); 2205 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn); 2206 void pci_disable_sriov(struct pci_dev *dev); 2207 2208 int pci_iov_sysfs_link(struct pci_dev *dev, struct pci_dev *virtfn, int id); 2209 int pci_iov_add_virtfn(struct pci_dev *dev, int id); 2210 void pci_iov_remove_virtfn(struct pci_dev *dev, int id); 2211 int pci_num_vf(struct pci_dev *dev); 2212 int pci_vfs_assigned(struct pci_dev *dev); 2213 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs); 2214 int pci_sriov_get_totalvfs(struct pci_dev *dev); 2215 int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn); 2216 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno); 2217 void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe); 2218 2219 /* Arch may override these (weak) */ 2220 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs); 2221 int pcibios_sriov_disable(struct pci_dev *pdev); 2222 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno); 2223 #else 2224 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id) 2225 { 2226 return -ENOSYS; 2227 } 2228 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id) 2229 { 2230 return -ENOSYS; 2231 } 2232 2233 static inline int pci_iov_vf_id(struct pci_dev *dev) 2234 { 2235 return -ENOSYS; 2236 } 2237 2238 static inline void *pci_iov_get_pf_drvdata(struct pci_dev *dev, 2239 struct pci_driver *pf_driver) 2240 { 2241 return ERR_PTR(-EINVAL); 2242 } 2243 2244 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 2245 { return -ENODEV; } 2246 2247 static inline int pci_iov_sysfs_link(struct pci_dev *dev, 2248 struct pci_dev *virtfn, int id) 2249 { 2250 return -ENODEV; 2251 } 2252 static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id) 2253 { 2254 return -ENOSYS; 2255 } 2256 static inline void pci_iov_remove_virtfn(struct pci_dev *dev, 2257 int id) { } 2258 static inline void pci_disable_sriov(struct pci_dev *dev) { } 2259 static inline int pci_num_vf(struct pci_dev *dev) { return 0; } 2260 static inline int pci_vfs_assigned(struct pci_dev *dev) 2261 { return 0; } 2262 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs) 2263 { return 0; } 2264 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev) 2265 { return 0; } 2266 #define pci_sriov_configure_simple NULL 2267 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno) 2268 { return 0; } 2269 static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { } 2270 #endif 2271 2272 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE) 2273 void pci_hp_create_module_link(struct pci_slot *pci_slot); 2274 void pci_hp_remove_module_link(struct pci_slot *pci_slot); 2275 #endif 2276 2277 /** 2278 * pci_pcie_cap - get the saved PCIe capability offset 2279 * @dev: PCI device 2280 * 2281 * PCIe capability offset is calculated at PCI device initialization 2282 * time and saved in the data structure. This function returns saved 2283 * PCIe capability offset. Using this instead of pci_find_capability() 2284 * reduces unnecessary search in the PCI configuration space. If you 2285 * need to calculate PCIe capability offset from raw device for some 2286 * reasons, please use pci_find_capability() instead. 2287 */ 2288 static inline int pci_pcie_cap(struct pci_dev *dev) 2289 { 2290 return dev->pcie_cap; 2291 } 2292 2293 /** 2294 * pci_is_pcie - check if the PCI device is PCI Express capable 2295 * @dev: PCI device 2296 * 2297 * Returns: true if the PCI device is PCI Express capable, false otherwise. 2298 */ 2299 static inline bool pci_is_pcie(struct pci_dev *dev) 2300 { 2301 return pci_pcie_cap(dev); 2302 } 2303 2304 /** 2305 * pcie_caps_reg - get the PCIe Capabilities Register 2306 * @dev: PCI device 2307 */ 2308 static inline u16 pcie_caps_reg(const struct pci_dev *dev) 2309 { 2310 return dev->pcie_flags_reg; 2311 } 2312 2313 /** 2314 * pci_pcie_type - get the PCIe device/port type 2315 * @dev: PCI device 2316 */ 2317 static inline int pci_pcie_type(const struct pci_dev *dev) 2318 { 2319 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 2320 } 2321 2322 /** 2323 * pcie_find_root_port - Get the PCIe root port device 2324 * @dev: PCI device 2325 * 2326 * Traverse up the parent chain and return the PCIe Root Port PCI Device 2327 * for a given PCI/PCIe Device. 2328 */ 2329 static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev) 2330 { 2331 while (dev) { 2332 if (pci_is_pcie(dev) && 2333 pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) 2334 return dev; 2335 dev = pci_upstream_bridge(dev); 2336 } 2337 2338 return NULL; 2339 } 2340 2341 void pci_request_acs(void); 2342 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags); 2343 bool pci_acs_path_enabled(struct pci_dev *start, 2344 struct pci_dev *end, u16 acs_flags); 2345 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask); 2346 2347 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */ 2348 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT) 2349 2350 /* Large Resource Data Type Tag Item Names */ 2351 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */ 2352 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */ 2353 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */ 2354 2355 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING) 2356 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA) 2357 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA) 2358 2359 #define PCI_VPD_RO_KEYWORD_PARTNO "PN" 2360 #define PCI_VPD_RO_KEYWORD_SERIALNO "SN" 2361 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN" 2362 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0" 2363 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV" 2364 2365 /** 2366 * pci_vpd_alloc - Allocate buffer and read VPD into it 2367 * @dev: PCI device 2368 * @size: pointer to field where VPD length is returned 2369 * 2370 * Returns pointer to allocated buffer or an ERR_PTR in case of failure 2371 */ 2372 void *pci_vpd_alloc(struct pci_dev *dev, unsigned int *size); 2373 2374 /** 2375 * pci_vpd_find_id_string - Locate id string in VPD 2376 * @buf: Pointer to buffered VPD data 2377 * @len: The length of the buffer area in which to search 2378 * @size: Pointer to field where length of id string is returned 2379 * 2380 * Returns the index of the id string or -ENOENT if not found. 2381 */ 2382 int pci_vpd_find_id_string(const u8 *buf, unsigned int len, unsigned int *size); 2383 2384 /** 2385 * pci_vpd_find_ro_info_keyword - Locate info field keyword in VPD RO section 2386 * @buf: Pointer to buffered VPD data 2387 * @len: The length of the buffer area in which to search 2388 * @kw: The keyword to search for 2389 * @size: Pointer to field where length of found keyword data is returned 2390 * 2391 * Returns the index of the information field keyword data or -ENOENT if 2392 * not found. 2393 */ 2394 int pci_vpd_find_ro_info_keyword(const void *buf, unsigned int len, 2395 const char *kw, unsigned int *size); 2396 2397 /** 2398 * pci_vpd_check_csum - Check VPD checksum 2399 * @buf: Pointer to buffered VPD data 2400 * @len: VPD size 2401 * 2402 * Returns 1 if VPD has no checksum, otherwise 0 or an errno 2403 */ 2404 int pci_vpd_check_csum(const void *buf, unsigned int len); 2405 2406 /* PCI <-> OF binding helpers */ 2407 #ifdef CONFIG_OF 2408 struct device_node; 2409 struct irq_domain; 2410 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus); 2411 bool pci_host_of_has_msi_map(struct device *dev); 2412 2413 /* Arch may override this (weak) */ 2414 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus); 2415 2416 #else /* CONFIG_OF */ 2417 static inline struct irq_domain * 2418 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; } 2419 static inline bool pci_host_of_has_msi_map(struct device *dev) { return false; } 2420 #endif /* CONFIG_OF */ 2421 2422 static inline struct device_node * 2423 pci_device_to_OF_node(const struct pci_dev *pdev) 2424 { 2425 return pdev ? pdev->dev.of_node : NULL; 2426 } 2427 2428 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus) 2429 { 2430 return bus ? bus->dev.of_node : NULL; 2431 } 2432 2433 #ifdef CONFIG_ACPI 2434 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus); 2435 2436 void 2437 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *)); 2438 bool pci_pr3_present(struct pci_dev *pdev); 2439 #else 2440 static inline struct irq_domain * 2441 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; } 2442 static inline bool pci_pr3_present(struct pci_dev *pdev) { return false; } 2443 #endif 2444 2445 #ifdef CONFIG_EEH 2446 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev) 2447 { 2448 return pdev->dev.archdata.edev; 2449 } 2450 #endif 2451 2452 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from, unsigned nr_devfns); 2453 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2); 2454 int pci_for_each_dma_alias(struct pci_dev *pdev, 2455 int (*fn)(struct pci_dev *pdev, 2456 u16 alias, void *data), void *data); 2457 2458 /* Helper functions for operation of device flag */ 2459 static inline void pci_set_dev_assigned(struct pci_dev *pdev) 2460 { 2461 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED; 2462 } 2463 static inline void pci_clear_dev_assigned(struct pci_dev *pdev) 2464 { 2465 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED; 2466 } 2467 static inline bool pci_is_dev_assigned(struct pci_dev *pdev) 2468 { 2469 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED; 2470 } 2471 2472 /** 2473 * pci_ari_enabled - query ARI forwarding status 2474 * @bus: the PCI bus 2475 * 2476 * Returns true if ARI forwarding is enabled. 2477 */ 2478 static inline bool pci_ari_enabled(struct pci_bus *bus) 2479 { 2480 return bus->self && bus->self->ari_enabled; 2481 } 2482 2483 /** 2484 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain 2485 * @pdev: PCI device to check 2486 * 2487 * Walk upwards from @pdev and check for each encountered bridge if it's part 2488 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not 2489 * Thunderbolt-attached. (But rather soldered to the mainboard usually.) 2490 */ 2491 static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev) 2492 { 2493 struct pci_dev *parent = pdev; 2494 2495 if (pdev->is_thunderbolt) 2496 return true; 2497 2498 while ((parent = pci_upstream_bridge(parent))) 2499 if (parent->is_thunderbolt) 2500 return true; 2501 2502 return false; 2503 } 2504 2505 #if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH) 2506 void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type); 2507 #endif 2508 2509 struct msi_domain_template; 2510 2511 bool pci_create_ims_domain(struct pci_dev *pdev, const struct msi_domain_template *template, 2512 unsigned int hwsize, void *data); 2513 struct msi_map pci_ims_alloc_irq(struct pci_dev *pdev, union msi_instance_cookie *icookie, 2514 const struct irq_affinity_desc *affdesc); 2515 void pci_ims_free_irq(struct pci_dev *pdev, struct msi_map map); 2516 2517 #include <linux/dma-mapping.h> 2518 2519 #define pci_printk(level, pdev, fmt, arg...) \ 2520 dev_printk(level, &(pdev)->dev, fmt, ##arg) 2521 2522 #define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg) 2523 #define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg) 2524 #define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg) 2525 #define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg) 2526 #define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg) 2527 #define pci_warn_once(pdev, fmt, arg...) dev_warn_once(&(pdev)->dev, fmt, ##arg) 2528 #define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg) 2529 #define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg) 2530 #define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg) 2531 2532 #define pci_notice_ratelimited(pdev, fmt, arg...) \ 2533 dev_notice_ratelimited(&(pdev)->dev, fmt, ##arg) 2534 2535 #define pci_info_ratelimited(pdev, fmt, arg...) \ 2536 dev_info_ratelimited(&(pdev)->dev, fmt, ##arg) 2537 2538 #define pci_WARN(pdev, condition, fmt, arg...) \ 2539 WARN(condition, "%s %s: " fmt, \ 2540 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg) 2541 2542 #define pci_WARN_ONCE(pdev, condition, fmt, arg...) \ 2543 WARN_ONCE(condition, "%s %s: " fmt, \ 2544 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg) 2545 2546 #endif /* LINUX_PCI_H */ 2547