1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _LINUX_PGTABLE_H 3 #define _LINUX_PGTABLE_H 4 5 #include <linux/pfn.h> 6 #include <asm/pgtable.h> 7 8 #define PMD_ORDER (PMD_SHIFT - PAGE_SHIFT) 9 #define PUD_ORDER (PUD_SHIFT - PAGE_SHIFT) 10 11 #ifndef __ASSEMBLY__ 12 #ifdef CONFIG_MMU 13 14 #include <linux/mm_types.h> 15 #include <linux/bug.h> 16 #include <linux/errno.h> 17 #include <asm-generic/pgtable_uffd.h> 18 #include <linux/page_table_check.h> 19 20 #if 5 - defined(__PAGETABLE_P4D_FOLDED) - defined(__PAGETABLE_PUD_FOLDED) - \ 21 defined(__PAGETABLE_PMD_FOLDED) != CONFIG_PGTABLE_LEVELS 22 #error CONFIG_PGTABLE_LEVELS is not consistent with __PAGETABLE_{P4D,PUD,PMD}_FOLDED 23 #endif 24 25 /* 26 * On almost all architectures and configurations, 0 can be used as the 27 * upper ceiling to free_pgtables(): on many architectures it has the same 28 * effect as using TASK_SIZE. However, there is one configuration which 29 * must impose a more careful limit, to avoid freeing kernel pgtables. 30 */ 31 #ifndef USER_PGTABLES_CEILING 32 #define USER_PGTABLES_CEILING 0UL 33 #endif 34 35 /* 36 * This defines the first usable user address. Platforms 37 * can override its value with custom FIRST_USER_ADDRESS 38 * defined in their respective <asm/pgtable.h>. 39 */ 40 #ifndef FIRST_USER_ADDRESS 41 #define FIRST_USER_ADDRESS 0UL 42 #endif 43 44 /* 45 * This defines the generic helper for accessing PMD page 46 * table page. Although platforms can still override this 47 * via their respective <asm/pgtable.h>. 48 */ 49 #ifndef pmd_pgtable 50 #define pmd_pgtable(pmd) pmd_page(pmd) 51 #endif 52 53 /* 54 * A page table page can be thought of an array like this: pXd_t[PTRS_PER_PxD] 55 * 56 * The pXx_index() functions return the index of the entry in the page 57 * table page which would control the given virtual address 58 * 59 * As these functions may be used by the same code for different levels of 60 * the page table folding, they are always available, regardless of 61 * CONFIG_PGTABLE_LEVELS value. For the folded levels they simply return 0 62 * because in such cases PTRS_PER_PxD equals 1. 63 */ 64 65 static inline unsigned long pte_index(unsigned long address) 66 { 67 return (address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1); 68 } 69 70 #ifndef pmd_index 71 static inline unsigned long pmd_index(unsigned long address) 72 { 73 return (address >> PMD_SHIFT) & (PTRS_PER_PMD - 1); 74 } 75 #define pmd_index pmd_index 76 #endif 77 78 #ifndef pud_index 79 static inline unsigned long pud_index(unsigned long address) 80 { 81 return (address >> PUD_SHIFT) & (PTRS_PER_PUD - 1); 82 } 83 #define pud_index pud_index 84 #endif 85 86 #ifndef pgd_index 87 /* Must be a compile-time constant, so implement it as a macro */ 88 #define pgd_index(a) (((a) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)) 89 #endif 90 91 #ifndef pte_offset_kernel 92 static inline pte_t *pte_offset_kernel(pmd_t *pmd, unsigned long address) 93 { 94 return (pte_t *)pmd_page_vaddr(*pmd) + pte_index(address); 95 } 96 #define pte_offset_kernel pte_offset_kernel 97 #endif 98 99 #ifdef CONFIG_HIGHPTE 100 #define __pte_map(pmd, address) \ 101 ((pte_t *)kmap_local_page(pmd_page(*(pmd))) + pte_index((address))) 102 #define pte_unmap(pte) do { \ 103 kunmap_local((pte)); \ 104 rcu_read_unlock(); \ 105 } while (0) 106 #else 107 static inline pte_t *__pte_map(pmd_t *pmd, unsigned long address) 108 { 109 return pte_offset_kernel(pmd, address); 110 } 111 static inline void pte_unmap(pte_t *pte) 112 { 113 rcu_read_unlock(); 114 } 115 #endif 116 117 void pte_free_defer(struct mm_struct *mm, pgtable_t pgtable); 118 119 /* Find an entry in the second-level page table.. */ 120 #ifndef pmd_offset 121 static inline pmd_t *pmd_offset(pud_t *pud, unsigned long address) 122 { 123 return pud_pgtable(*pud) + pmd_index(address); 124 } 125 #define pmd_offset pmd_offset 126 #endif 127 128 #ifndef pud_offset 129 static inline pud_t *pud_offset(p4d_t *p4d, unsigned long address) 130 { 131 return p4d_pgtable(*p4d) + pud_index(address); 132 } 133 #define pud_offset pud_offset 134 #endif 135 136 static inline pgd_t *pgd_offset_pgd(pgd_t *pgd, unsigned long address) 137 { 138 return (pgd + pgd_index(address)); 139 }; 140 141 /* 142 * a shortcut to get a pgd_t in a given mm 143 */ 144 #ifndef pgd_offset 145 #define pgd_offset(mm, address) pgd_offset_pgd((mm)->pgd, (address)) 146 #endif 147 148 /* 149 * a shortcut which implies the use of the kernel's pgd, instead 150 * of a process's 151 */ 152 #ifndef pgd_offset_k 153 #define pgd_offset_k(address) pgd_offset(&init_mm, (address)) 154 #endif 155 156 /* 157 * In many cases it is known that a virtual address is mapped at PMD or PTE 158 * level, so instead of traversing all the page table levels, we can get a 159 * pointer to the PMD entry in user or kernel page table or translate a virtual 160 * address to the pointer in the PTE in the kernel page tables with simple 161 * helpers. 162 */ 163 static inline pmd_t *pmd_off(struct mm_struct *mm, unsigned long va) 164 { 165 return pmd_offset(pud_offset(p4d_offset(pgd_offset(mm, va), va), va), va); 166 } 167 168 static inline pmd_t *pmd_off_k(unsigned long va) 169 { 170 return pmd_offset(pud_offset(p4d_offset(pgd_offset_k(va), va), va), va); 171 } 172 173 static inline pte_t *virt_to_kpte(unsigned long vaddr) 174 { 175 pmd_t *pmd = pmd_off_k(vaddr); 176 177 return pmd_none(*pmd) ? NULL : pte_offset_kernel(pmd, vaddr); 178 } 179 180 #ifndef pmd_young 181 static inline int pmd_young(pmd_t pmd) 182 { 183 return 0; 184 } 185 #endif 186 187 #ifndef pmd_dirty 188 static inline int pmd_dirty(pmd_t pmd) 189 { 190 return 0; 191 } 192 #endif 193 194 /* 195 * A facility to provide lazy MMU batching. This allows PTE updates and 196 * page invalidations to be delayed until a call to leave lazy MMU mode 197 * is issued. Some architectures may benefit from doing this, and it is 198 * beneficial for both shadow and direct mode hypervisors, which may batch 199 * the PTE updates which happen during this window. Note that using this 200 * interface requires that read hazards be removed from the code. A read 201 * hazard could result in the direct mode hypervisor case, since the actual 202 * write to the page tables may not yet have taken place, so reads though 203 * a raw PTE pointer after it has been modified are not guaranteed to be 204 * up to date. This mode can only be entered and left under the protection of 205 * the page table locks for all page tables which may be modified. In the UP 206 * case, this is required so that preemption is disabled, and in the SMP case, 207 * it must synchronize the delayed page table writes properly on other CPUs. 208 */ 209 #ifndef __HAVE_ARCH_ENTER_LAZY_MMU_MODE 210 #define arch_enter_lazy_mmu_mode() do {} while (0) 211 #define arch_leave_lazy_mmu_mode() do {} while (0) 212 #define arch_flush_lazy_mmu_mode() do {} while (0) 213 #endif 214 215 #ifndef set_ptes 216 217 #ifndef pte_next_pfn 218 static inline pte_t pte_next_pfn(pte_t pte) 219 { 220 return __pte(pte_val(pte) + (1UL << PFN_PTE_SHIFT)); 221 } 222 #endif 223 224 /** 225 * set_ptes - Map consecutive pages to a contiguous range of addresses. 226 * @mm: Address space to map the pages into. 227 * @addr: Address to map the first page at. 228 * @ptep: Page table pointer for the first entry. 229 * @pte: Page table entry for the first page. 230 * @nr: Number of pages to map. 231 * 232 * May be overridden by the architecture, or the architecture can define 233 * set_pte() and PFN_PTE_SHIFT. 234 * 235 * Context: The caller holds the page table lock. The pages all belong 236 * to the same folio. The PTEs are all in the same PMD. 237 */ 238 static inline void set_ptes(struct mm_struct *mm, unsigned long addr, 239 pte_t *ptep, pte_t pte, unsigned int nr) 240 { 241 page_table_check_ptes_set(mm, ptep, pte, nr); 242 243 arch_enter_lazy_mmu_mode(); 244 for (;;) { 245 set_pte(ptep, pte); 246 if (--nr == 0) 247 break; 248 ptep++; 249 pte = pte_next_pfn(pte); 250 } 251 arch_leave_lazy_mmu_mode(); 252 } 253 #endif 254 #define set_pte_at(mm, addr, ptep, pte) set_ptes(mm, addr, ptep, pte, 1) 255 256 #ifndef __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 257 extern int ptep_set_access_flags(struct vm_area_struct *vma, 258 unsigned long address, pte_t *ptep, 259 pte_t entry, int dirty); 260 #endif 261 262 #ifndef __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 263 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 264 extern int pmdp_set_access_flags(struct vm_area_struct *vma, 265 unsigned long address, pmd_t *pmdp, 266 pmd_t entry, int dirty); 267 extern int pudp_set_access_flags(struct vm_area_struct *vma, 268 unsigned long address, pud_t *pudp, 269 pud_t entry, int dirty); 270 #else 271 static inline int pmdp_set_access_flags(struct vm_area_struct *vma, 272 unsigned long address, pmd_t *pmdp, 273 pmd_t entry, int dirty) 274 { 275 BUILD_BUG(); 276 return 0; 277 } 278 static inline int pudp_set_access_flags(struct vm_area_struct *vma, 279 unsigned long address, pud_t *pudp, 280 pud_t entry, int dirty) 281 { 282 BUILD_BUG(); 283 return 0; 284 } 285 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 286 #endif 287 288 #ifndef ptep_get 289 static inline pte_t ptep_get(pte_t *ptep) 290 { 291 return READ_ONCE(*ptep); 292 } 293 #endif 294 295 #ifndef pmdp_get 296 static inline pmd_t pmdp_get(pmd_t *pmdp) 297 { 298 return READ_ONCE(*pmdp); 299 } 300 #endif 301 302 #ifndef pudp_get 303 static inline pud_t pudp_get(pud_t *pudp) 304 { 305 return READ_ONCE(*pudp); 306 } 307 #endif 308 309 #ifndef p4dp_get 310 static inline p4d_t p4dp_get(p4d_t *p4dp) 311 { 312 return READ_ONCE(*p4dp); 313 } 314 #endif 315 316 #ifndef pgdp_get 317 static inline pgd_t pgdp_get(pgd_t *pgdp) 318 { 319 return READ_ONCE(*pgdp); 320 } 321 #endif 322 323 #ifndef __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 324 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 325 unsigned long address, 326 pte_t *ptep) 327 { 328 pte_t pte = ptep_get(ptep); 329 int r = 1; 330 if (!pte_young(pte)) 331 r = 0; 332 else 333 set_pte_at(vma->vm_mm, address, ptep, pte_mkold(pte)); 334 return r; 335 } 336 #endif 337 338 #ifndef __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 339 #if defined(CONFIG_TRANSPARENT_HUGEPAGE) || defined(CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG) 340 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 341 unsigned long address, 342 pmd_t *pmdp) 343 { 344 pmd_t pmd = *pmdp; 345 int r = 1; 346 if (!pmd_young(pmd)) 347 r = 0; 348 else 349 set_pmd_at(vma->vm_mm, address, pmdp, pmd_mkold(pmd)); 350 return r; 351 } 352 #else 353 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 354 unsigned long address, 355 pmd_t *pmdp) 356 { 357 BUILD_BUG(); 358 return 0; 359 } 360 #endif /* CONFIG_TRANSPARENT_HUGEPAGE || CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG */ 361 #endif 362 363 #ifndef __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 364 int ptep_clear_flush_young(struct vm_area_struct *vma, 365 unsigned long address, pte_t *ptep); 366 #endif 367 368 #ifndef __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH 369 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 370 extern int pmdp_clear_flush_young(struct vm_area_struct *vma, 371 unsigned long address, pmd_t *pmdp); 372 #else 373 /* 374 * Despite relevant to THP only, this API is called from generic rmap code 375 * under PageTransHuge(), hence needs a dummy implementation for !THP 376 */ 377 static inline int pmdp_clear_flush_young(struct vm_area_struct *vma, 378 unsigned long address, pmd_t *pmdp) 379 { 380 BUILD_BUG(); 381 return 0; 382 } 383 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 384 #endif 385 386 #ifndef arch_has_hw_nonleaf_pmd_young 387 /* 388 * Return whether the accessed bit in non-leaf PMD entries is supported on the 389 * local CPU. 390 */ 391 static inline bool arch_has_hw_nonleaf_pmd_young(void) 392 { 393 return IS_ENABLED(CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG); 394 } 395 #endif 396 397 #ifndef arch_has_hw_pte_young 398 /* 399 * Return whether the accessed bit is supported on the local CPU. 400 * 401 * This stub assumes accessing through an old PTE triggers a page fault. 402 * Architectures that automatically set the access bit should overwrite it. 403 */ 404 static inline bool arch_has_hw_pte_young(void) 405 { 406 return IS_ENABLED(CONFIG_ARCH_HAS_HW_PTE_YOUNG); 407 } 408 #endif 409 410 #ifndef arch_check_zapped_pte 411 static inline void arch_check_zapped_pte(struct vm_area_struct *vma, 412 pte_t pte) 413 { 414 } 415 #endif 416 417 #ifndef arch_check_zapped_pmd 418 static inline void arch_check_zapped_pmd(struct vm_area_struct *vma, 419 pmd_t pmd) 420 { 421 } 422 #endif 423 424 #ifndef __HAVE_ARCH_PTEP_GET_AND_CLEAR 425 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 426 unsigned long address, 427 pte_t *ptep) 428 { 429 pte_t pte = ptep_get(ptep); 430 pte_clear(mm, address, ptep); 431 page_table_check_pte_clear(mm, pte); 432 return pte; 433 } 434 #endif 435 436 static inline void ptep_clear(struct mm_struct *mm, unsigned long addr, 437 pte_t *ptep) 438 { 439 ptep_get_and_clear(mm, addr, ptep); 440 } 441 442 #ifdef CONFIG_GUP_GET_PXX_LOW_HIGH 443 /* 444 * For walking the pagetables without holding any locks. Some architectures 445 * (eg x86-32 PAE) cannot load the entries atomically without using expensive 446 * instructions. We are guaranteed that a PTE will only either go from not 447 * present to present, or present to not present -- it will not switch to a 448 * completely different present page without a TLB flush inbetween; which we 449 * are blocking by holding interrupts off. 450 * 451 * Setting ptes from not present to present goes: 452 * 453 * ptep->pte_high = h; 454 * smp_wmb(); 455 * ptep->pte_low = l; 456 * 457 * And present to not present goes: 458 * 459 * ptep->pte_low = 0; 460 * smp_wmb(); 461 * ptep->pte_high = 0; 462 * 463 * We must ensure here that the load of pte_low sees 'l' IFF pte_high sees 'h'. 464 * We load pte_high *after* loading pte_low, which ensures we don't see an older 465 * value of pte_high. *Then* we recheck pte_low, which ensures that we haven't 466 * picked up a changed pte high. We might have gotten rubbish values from 467 * pte_low and pte_high, but we are guaranteed that pte_low will not have the 468 * present bit set *unless* it is 'l'. Because get_user_pages_fast() only 469 * operates on present ptes we're safe. 470 */ 471 static inline pte_t ptep_get_lockless(pte_t *ptep) 472 { 473 pte_t pte; 474 475 do { 476 pte.pte_low = ptep->pte_low; 477 smp_rmb(); 478 pte.pte_high = ptep->pte_high; 479 smp_rmb(); 480 } while (unlikely(pte.pte_low != ptep->pte_low)); 481 482 return pte; 483 } 484 #define ptep_get_lockless ptep_get_lockless 485 486 #if CONFIG_PGTABLE_LEVELS > 2 487 static inline pmd_t pmdp_get_lockless(pmd_t *pmdp) 488 { 489 pmd_t pmd; 490 491 do { 492 pmd.pmd_low = pmdp->pmd_low; 493 smp_rmb(); 494 pmd.pmd_high = pmdp->pmd_high; 495 smp_rmb(); 496 } while (unlikely(pmd.pmd_low != pmdp->pmd_low)); 497 498 return pmd; 499 } 500 #define pmdp_get_lockless pmdp_get_lockless 501 #define pmdp_get_lockless_sync() tlb_remove_table_sync_one() 502 #endif /* CONFIG_PGTABLE_LEVELS > 2 */ 503 #endif /* CONFIG_GUP_GET_PXX_LOW_HIGH */ 504 505 /* 506 * We require that the PTE can be read atomically. 507 */ 508 #ifndef ptep_get_lockless 509 static inline pte_t ptep_get_lockless(pte_t *ptep) 510 { 511 return ptep_get(ptep); 512 } 513 #endif 514 515 #ifndef pmdp_get_lockless 516 static inline pmd_t pmdp_get_lockless(pmd_t *pmdp) 517 { 518 return pmdp_get(pmdp); 519 } 520 static inline void pmdp_get_lockless_sync(void) 521 { 522 } 523 #endif 524 525 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 526 #ifndef __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 527 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 528 unsigned long address, 529 pmd_t *pmdp) 530 { 531 pmd_t pmd = *pmdp; 532 533 pmd_clear(pmdp); 534 page_table_check_pmd_clear(mm, pmd); 535 536 return pmd; 537 } 538 #endif /* __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR */ 539 #ifndef __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR 540 static inline pud_t pudp_huge_get_and_clear(struct mm_struct *mm, 541 unsigned long address, 542 pud_t *pudp) 543 { 544 pud_t pud = *pudp; 545 546 pud_clear(pudp); 547 page_table_check_pud_clear(mm, pud); 548 549 return pud; 550 } 551 #endif /* __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR */ 552 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 553 554 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 555 #ifndef __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR_FULL 556 static inline pmd_t pmdp_huge_get_and_clear_full(struct vm_area_struct *vma, 557 unsigned long address, pmd_t *pmdp, 558 int full) 559 { 560 return pmdp_huge_get_and_clear(vma->vm_mm, address, pmdp); 561 } 562 #endif 563 564 #ifndef __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR_FULL 565 static inline pud_t pudp_huge_get_and_clear_full(struct vm_area_struct *vma, 566 unsigned long address, pud_t *pudp, 567 int full) 568 { 569 return pudp_huge_get_and_clear(vma->vm_mm, address, pudp); 570 } 571 #endif 572 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 573 574 #ifndef __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL 575 static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, 576 unsigned long address, pte_t *ptep, 577 int full) 578 { 579 return ptep_get_and_clear(mm, address, ptep); 580 } 581 #endif 582 583 584 /* 585 * If two threads concurrently fault at the same page, the thread that 586 * won the race updates the PTE and its local TLB/Cache. The other thread 587 * gives up, simply does nothing, and continues; on architectures where 588 * software can update TLB, local TLB can be updated here to avoid next page 589 * fault. This function updates TLB only, do nothing with cache or others. 590 * It is the difference with function update_mmu_cache. 591 */ 592 #ifndef __HAVE_ARCH_UPDATE_MMU_TLB 593 static inline void update_mmu_tlb(struct vm_area_struct *vma, 594 unsigned long address, pte_t *ptep) 595 { 596 } 597 #define __HAVE_ARCH_UPDATE_MMU_TLB 598 #endif 599 600 /* 601 * Some architectures may be able to avoid expensive synchronization 602 * primitives when modifications are made to PTE's which are already 603 * not present, or in the process of an address space destruction. 604 */ 605 #ifndef __HAVE_ARCH_PTE_CLEAR_NOT_PRESENT_FULL 606 static inline void pte_clear_not_present_full(struct mm_struct *mm, 607 unsigned long address, 608 pte_t *ptep, 609 int full) 610 { 611 pte_clear(mm, address, ptep); 612 } 613 #endif 614 615 #ifndef __HAVE_ARCH_PTEP_CLEAR_FLUSH 616 extern pte_t ptep_clear_flush(struct vm_area_struct *vma, 617 unsigned long address, 618 pte_t *ptep); 619 #endif 620 621 #ifndef __HAVE_ARCH_PMDP_HUGE_CLEAR_FLUSH 622 extern pmd_t pmdp_huge_clear_flush(struct vm_area_struct *vma, 623 unsigned long address, 624 pmd_t *pmdp); 625 extern pud_t pudp_huge_clear_flush(struct vm_area_struct *vma, 626 unsigned long address, 627 pud_t *pudp); 628 #endif 629 630 #ifndef pte_mkwrite 631 static inline pte_t pte_mkwrite(pte_t pte, struct vm_area_struct *vma) 632 { 633 return pte_mkwrite_novma(pte); 634 } 635 #endif 636 637 #if defined(CONFIG_ARCH_WANT_PMD_MKWRITE) && !defined(pmd_mkwrite) 638 static inline pmd_t pmd_mkwrite(pmd_t pmd, struct vm_area_struct *vma) 639 { 640 return pmd_mkwrite_novma(pmd); 641 } 642 #endif 643 644 #ifndef __HAVE_ARCH_PTEP_SET_WRPROTECT 645 struct mm_struct; 646 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep) 647 { 648 pte_t old_pte = ptep_get(ptep); 649 set_pte_at(mm, address, ptep, pte_wrprotect(old_pte)); 650 } 651 #endif 652 653 /* 654 * On some architectures hardware does not set page access bit when accessing 655 * memory page, it is responsibility of software setting this bit. It brings 656 * out extra page fault penalty to track page access bit. For optimization page 657 * access bit can be set during all page fault flow on these arches. 658 * To be differentiate with macro pte_mkyoung, this macro is used on platforms 659 * where software maintains page access bit. 660 */ 661 #ifndef pte_sw_mkyoung 662 static inline pte_t pte_sw_mkyoung(pte_t pte) 663 { 664 return pte; 665 } 666 #define pte_sw_mkyoung pte_sw_mkyoung 667 #endif 668 669 #ifndef __HAVE_ARCH_PMDP_SET_WRPROTECT 670 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 671 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 672 unsigned long address, pmd_t *pmdp) 673 { 674 pmd_t old_pmd = *pmdp; 675 set_pmd_at(mm, address, pmdp, pmd_wrprotect(old_pmd)); 676 } 677 #else 678 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 679 unsigned long address, pmd_t *pmdp) 680 { 681 BUILD_BUG(); 682 } 683 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 684 #endif 685 #ifndef __HAVE_ARCH_PUDP_SET_WRPROTECT 686 #ifdef CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD 687 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 688 static inline void pudp_set_wrprotect(struct mm_struct *mm, 689 unsigned long address, pud_t *pudp) 690 { 691 pud_t old_pud = *pudp; 692 693 set_pud_at(mm, address, pudp, pud_wrprotect(old_pud)); 694 } 695 #else 696 static inline void pudp_set_wrprotect(struct mm_struct *mm, 697 unsigned long address, pud_t *pudp) 698 { 699 BUILD_BUG(); 700 } 701 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 702 #endif /* CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD */ 703 #endif 704 705 #ifndef pmdp_collapse_flush 706 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 707 extern pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, 708 unsigned long address, pmd_t *pmdp); 709 #else 710 static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, 711 unsigned long address, 712 pmd_t *pmdp) 713 { 714 BUILD_BUG(); 715 return *pmdp; 716 } 717 #define pmdp_collapse_flush pmdp_collapse_flush 718 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 719 #endif 720 721 #ifndef __HAVE_ARCH_PGTABLE_DEPOSIT 722 extern void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp, 723 pgtable_t pgtable); 724 #endif 725 726 #ifndef __HAVE_ARCH_PGTABLE_WITHDRAW 727 extern pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp); 728 #endif 729 730 #ifndef arch_needs_pgtable_deposit 731 #define arch_needs_pgtable_deposit() (false) 732 #endif 733 734 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 735 /* 736 * This is an implementation of pmdp_establish() that is only suitable for an 737 * architecture that doesn't have hardware dirty/accessed bits. In this case we 738 * can't race with CPU which sets these bits and non-atomic approach is fine. 739 */ 740 static inline pmd_t generic_pmdp_establish(struct vm_area_struct *vma, 741 unsigned long address, pmd_t *pmdp, pmd_t pmd) 742 { 743 pmd_t old_pmd = *pmdp; 744 set_pmd_at(vma->vm_mm, address, pmdp, pmd); 745 return old_pmd; 746 } 747 #endif 748 749 #ifndef __HAVE_ARCH_PMDP_INVALIDATE 750 extern pmd_t pmdp_invalidate(struct vm_area_struct *vma, unsigned long address, 751 pmd_t *pmdp); 752 #endif 753 754 #ifndef __HAVE_ARCH_PMDP_INVALIDATE_AD 755 756 /* 757 * pmdp_invalidate_ad() invalidates the PMD while changing a transparent 758 * hugepage mapping in the page tables. This function is similar to 759 * pmdp_invalidate(), but should only be used if the access and dirty bits would 760 * not be cleared by the software in the new PMD value. The function ensures 761 * that hardware changes of the access and dirty bits updates would not be lost. 762 * 763 * Doing so can allow in certain architectures to avoid a TLB flush in most 764 * cases. Yet, another TLB flush might be necessary later if the PMD update 765 * itself requires such flush (e.g., if protection was set to be stricter). Yet, 766 * even when a TLB flush is needed because of the update, the caller may be able 767 * to batch these TLB flushing operations, so fewer TLB flush operations are 768 * needed. 769 */ 770 extern pmd_t pmdp_invalidate_ad(struct vm_area_struct *vma, 771 unsigned long address, pmd_t *pmdp); 772 #endif 773 774 #ifndef __HAVE_ARCH_PTE_SAME 775 static inline int pte_same(pte_t pte_a, pte_t pte_b) 776 { 777 return pte_val(pte_a) == pte_val(pte_b); 778 } 779 #endif 780 781 #ifndef __HAVE_ARCH_PTE_UNUSED 782 /* 783 * Some architectures provide facilities to virtualization guests 784 * so that they can flag allocated pages as unused. This allows the 785 * host to transparently reclaim unused pages. This function returns 786 * whether the pte's page is unused. 787 */ 788 static inline int pte_unused(pte_t pte) 789 { 790 return 0; 791 } 792 #endif 793 794 #ifndef pte_access_permitted 795 #define pte_access_permitted(pte, write) \ 796 (pte_present(pte) && (!(write) || pte_write(pte))) 797 #endif 798 799 #ifndef pmd_access_permitted 800 #define pmd_access_permitted(pmd, write) \ 801 (pmd_present(pmd) && (!(write) || pmd_write(pmd))) 802 #endif 803 804 #ifndef pud_access_permitted 805 #define pud_access_permitted(pud, write) \ 806 (pud_present(pud) && (!(write) || pud_write(pud))) 807 #endif 808 809 #ifndef p4d_access_permitted 810 #define p4d_access_permitted(p4d, write) \ 811 (p4d_present(p4d) && (!(write) || p4d_write(p4d))) 812 #endif 813 814 #ifndef pgd_access_permitted 815 #define pgd_access_permitted(pgd, write) \ 816 (pgd_present(pgd) && (!(write) || pgd_write(pgd))) 817 #endif 818 819 #ifndef __HAVE_ARCH_PMD_SAME 820 static inline int pmd_same(pmd_t pmd_a, pmd_t pmd_b) 821 { 822 return pmd_val(pmd_a) == pmd_val(pmd_b); 823 } 824 #endif 825 826 #ifndef pud_same 827 static inline int pud_same(pud_t pud_a, pud_t pud_b) 828 { 829 return pud_val(pud_a) == pud_val(pud_b); 830 } 831 #define pud_same pud_same 832 #endif 833 834 #ifndef __HAVE_ARCH_P4D_SAME 835 static inline int p4d_same(p4d_t p4d_a, p4d_t p4d_b) 836 { 837 return p4d_val(p4d_a) == p4d_val(p4d_b); 838 } 839 #endif 840 841 #ifndef __HAVE_ARCH_PGD_SAME 842 static inline int pgd_same(pgd_t pgd_a, pgd_t pgd_b) 843 { 844 return pgd_val(pgd_a) == pgd_val(pgd_b); 845 } 846 #endif 847 848 /* 849 * Use set_p*_safe(), and elide TLB flushing, when confident that *no* 850 * TLB flush will be required as a result of the "set". For example, use 851 * in scenarios where it is known ahead of time that the routine is 852 * setting non-present entries, or re-setting an existing entry to the 853 * same value. Otherwise, use the typical "set" helpers and flush the 854 * TLB. 855 */ 856 #define set_pte_safe(ptep, pte) \ 857 ({ \ 858 WARN_ON_ONCE(pte_present(*ptep) && !pte_same(*ptep, pte)); \ 859 set_pte(ptep, pte); \ 860 }) 861 862 #define set_pmd_safe(pmdp, pmd) \ 863 ({ \ 864 WARN_ON_ONCE(pmd_present(*pmdp) && !pmd_same(*pmdp, pmd)); \ 865 set_pmd(pmdp, pmd); \ 866 }) 867 868 #define set_pud_safe(pudp, pud) \ 869 ({ \ 870 WARN_ON_ONCE(pud_present(*pudp) && !pud_same(*pudp, pud)); \ 871 set_pud(pudp, pud); \ 872 }) 873 874 #define set_p4d_safe(p4dp, p4d) \ 875 ({ \ 876 WARN_ON_ONCE(p4d_present(*p4dp) && !p4d_same(*p4dp, p4d)); \ 877 set_p4d(p4dp, p4d); \ 878 }) 879 880 #define set_pgd_safe(pgdp, pgd) \ 881 ({ \ 882 WARN_ON_ONCE(pgd_present(*pgdp) && !pgd_same(*pgdp, pgd)); \ 883 set_pgd(pgdp, pgd); \ 884 }) 885 886 #ifndef __HAVE_ARCH_DO_SWAP_PAGE 887 /* 888 * Some architectures support metadata associated with a page. When a 889 * page is being swapped out, this metadata must be saved so it can be 890 * restored when the page is swapped back in. SPARC M7 and newer 891 * processors support an ADI (Application Data Integrity) tag for the 892 * page as metadata for the page. arch_do_swap_page() can restore this 893 * metadata when a page is swapped back in. 894 */ 895 static inline void arch_do_swap_page(struct mm_struct *mm, 896 struct vm_area_struct *vma, 897 unsigned long addr, 898 pte_t pte, pte_t oldpte) 899 { 900 901 } 902 #endif 903 904 #ifndef __HAVE_ARCH_UNMAP_ONE 905 /* 906 * Some architectures support metadata associated with a page. When a 907 * page is being swapped out, this metadata must be saved so it can be 908 * restored when the page is swapped back in. SPARC M7 and newer 909 * processors support an ADI (Application Data Integrity) tag for the 910 * page as metadata for the page. arch_unmap_one() can save this 911 * metadata on a swap-out of a page. 912 */ 913 static inline int arch_unmap_one(struct mm_struct *mm, 914 struct vm_area_struct *vma, 915 unsigned long addr, 916 pte_t orig_pte) 917 { 918 return 0; 919 } 920 #endif 921 922 /* 923 * Allow architectures to preserve additional metadata associated with 924 * swapped-out pages. The corresponding __HAVE_ARCH_SWAP_* macros and function 925 * prototypes must be defined in the arch-specific asm/pgtable.h file. 926 */ 927 #ifndef __HAVE_ARCH_PREPARE_TO_SWAP 928 static inline int arch_prepare_to_swap(struct page *page) 929 { 930 return 0; 931 } 932 #endif 933 934 #ifndef __HAVE_ARCH_SWAP_INVALIDATE 935 static inline void arch_swap_invalidate_page(int type, pgoff_t offset) 936 { 937 } 938 939 static inline void arch_swap_invalidate_area(int type) 940 { 941 } 942 #endif 943 944 #ifndef __HAVE_ARCH_SWAP_RESTORE 945 static inline void arch_swap_restore(swp_entry_t entry, struct folio *folio) 946 { 947 } 948 #endif 949 950 #ifndef __HAVE_ARCH_PGD_OFFSET_GATE 951 #define pgd_offset_gate(mm, addr) pgd_offset(mm, addr) 952 #endif 953 954 #ifndef __HAVE_ARCH_MOVE_PTE 955 #define move_pte(pte, prot, old_addr, new_addr) (pte) 956 #endif 957 958 #ifndef pte_accessible 959 # define pte_accessible(mm, pte) ((void)(pte), 1) 960 #endif 961 962 #ifndef flush_tlb_fix_spurious_fault 963 #define flush_tlb_fix_spurious_fault(vma, address, ptep) flush_tlb_page(vma, address) 964 #endif 965 966 /* 967 * When walking page tables, get the address of the next boundary, 968 * or the end address of the range if that comes earlier. Although no 969 * vma end wraps to 0, rounded up __boundary may wrap to 0 throughout. 970 */ 971 972 #define pgd_addr_end(addr, end) \ 973 ({ unsigned long __boundary = ((addr) + PGDIR_SIZE) & PGDIR_MASK; \ 974 (__boundary - 1 < (end) - 1)? __boundary: (end); \ 975 }) 976 977 #ifndef p4d_addr_end 978 #define p4d_addr_end(addr, end) \ 979 ({ unsigned long __boundary = ((addr) + P4D_SIZE) & P4D_MASK; \ 980 (__boundary - 1 < (end) - 1)? __boundary: (end); \ 981 }) 982 #endif 983 984 #ifndef pud_addr_end 985 #define pud_addr_end(addr, end) \ 986 ({ unsigned long __boundary = ((addr) + PUD_SIZE) & PUD_MASK; \ 987 (__boundary - 1 < (end) - 1)? __boundary: (end); \ 988 }) 989 #endif 990 991 #ifndef pmd_addr_end 992 #define pmd_addr_end(addr, end) \ 993 ({ unsigned long __boundary = ((addr) + PMD_SIZE) & PMD_MASK; \ 994 (__boundary - 1 < (end) - 1)? __boundary: (end); \ 995 }) 996 #endif 997 998 /* 999 * When walking page tables, we usually want to skip any p?d_none entries; 1000 * and any p?d_bad entries - reporting the error before resetting to none. 1001 * Do the tests inline, but report and clear the bad entry in mm/memory.c. 1002 */ 1003 void pgd_clear_bad(pgd_t *); 1004 1005 #ifndef __PAGETABLE_P4D_FOLDED 1006 void p4d_clear_bad(p4d_t *); 1007 #else 1008 #define p4d_clear_bad(p4d) do { } while (0) 1009 #endif 1010 1011 #ifndef __PAGETABLE_PUD_FOLDED 1012 void pud_clear_bad(pud_t *); 1013 #else 1014 #define pud_clear_bad(p4d) do { } while (0) 1015 #endif 1016 1017 void pmd_clear_bad(pmd_t *); 1018 1019 static inline int pgd_none_or_clear_bad(pgd_t *pgd) 1020 { 1021 if (pgd_none(*pgd)) 1022 return 1; 1023 if (unlikely(pgd_bad(*pgd))) { 1024 pgd_clear_bad(pgd); 1025 return 1; 1026 } 1027 return 0; 1028 } 1029 1030 static inline int p4d_none_or_clear_bad(p4d_t *p4d) 1031 { 1032 if (p4d_none(*p4d)) 1033 return 1; 1034 if (unlikely(p4d_bad(*p4d))) { 1035 p4d_clear_bad(p4d); 1036 return 1; 1037 } 1038 return 0; 1039 } 1040 1041 static inline int pud_none_or_clear_bad(pud_t *pud) 1042 { 1043 if (pud_none(*pud)) 1044 return 1; 1045 if (unlikely(pud_bad(*pud))) { 1046 pud_clear_bad(pud); 1047 return 1; 1048 } 1049 return 0; 1050 } 1051 1052 static inline int pmd_none_or_clear_bad(pmd_t *pmd) 1053 { 1054 if (pmd_none(*pmd)) 1055 return 1; 1056 if (unlikely(pmd_bad(*pmd))) { 1057 pmd_clear_bad(pmd); 1058 return 1; 1059 } 1060 return 0; 1061 } 1062 1063 static inline pte_t __ptep_modify_prot_start(struct vm_area_struct *vma, 1064 unsigned long addr, 1065 pte_t *ptep) 1066 { 1067 /* 1068 * Get the current pte state, but zero it out to make it 1069 * non-present, preventing the hardware from asynchronously 1070 * updating it. 1071 */ 1072 return ptep_get_and_clear(vma->vm_mm, addr, ptep); 1073 } 1074 1075 static inline void __ptep_modify_prot_commit(struct vm_area_struct *vma, 1076 unsigned long addr, 1077 pte_t *ptep, pte_t pte) 1078 { 1079 /* 1080 * The pte is non-present, so there's no hardware state to 1081 * preserve. 1082 */ 1083 set_pte_at(vma->vm_mm, addr, ptep, pte); 1084 } 1085 1086 #ifndef __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION 1087 /* 1088 * Start a pte protection read-modify-write transaction, which 1089 * protects against asynchronous hardware modifications to the pte. 1090 * The intention is not to prevent the hardware from making pte 1091 * updates, but to prevent any updates it may make from being lost. 1092 * 1093 * This does not protect against other software modifications of the 1094 * pte; the appropriate pte lock must be held over the transaction. 1095 * 1096 * Note that this interface is intended to be batchable, meaning that 1097 * ptep_modify_prot_commit may not actually update the pte, but merely 1098 * queue the update to be done at some later time. The update must be 1099 * actually committed before the pte lock is released, however. 1100 */ 1101 static inline pte_t ptep_modify_prot_start(struct vm_area_struct *vma, 1102 unsigned long addr, 1103 pte_t *ptep) 1104 { 1105 return __ptep_modify_prot_start(vma, addr, ptep); 1106 } 1107 1108 /* 1109 * Commit an update to a pte, leaving any hardware-controlled bits in 1110 * the PTE unmodified. 1111 */ 1112 static inline void ptep_modify_prot_commit(struct vm_area_struct *vma, 1113 unsigned long addr, 1114 pte_t *ptep, pte_t old_pte, pte_t pte) 1115 { 1116 __ptep_modify_prot_commit(vma, addr, ptep, pte); 1117 } 1118 #endif /* __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION */ 1119 #endif /* CONFIG_MMU */ 1120 1121 /* 1122 * No-op macros that just return the current protection value. Defined here 1123 * because these macros can be used even if CONFIG_MMU is not defined. 1124 */ 1125 1126 #ifndef pgprot_nx 1127 #define pgprot_nx(prot) (prot) 1128 #endif 1129 1130 #ifndef pgprot_noncached 1131 #define pgprot_noncached(prot) (prot) 1132 #endif 1133 1134 #ifndef pgprot_writecombine 1135 #define pgprot_writecombine pgprot_noncached 1136 #endif 1137 1138 #ifndef pgprot_writethrough 1139 #define pgprot_writethrough pgprot_noncached 1140 #endif 1141 1142 #ifndef pgprot_device 1143 #define pgprot_device pgprot_noncached 1144 #endif 1145 1146 #ifndef pgprot_mhp 1147 #define pgprot_mhp(prot) (prot) 1148 #endif 1149 1150 #ifdef CONFIG_MMU 1151 #ifndef pgprot_modify 1152 #define pgprot_modify pgprot_modify 1153 static inline pgprot_t pgprot_modify(pgprot_t oldprot, pgprot_t newprot) 1154 { 1155 if (pgprot_val(oldprot) == pgprot_val(pgprot_noncached(oldprot))) 1156 newprot = pgprot_noncached(newprot); 1157 if (pgprot_val(oldprot) == pgprot_val(pgprot_writecombine(oldprot))) 1158 newprot = pgprot_writecombine(newprot); 1159 if (pgprot_val(oldprot) == pgprot_val(pgprot_device(oldprot))) 1160 newprot = pgprot_device(newprot); 1161 return newprot; 1162 } 1163 #endif 1164 #endif /* CONFIG_MMU */ 1165 1166 #ifndef pgprot_encrypted 1167 #define pgprot_encrypted(prot) (prot) 1168 #endif 1169 1170 #ifndef pgprot_decrypted 1171 #define pgprot_decrypted(prot) (prot) 1172 #endif 1173 1174 /* 1175 * A facility to provide batching of the reload of page tables and 1176 * other process state with the actual context switch code for 1177 * paravirtualized guests. By convention, only one of the batched 1178 * update (lazy) modes (CPU, MMU) should be active at any given time, 1179 * entry should never be nested, and entry and exits should always be 1180 * paired. This is for sanity of maintaining and reasoning about the 1181 * kernel code. In this case, the exit (end of the context switch) is 1182 * in architecture-specific code, and so doesn't need a generic 1183 * definition. 1184 */ 1185 #ifndef __HAVE_ARCH_START_CONTEXT_SWITCH 1186 #define arch_start_context_switch(prev) do {} while (0) 1187 #endif 1188 1189 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 1190 #ifndef CONFIG_ARCH_ENABLE_THP_MIGRATION 1191 static inline pmd_t pmd_swp_mksoft_dirty(pmd_t pmd) 1192 { 1193 return pmd; 1194 } 1195 1196 static inline int pmd_swp_soft_dirty(pmd_t pmd) 1197 { 1198 return 0; 1199 } 1200 1201 static inline pmd_t pmd_swp_clear_soft_dirty(pmd_t pmd) 1202 { 1203 return pmd; 1204 } 1205 #endif 1206 #else /* !CONFIG_HAVE_ARCH_SOFT_DIRTY */ 1207 static inline int pte_soft_dirty(pte_t pte) 1208 { 1209 return 0; 1210 } 1211 1212 static inline int pmd_soft_dirty(pmd_t pmd) 1213 { 1214 return 0; 1215 } 1216 1217 static inline pte_t pte_mksoft_dirty(pte_t pte) 1218 { 1219 return pte; 1220 } 1221 1222 static inline pmd_t pmd_mksoft_dirty(pmd_t pmd) 1223 { 1224 return pmd; 1225 } 1226 1227 static inline pte_t pte_clear_soft_dirty(pte_t pte) 1228 { 1229 return pte; 1230 } 1231 1232 static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd) 1233 { 1234 return pmd; 1235 } 1236 1237 static inline pte_t pte_swp_mksoft_dirty(pte_t pte) 1238 { 1239 return pte; 1240 } 1241 1242 static inline int pte_swp_soft_dirty(pte_t pte) 1243 { 1244 return 0; 1245 } 1246 1247 static inline pte_t pte_swp_clear_soft_dirty(pte_t pte) 1248 { 1249 return pte; 1250 } 1251 1252 static inline pmd_t pmd_swp_mksoft_dirty(pmd_t pmd) 1253 { 1254 return pmd; 1255 } 1256 1257 static inline int pmd_swp_soft_dirty(pmd_t pmd) 1258 { 1259 return 0; 1260 } 1261 1262 static inline pmd_t pmd_swp_clear_soft_dirty(pmd_t pmd) 1263 { 1264 return pmd; 1265 } 1266 #endif 1267 1268 #ifndef __HAVE_PFNMAP_TRACKING 1269 /* 1270 * Interfaces that can be used by architecture code to keep track of 1271 * memory type of pfn mappings specified by the remap_pfn_range, 1272 * vmf_insert_pfn. 1273 */ 1274 1275 /* 1276 * track_pfn_remap is called when a _new_ pfn mapping is being established 1277 * by remap_pfn_range() for physical range indicated by pfn and size. 1278 */ 1279 static inline int track_pfn_remap(struct vm_area_struct *vma, pgprot_t *prot, 1280 unsigned long pfn, unsigned long addr, 1281 unsigned long size) 1282 { 1283 return 0; 1284 } 1285 1286 /* 1287 * track_pfn_insert is called when a _new_ single pfn is established 1288 * by vmf_insert_pfn(). 1289 */ 1290 static inline void track_pfn_insert(struct vm_area_struct *vma, pgprot_t *prot, 1291 pfn_t pfn) 1292 { 1293 } 1294 1295 /* 1296 * track_pfn_copy is called when vma that is covering the pfnmap gets 1297 * copied through copy_page_range(). 1298 */ 1299 static inline int track_pfn_copy(struct vm_area_struct *vma) 1300 { 1301 return 0; 1302 } 1303 1304 /* 1305 * untrack_pfn is called while unmapping a pfnmap for a region. 1306 * untrack can be called for a specific region indicated by pfn and size or 1307 * can be for the entire vma (in which case pfn, size are zero). 1308 */ 1309 static inline void untrack_pfn(struct vm_area_struct *vma, 1310 unsigned long pfn, unsigned long size, 1311 bool mm_wr_locked) 1312 { 1313 } 1314 1315 /* 1316 * untrack_pfn_clear is called while mremapping a pfnmap for a new region 1317 * or fails to copy pgtable during duplicate vm area. 1318 */ 1319 static inline void untrack_pfn_clear(struct vm_area_struct *vma) 1320 { 1321 } 1322 #else 1323 extern int track_pfn_remap(struct vm_area_struct *vma, pgprot_t *prot, 1324 unsigned long pfn, unsigned long addr, 1325 unsigned long size); 1326 extern void track_pfn_insert(struct vm_area_struct *vma, pgprot_t *prot, 1327 pfn_t pfn); 1328 extern int track_pfn_copy(struct vm_area_struct *vma); 1329 extern void untrack_pfn(struct vm_area_struct *vma, unsigned long pfn, 1330 unsigned long size, bool mm_wr_locked); 1331 extern void untrack_pfn_clear(struct vm_area_struct *vma); 1332 #endif 1333 1334 #ifdef CONFIG_MMU 1335 #ifdef __HAVE_COLOR_ZERO_PAGE 1336 static inline int is_zero_pfn(unsigned long pfn) 1337 { 1338 extern unsigned long zero_pfn; 1339 unsigned long offset_from_zero_pfn = pfn - zero_pfn; 1340 return offset_from_zero_pfn <= (zero_page_mask >> PAGE_SHIFT); 1341 } 1342 1343 #define my_zero_pfn(addr) page_to_pfn(ZERO_PAGE(addr)) 1344 1345 #else 1346 static inline int is_zero_pfn(unsigned long pfn) 1347 { 1348 extern unsigned long zero_pfn; 1349 return pfn == zero_pfn; 1350 } 1351 1352 static inline unsigned long my_zero_pfn(unsigned long addr) 1353 { 1354 extern unsigned long zero_pfn; 1355 return zero_pfn; 1356 } 1357 #endif 1358 #else 1359 static inline int is_zero_pfn(unsigned long pfn) 1360 { 1361 return 0; 1362 } 1363 1364 static inline unsigned long my_zero_pfn(unsigned long addr) 1365 { 1366 return 0; 1367 } 1368 #endif /* CONFIG_MMU */ 1369 1370 #ifdef CONFIG_MMU 1371 1372 #ifndef CONFIG_TRANSPARENT_HUGEPAGE 1373 static inline int pmd_trans_huge(pmd_t pmd) 1374 { 1375 return 0; 1376 } 1377 #ifndef pmd_write 1378 static inline int pmd_write(pmd_t pmd) 1379 { 1380 BUG(); 1381 return 0; 1382 } 1383 #endif /* pmd_write */ 1384 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1385 1386 #ifndef pud_write 1387 static inline int pud_write(pud_t pud) 1388 { 1389 BUG(); 1390 return 0; 1391 } 1392 #endif /* pud_write */ 1393 1394 #if !defined(CONFIG_ARCH_HAS_PTE_DEVMAP) || !defined(CONFIG_TRANSPARENT_HUGEPAGE) 1395 static inline int pmd_devmap(pmd_t pmd) 1396 { 1397 return 0; 1398 } 1399 static inline int pud_devmap(pud_t pud) 1400 { 1401 return 0; 1402 } 1403 static inline int pgd_devmap(pgd_t pgd) 1404 { 1405 return 0; 1406 } 1407 #endif 1408 1409 #if !defined(CONFIG_TRANSPARENT_HUGEPAGE) || \ 1410 !defined(CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD) 1411 static inline int pud_trans_huge(pud_t pud) 1412 { 1413 return 0; 1414 } 1415 #endif 1416 1417 static inline int pud_trans_unstable(pud_t *pud) 1418 { 1419 #if defined(CONFIG_TRANSPARENT_HUGEPAGE) && \ 1420 defined(CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD) 1421 pud_t pudval = READ_ONCE(*pud); 1422 1423 if (pud_none(pudval) || pud_trans_huge(pudval) || pud_devmap(pudval)) 1424 return 1; 1425 if (unlikely(pud_bad(pudval))) { 1426 pud_clear_bad(pud); 1427 return 1; 1428 } 1429 #endif 1430 return 0; 1431 } 1432 1433 #ifndef CONFIG_NUMA_BALANCING 1434 /* 1435 * In an inaccessible (PROT_NONE) VMA, pte_protnone() may indicate "yes". It is 1436 * perfectly valid to indicate "no" in that case, which is why our default 1437 * implementation defaults to "always no". 1438 * 1439 * In an accessible VMA, however, pte_protnone() reliably indicates PROT_NONE 1440 * page protection due to NUMA hinting. NUMA hinting faults only apply in 1441 * accessible VMAs. 1442 * 1443 * So, to reliably identify PROT_NONE PTEs that require a NUMA hinting fault, 1444 * looking at the VMA accessibility is sufficient. 1445 */ 1446 static inline int pte_protnone(pte_t pte) 1447 { 1448 return 0; 1449 } 1450 1451 static inline int pmd_protnone(pmd_t pmd) 1452 { 1453 return 0; 1454 } 1455 #endif /* CONFIG_NUMA_BALANCING */ 1456 1457 #endif /* CONFIG_MMU */ 1458 1459 #ifdef CONFIG_HAVE_ARCH_HUGE_VMAP 1460 1461 #ifndef __PAGETABLE_P4D_FOLDED 1462 int p4d_set_huge(p4d_t *p4d, phys_addr_t addr, pgprot_t prot); 1463 void p4d_clear_huge(p4d_t *p4d); 1464 #else 1465 static inline int p4d_set_huge(p4d_t *p4d, phys_addr_t addr, pgprot_t prot) 1466 { 1467 return 0; 1468 } 1469 static inline void p4d_clear_huge(p4d_t *p4d) { } 1470 #endif /* !__PAGETABLE_P4D_FOLDED */ 1471 1472 int pud_set_huge(pud_t *pud, phys_addr_t addr, pgprot_t prot); 1473 int pmd_set_huge(pmd_t *pmd, phys_addr_t addr, pgprot_t prot); 1474 int pud_clear_huge(pud_t *pud); 1475 int pmd_clear_huge(pmd_t *pmd); 1476 int p4d_free_pud_page(p4d_t *p4d, unsigned long addr); 1477 int pud_free_pmd_page(pud_t *pud, unsigned long addr); 1478 int pmd_free_pte_page(pmd_t *pmd, unsigned long addr); 1479 #else /* !CONFIG_HAVE_ARCH_HUGE_VMAP */ 1480 static inline int p4d_set_huge(p4d_t *p4d, phys_addr_t addr, pgprot_t prot) 1481 { 1482 return 0; 1483 } 1484 static inline int pud_set_huge(pud_t *pud, phys_addr_t addr, pgprot_t prot) 1485 { 1486 return 0; 1487 } 1488 static inline int pmd_set_huge(pmd_t *pmd, phys_addr_t addr, pgprot_t prot) 1489 { 1490 return 0; 1491 } 1492 static inline void p4d_clear_huge(p4d_t *p4d) { } 1493 static inline int pud_clear_huge(pud_t *pud) 1494 { 1495 return 0; 1496 } 1497 static inline int pmd_clear_huge(pmd_t *pmd) 1498 { 1499 return 0; 1500 } 1501 static inline int p4d_free_pud_page(p4d_t *p4d, unsigned long addr) 1502 { 1503 return 0; 1504 } 1505 static inline int pud_free_pmd_page(pud_t *pud, unsigned long addr) 1506 { 1507 return 0; 1508 } 1509 static inline int pmd_free_pte_page(pmd_t *pmd, unsigned long addr) 1510 { 1511 return 0; 1512 } 1513 #endif /* CONFIG_HAVE_ARCH_HUGE_VMAP */ 1514 1515 #ifndef __HAVE_ARCH_FLUSH_PMD_TLB_RANGE 1516 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1517 /* 1518 * ARCHes with special requirements for evicting THP backing TLB entries can 1519 * implement this. Otherwise also, it can help optimize normal TLB flush in 1520 * THP regime. Stock flush_tlb_range() typically has optimization to nuke the 1521 * entire TLB if flush span is greater than a threshold, which will 1522 * likely be true for a single huge page. Thus a single THP flush will 1523 * invalidate the entire TLB which is not desirable. 1524 * e.g. see arch/arc: flush_pmd_tlb_range 1525 */ 1526 #define flush_pmd_tlb_range(vma, addr, end) flush_tlb_range(vma, addr, end) 1527 #define flush_pud_tlb_range(vma, addr, end) flush_tlb_range(vma, addr, end) 1528 #else 1529 #define flush_pmd_tlb_range(vma, addr, end) BUILD_BUG() 1530 #define flush_pud_tlb_range(vma, addr, end) BUILD_BUG() 1531 #endif 1532 #endif 1533 1534 struct file; 1535 int phys_mem_access_prot_allowed(struct file *file, unsigned long pfn, 1536 unsigned long size, pgprot_t *vma_prot); 1537 1538 #ifndef CONFIG_X86_ESPFIX64 1539 static inline void init_espfix_bsp(void) { } 1540 #endif 1541 1542 extern void __init pgtable_cache_init(void); 1543 1544 #ifndef __HAVE_ARCH_PFN_MODIFY_ALLOWED 1545 static inline bool pfn_modify_allowed(unsigned long pfn, pgprot_t prot) 1546 { 1547 return true; 1548 } 1549 1550 static inline bool arch_has_pfn_modify_check(void) 1551 { 1552 return false; 1553 } 1554 #endif /* !_HAVE_ARCH_PFN_MODIFY_ALLOWED */ 1555 1556 /* 1557 * Architecture PAGE_KERNEL_* fallbacks 1558 * 1559 * Some architectures don't define certain PAGE_KERNEL_* flags. This is either 1560 * because they really don't support them, or the port needs to be updated to 1561 * reflect the required functionality. Below are a set of relatively safe 1562 * fallbacks, as best effort, which we can count on in lieu of the architectures 1563 * not defining them on their own yet. 1564 */ 1565 1566 #ifndef PAGE_KERNEL_RO 1567 # define PAGE_KERNEL_RO PAGE_KERNEL 1568 #endif 1569 1570 #ifndef PAGE_KERNEL_EXEC 1571 # define PAGE_KERNEL_EXEC PAGE_KERNEL 1572 #endif 1573 1574 /* 1575 * Page Table Modification bits for pgtbl_mod_mask. 1576 * 1577 * These are used by the p?d_alloc_track*() set of functions an in the generic 1578 * vmalloc/ioremap code to track at which page-table levels entries have been 1579 * modified. Based on that the code can better decide when vmalloc and ioremap 1580 * mapping changes need to be synchronized to other page-tables in the system. 1581 */ 1582 #define __PGTBL_PGD_MODIFIED 0 1583 #define __PGTBL_P4D_MODIFIED 1 1584 #define __PGTBL_PUD_MODIFIED 2 1585 #define __PGTBL_PMD_MODIFIED 3 1586 #define __PGTBL_PTE_MODIFIED 4 1587 1588 #define PGTBL_PGD_MODIFIED BIT(__PGTBL_PGD_MODIFIED) 1589 #define PGTBL_P4D_MODIFIED BIT(__PGTBL_P4D_MODIFIED) 1590 #define PGTBL_PUD_MODIFIED BIT(__PGTBL_PUD_MODIFIED) 1591 #define PGTBL_PMD_MODIFIED BIT(__PGTBL_PMD_MODIFIED) 1592 #define PGTBL_PTE_MODIFIED BIT(__PGTBL_PTE_MODIFIED) 1593 1594 /* Page-Table Modification Mask */ 1595 typedef unsigned int pgtbl_mod_mask; 1596 1597 #endif /* !__ASSEMBLY__ */ 1598 1599 #if !defined(MAX_POSSIBLE_PHYSMEM_BITS) && !defined(CONFIG_64BIT) 1600 #ifdef CONFIG_PHYS_ADDR_T_64BIT 1601 /* 1602 * ZSMALLOC needs to know the highest PFN on 32-bit architectures 1603 * with physical address space extension, but falls back to 1604 * BITS_PER_LONG otherwise. 1605 */ 1606 #error Missing MAX_POSSIBLE_PHYSMEM_BITS definition 1607 #else 1608 #define MAX_POSSIBLE_PHYSMEM_BITS 32 1609 #endif 1610 #endif 1611 1612 #ifndef has_transparent_hugepage 1613 #define has_transparent_hugepage() IS_BUILTIN(CONFIG_TRANSPARENT_HUGEPAGE) 1614 #endif 1615 1616 #ifndef has_transparent_pud_hugepage 1617 #define has_transparent_pud_hugepage() IS_BUILTIN(CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD) 1618 #endif 1619 /* 1620 * On some architectures it depends on the mm if the p4d/pud or pmd 1621 * layer of the page table hierarchy is folded or not. 1622 */ 1623 #ifndef mm_p4d_folded 1624 #define mm_p4d_folded(mm) __is_defined(__PAGETABLE_P4D_FOLDED) 1625 #endif 1626 1627 #ifndef mm_pud_folded 1628 #define mm_pud_folded(mm) __is_defined(__PAGETABLE_PUD_FOLDED) 1629 #endif 1630 1631 #ifndef mm_pmd_folded 1632 #define mm_pmd_folded(mm) __is_defined(__PAGETABLE_PMD_FOLDED) 1633 #endif 1634 1635 #ifndef p4d_offset_lockless 1636 #define p4d_offset_lockless(pgdp, pgd, address) p4d_offset(&(pgd), address) 1637 #endif 1638 #ifndef pud_offset_lockless 1639 #define pud_offset_lockless(p4dp, p4d, address) pud_offset(&(p4d), address) 1640 #endif 1641 #ifndef pmd_offset_lockless 1642 #define pmd_offset_lockless(pudp, pud, address) pmd_offset(&(pud), address) 1643 #endif 1644 1645 /* 1646 * p?d_leaf() - true if this entry is a final mapping to a physical address. 1647 * This differs from p?d_huge() by the fact that they are always available (if 1648 * the architecture supports large pages at the appropriate level) even 1649 * if CONFIG_HUGETLB_PAGE is not defined. 1650 * Only meaningful when called on a valid entry. 1651 */ 1652 #ifndef pgd_leaf 1653 #define pgd_leaf(x) 0 1654 #endif 1655 #ifndef p4d_leaf 1656 #define p4d_leaf(x) 0 1657 #endif 1658 #ifndef pud_leaf 1659 #define pud_leaf(x) 0 1660 #endif 1661 #ifndef pmd_leaf 1662 #define pmd_leaf(x) 0 1663 #endif 1664 1665 #ifndef pgd_leaf_size 1666 #define pgd_leaf_size(x) (1ULL << PGDIR_SHIFT) 1667 #endif 1668 #ifndef p4d_leaf_size 1669 #define p4d_leaf_size(x) P4D_SIZE 1670 #endif 1671 #ifndef pud_leaf_size 1672 #define pud_leaf_size(x) PUD_SIZE 1673 #endif 1674 #ifndef pmd_leaf_size 1675 #define pmd_leaf_size(x) PMD_SIZE 1676 #endif 1677 #ifndef pte_leaf_size 1678 #define pte_leaf_size(x) PAGE_SIZE 1679 #endif 1680 1681 /* 1682 * Some architectures have MMUs that are configurable or selectable at boot 1683 * time. These lead to variable PTRS_PER_x. For statically allocated arrays it 1684 * helps to have a static maximum value. 1685 */ 1686 1687 #ifndef MAX_PTRS_PER_PTE 1688 #define MAX_PTRS_PER_PTE PTRS_PER_PTE 1689 #endif 1690 1691 #ifndef MAX_PTRS_PER_PMD 1692 #define MAX_PTRS_PER_PMD PTRS_PER_PMD 1693 #endif 1694 1695 #ifndef MAX_PTRS_PER_PUD 1696 #define MAX_PTRS_PER_PUD PTRS_PER_PUD 1697 #endif 1698 1699 #ifndef MAX_PTRS_PER_P4D 1700 #define MAX_PTRS_PER_P4D PTRS_PER_P4D 1701 #endif 1702 1703 /* description of effects of mapping type and prot in current implementation. 1704 * this is due to the limited x86 page protection hardware. The expected 1705 * behavior is in parens: 1706 * 1707 * map_type prot 1708 * PROT_NONE PROT_READ PROT_WRITE PROT_EXEC 1709 * MAP_SHARED r: (no) no r: (yes) yes r: (no) yes r: (no) yes 1710 * w: (no) no w: (no) no w: (yes) yes w: (no) no 1711 * x: (no) no x: (no) yes x: (no) yes x: (yes) yes 1712 * 1713 * MAP_PRIVATE r: (no) no r: (yes) yes r: (no) yes r: (no) yes 1714 * w: (no) no w: (no) no w: (copy) copy w: (no) no 1715 * x: (no) no x: (no) yes x: (no) yes x: (yes) yes 1716 * 1717 * On arm64, PROT_EXEC has the following behaviour for both MAP_SHARED and 1718 * MAP_PRIVATE (with Enhanced PAN supported): 1719 * r: (no) no 1720 * w: (no) no 1721 * x: (yes) yes 1722 */ 1723 #define DECLARE_VM_GET_PAGE_PROT \ 1724 pgprot_t vm_get_page_prot(unsigned long vm_flags) \ 1725 { \ 1726 return protection_map[vm_flags & \ 1727 (VM_READ | VM_WRITE | VM_EXEC | VM_SHARED)]; \ 1728 } \ 1729 EXPORT_SYMBOL(vm_get_page_prot); 1730 1731 #endif /* _LINUX_PGTABLE_H */ 1732