1*3abfaefbSLiu Ying /* SPDX-License-Identifier: GPL-2.0 */ 2*3abfaefbSLiu Ying /* 3*3abfaefbSLiu Ying * Copyright 2020,2022 NXP 4*3abfaefbSLiu Ying */ 5*3abfaefbSLiu Ying 6*3abfaefbSLiu Ying #ifndef __PHY_LVDS_H_ 7*3abfaefbSLiu Ying #define __PHY_LVDS_H_ 8*3abfaefbSLiu Ying 9*3abfaefbSLiu Ying /** 10*3abfaefbSLiu Ying * struct phy_configure_opts_lvds - LVDS configuration set 11*3abfaefbSLiu Ying * @bits_per_lane_and_dclk_cycle: Number of bits per lane per differential 12*3abfaefbSLiu Ying * clock cycle. 13*3abfaefbSLiu Ying * @differential_clk_rate: Clock rate, in Hertz, of the LVDS 14*3abfaefbSLiu Ying * differential clock. 15*3abfaefbSLiu Ying * @lanes: Number of active, consecutive, 16*3abfaefbSLiu Ying * data lanes, starting from lane 0, 17*3abfaefbSLiu Ying * used for the transmissions. 18*3abfaefbSLiu Ying * @is_slave: Boolean, true if the phy is a slave 19*3abfaefbSLiu Ying * which works together with a master 20*3abfaefbSLiu Ying * phy to support dual link transmission, 21*3abfaefbSLiu Ying * otherwise a regular phy or a master phy. 22*3abfaefbSLiu Ying * 23*3abfaefbSLiu Ying * This structure is used to represent the configuration state of a LVDS phy. 24*3abfaefbSLiu Ying */ 25*3abfaefbSLiu Ying struct phy_configure_opts_lvds { 26*3abfaefbSLiu Ying unsigned int bits_per_lane_and_dclk_cycle; 27*3abfaefbSLiu Ying unsigned long differential_clk_rate; 28*3abfaefbSLiu Ying unsigned int lanes; 29*3abfaefbSLiu Ying bool is_slave; 30*3abfaefbSLiu Ying }; 31*3abfaefbSLiu Ying 32*3abfaefbSLiu Ying #endif /* __PHY_LVDS_H_ */ 33