1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * platform data for eMMC driver 4 * 5 * Copyright (C) 2010 Renesas Solutions Corp. 6 */ 7 8 #ifndef LINUX_MMC_SH_MMCIF_H 9 #define LINUX_MMC_SH_MMCIF_H 10 11 #include <linux/io.h> 12 #include <linux/platform_device.h> 13 14 /* 15 * MMCIF : CE_CLK_CTRL [19:16] 16 * 1000 : Peripheral clock / 512 17 * 0111 : Peripheral clock / 256 18 * 0110 : Peripheral clock / 128 19 * 0101 : Peripheral clock / 64 20 * 0100 : Peripheral clock / 32 21 * 0011 : Peripheral clock / 16 22 * 0010 : Peripheral clock / 8 23 * 0001 : Peripheral clock / 4 24 * 0000 : Peripheral clock / 2 25 * 1111 : Peripheral clock (sup_pclk set '1') 26 */ 27 28 struct sh_mmcif_plat_data { 29 unsigned int slave_id_tx; /* embedded slave_id_[tr]x */ 30 unsigned int slave_id_rx; 31 u8 sup_pclk; /* 1 :SH7757, 0: SH7724/SH7372 */ 32 unsigned long caps; 33 u32 ocr; 34 }; 35 36 #define MMCIF_CE_CMD_SET 0x00000000 37 #define MMCIF_CE_ARG 0x00000008 38 #define MMCIF_CE_ARG_CMD12 0x0000000C 39 #define MMCIF_CE_CMD_CTRL 0x00000010 40 #define MMCIF_CE_BLOCK_SET 0x00000014 41 #define MMCIF_CE_CLK_CTRL 0x00000018 42 #define MMCIF_CE_BUF_ACC 0x0000001C 43 #define MMCIF_CE_RESP3 0x00000020 44 #define MMCIF_CE_RESP2 0x00000024 45 #define MMCIF_CE_RESP1 0x00000028 46 #define MMCIF_CE_RESP0 0x0000002C 47 #define MMCIF_CE_RESP_CMD12 0x00000030 48 #define MMCIF_CE_DATA 0x00000034 49 #define MMCIF_CE_INT 0x00000040 50 #define MMCIF_CE_INT_MASK 0x00000044 51 #define MMCIF_CE_HOST_STS1 0x00000048 52 #define MMCIF_CE_HOST_STS2 0x0000004C 53 #define MMCIF_CE_CLK_CTRL2 0x00000070 54 #define MMCIF_CE_VERSION 0x0000007C 55 56 /* CE_BUF_ACC */ 57 #define BUF_ACC_DMAWEN (1 << 25) 58 #define BUF_ACC_DMAREN (1 << 24) 59 #define BUF_ACC_BUSW_32 (0 << 17) 60 #define BUF_ACC_BUSW_16 (1 << 17) 61 #define BUF_ACC_ATYP (1 << 16) 62 63 /* CE_CLK_CTRL */ 64 #define CLK_ENABLE (1 << 24) /* 1: output mmc clock */ 65 #define CLK_CLEAR (0xf << 16) 66 #define CLK_SUP_PCLK (0xf << 16) 67 #define CLKDIV_4 (1 << 16) /* mmc clock frequency. 68 * n: bus clock/(2^(n+1)) */ 69 #define CLKDIV_256 (7 << 16) /* mmc clock frequency. (see above) */ 70 #define SRSPTO_256 (2 << 12) /* resp timeout */ 71 #define SRBSYTO_29 (0xf << 8) /* resp busy timeout */ 72 #define SRWDTO_29 (0xf << 4) /* read/write timeout */ 73 #define SCCSTO_29 (0xf << 0) /* ccs timeout */ 74 75 /* CE_VERSION */ 76 #define SOFT_RST_ON (1 << 31) 77 #define SOFT_RST_OFF 0 78 79 static inline u32 sh_mmcif_readl(void __iomem *addr, int reg) 80 { 81 return __raw_readl(addr + reg); 82 } 83 84 static inline void sh_mmcif_writel(void __iomem *addr, int reg, u32 val) 85 { 86 __raw_writel(val, addr + reg); 87 } 88 89 #define SH_MMCIF_BBS 512 /* boot block size */ 90 91 static inline void sh_mmcif_boot_cmd_send(void __iomem *base, 92 unsigned long cmd, unsigned long arg) 93 { 94 sh_mmcif_writel(base, MMCIF_CE_INT, 0); 95 sh_mmcif_writel(base, MMCIF_CE_ARG, arg); 96 sh_mmcif_writel(base, MMCIF_CE_CMD_SET, cmd); 97 } 98 99 static inline int sh_mmcif_boot_cmd_poll(void __iomem *base, unsigned long mask) 100 { 101 unsigned long tmp; 102 int cnt; 103 104 for (cnt = 0; cnt < 1000000; cnt++) { 105 tmp = sh_mmcif_readl(base, MMCIF_CE_INT); 106 if (tmp & mask) { 107 sh_mmcif_writel(base, MMCIF_CE_INT, tmp & ~mask); 108 return 0; 109 } 110 } 111 112 return -1; 113 } 114 115 static inline int sh_mmcif_boot_cmd(void __iomem *base, 116 unsigned long cmd, unsigned long arg) 117 { 118 sh_mmcif_boot_cmd_send(base, cmd, arg); 119 return sh_mmcif_boot_cmd_poll(base, 0x00010000); 120 } 121 122 static inline int sh_mmcif_boot_do_read_single(void __iomem *base, 123 unsigned int block_nr, 124 unsigned long *buf) 125 { 126 int k; 127 128 /* CMD13 - Status */ 129 sh_mmcif_boot_cmd(base, 0x0d400000, 0x00010000); 130 131 if (sh_mmcif_readl(base, MMCIF_CE_RESP0) != 0x0900) 132 return -1; 133 134 /* CMD17 - Read */ 135 sh_mmcif_boot_cmd(base, 0x11480000, block_nr * SH_MMCIF_BBS); 136 if (sh_mmcif_boot_cmd_poll(base, 0x00100000) < 0) 137 return -1; 138 139 for (k = 0; k < (SH_MMCIF_BBS / 4); k++) 140 buf[k] = sh_mmcif_readl(base, MMCIF_CE_DATA); 141 142 return 0; 143 } 144 145 static inline int sh_mmcif_boot_do_read(void __iomem *base, 146 unsigned long first_block, 147 unsigned long nr_blocks, 148 void *buf) 149 { 150 unsigned long k; 151 int ret = 0; 152 153 /* In data transfer mode: Set clock to Bus clock/4 (about 20Mhz) */ 154 sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL, 155 CLK_ENABLE | CLKDIV_4 | SRSPTO_256 | 156 SRBSYTO_29 | SRWDTO_29 | SCCSTO_29); 157 158 /* CMD9 - Get CSD */ 159 sh_mmcif_boot_cmd(base, 0x09806000, 0x00010000); 160 161 /* CMD7 - Select the card */ 162 sh_mmcif_boot_cmd(base, 0x07400000, 0x00010000); 163 164 /* CMD16 - Set the block size */ 165 sh_mmcif_boot_cmd(base, 0x10400000, SH_MMCIF_BBS); 166 167 for (k = 0; !ret && k < nr_blocks; k++) 168 ret = sh_mmcif_boot_do_read_single(base, first_block + k, 169 buf + (k * SH_MMCIF_BBS)); 170 171 return ret; 172 } 173 174 static inline void sh_mmcif_boot_init(void __iomem *base) 175 { 176 /* reset */ 177 sh_mmcif_writel(base, MMCIF_CE_VERSION, SOFT_RST_ON); 178 sh_mmcif_writel(base, MMCIF_CE_VERSION, SOFT_RST_OFF); 179 180 /* byte swap */ 181 sh_mmcif_writel(base, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP); 182 183 /* Set block size in MMCIF hardware */ 184 sh_mmcif_writel(base, MMCIF_CE_BLOCK_SET, SH_MMCIF_BBS); 185 186 /* Enable the clock, set it to Bus clock/256 (about 325Khz). */ 187 sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL, 188 CLK_ENABLE | CLKDIV_256 | SRSPTO_256 | 189 SRBSYTO_29 | SRWDTO_29 | SCCSTO_29); 190 191 /* CMD0 */ 192 sh_mmcif_boot_cmd(base, 0x00000040, 0); 193 194 /* CMD1 - Get OCR */ 195 do { 196 sh_mmcif_boot_cmd(base, 0x01405040, 0x40300000); /* CMD1 */ 197 } while ((sh_mmcif_readl(base, MMCIF_CE_RESP0) & 0x80000000) 198 != 0x80000000); 199 200 /* CMD2 - Get CID */ 201 sh_mmcif_boot_cmd(base, 0x02806040, 0); 202 203 /* CMD3 - Set card relative address */ 204 sh_mmcif_boot_cmd(base, 0x03400040, 0x00010000); 205 } 206 207 #endif /* LINUX_MMC_SH_MMCIF_H */ 208