1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* Driver for Realtek PCI-Express card reader 3 * 4 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. 5 * 6 * Author: 7 * Wei WANG <wei_wang@realsil.com.cn> 8 */ 9 10 #ifndef __RTSX_PCI_H 11 #define __RTSX_PCI_H 12 13 #include <linux/sched.h> 14 #include <linux/pci.h> 15 #include <linux/rtsx_common.h> 16 17 #define MAX_RW_REG_CNT 1024 18 19 #define RTSX_HCBAR 0x00 20 #define RTSX_HCBCTLR 0x04 21 #define STOP_CMD (0x01 << 28) 22 #define READ_REG_CMD 0 23 #define WRITE_REG_CMD 1 24 #define CHECK_REG_CMD 2 25 26 #define RTSX_HDBAR 0x08 27 #define RTSX_SG_INT 0x04 28 #define RTSX_SG_END 0x02 29 #define RTSX_SG_VALID 0x01 30 #define RTSX_SG_NO_OP 0x00 31 #define RTSX_SG_TRANS_DATA (0x02 << 4) 32 #define RTSX_SG_LINK_DESC (0x03 << 4) 33 #define RTSX_HDBCTLR 0x0C 34 #define SDMA_MODE 0x00 35 #define ADMA_MODE (0x02 << 26) 36 #define STOP_DMA (0x01 << 28) 37 #define TRIG_DMA (0x01 << 31) 38 39 #define RTSX_HAIMR 0x10 40 #define HAIMR_TRANS_START (0x01 << 31) 41 #define HAIMR_READ 0x00 42 #define HAIMR_WRITE (0x01 << 30) 43 #define HAIMR_READ_START (HAIMR_TRANS_START | HAIMR_READ) 44 #define HAIMR_WRITE_START (HAIMR_TRANS_START | HAIMR_WRITE) 45 #define HAIMR_TRANS_END (HAIMR_TRANS_START) 46 47 #define RTSX_BIPR 0x14 48 #define CMD_DONE_INT (1 << 31) 49 #define DATA_DONE_INT (1 << 30) 50 #define TRANS_OK_INT (1 << 29) 51 #define TRANS_FAIL_INT (1 << 28) 52 #define XD_INT (1 << 27) 53 #define MS_INT (1 << 26) 54 #define SD_INT (1 << 25) 55 #define GPIO0_INT (1 << 24) 56 #define OC_INT (1 << 23) 57 #define SD_WRITE_PROTECT (1 << 19) 58 #define XD_EXIST (1 << 18) 59 #define MS_EXIST (1 << 17) 60 #define SD_EXIST (1 << 16) 61 #define DELINK_INT GPIO0_INT 62 #define MS_OC_INT (1 << 23) 63 #define SD_OVP_INT (1 << 23) 64 #define SD_OC_INT (1 << 22) 65 66 #define CARD_INT (XD_INT | MS_INT | SD_INT) 67 #define NEED_COMPLETE_INT (DATA_DONE_INT | TRANS_OK_INT | TRANS_FAIL_INT) 68 #define RTSX_INT (CMD_DONE_INT | NEED_COMPLETE_INT | \ 69 CARD_INT | GPIO0_INT | OC_INT) 70 #define CARD_EXIST (XD_EXIST | MS_EXIST | SD_EXIST) 71 72 #define RTSX_BIER 0x18 73 #define CMD_DONE_INT_EN (1 << 31) 74 #define DATA_DONE_INT_EN (1 << 30) 75 #define TRANS_OK_INT_EN (1 << 29) 76 #define TRANS_FAIL_INT_EN (1 << 28) 77 #define XD_INT_EN (1 << 27) 78 #define MS_INT_EN (1 << 26) 79 #define SD_INT_EN (1 << 25) 80 #define GPIO0_INT_EN (1 << 24) 81 #define OC_INT_EN (1 << 23) 82 #define DELINK_INT_EN GPIO0_INT_EN 83 #define MS_OC_INT_EN (1 << 23) 84 #define SD_OVP_INT_EN (1 << 23) 85 #define SD_OC_INT_EN (1 << 22) 86 87 #define RTSX_DUM_REG 0x1C 88 89 /* 90 * macros for easy use 91 */ 92 #define rtsx_pci_writel(pcr, reg, value) \ 93 iowrite32(value, (pcr)->remap_addr + reg) 94 #define rtsx_pci_readl(pcr, reg) \ 95 ioread32((pcr)->remap_addr + reg) 96 #define rtsx_pci_writew(pcr, reg, value) \ 97 iowrite16(value, (pcr)->remap_addr + reg) 98 #define rtsx_pci_readw(pcr, reg) \ 99 ioread16((pcr)->remap_addr + reg) 100 #define rtsx_pci_writeb(pcr, reg, value) \ 101 iowrite8(value, (pcr)->remap_addr + reg) 102 #define rtsx_pci_readb(pcr, reg) \ 103 ioread8((pcr)->remap_addr + reg) 104 105 #define STATE_TRANS_NONE 0 106 #define STATE_TRANS_CMD 1 107 #define STATE_TRANS_BUF 2 108 #define STATE_TRANS_SG 3 109 110 #define TRANS_NOT_READY 0 111 #define TRANS_RESULT_OK 1 112 #define TRANS_RESULT_FAIL 2 113 #define TRANS_NO_DEVICE 3 114 115 #define RTSX_RESV_BUF_LEN 4096 116 #define HOST_CMDS_BUF_LEN 1024 117 #define HOST_SG_TBL_BUF_LEN (RTSX_RESV_BUF_LEN - HOST_CMDS_BUF_LEN) 118 #define HOST_SG_TBL_ITEMS (HOST_SG_TBL_BUF_LEN / 8) 119 #define MAX_SG_ITEM_LEN 0x80000 120 #define HOST_TO_DEVICE 0 121 #define DEVICE_TO_HOST 1 122 123 #define OUTPUT_3V3 0 124 #define OUTPUT_1V8 1 125 126 #define RTSX_PHASE_MAX 32 127 #define RX_TUNING_CNT 3 128 129 #define MS_CFG 0xFD40 130 #define SAMPLE_TIME_RISING 0x00 131 #define SAMPLE_TIME_FALLING 0x80 132 #define PUSH_TIME_DEFAULT 0x00 133 #define PUSH_TIME_ODD 0x40 134 #define NO_EXTEND_TOGGLE 0x00 135 #define EXTEND_TOGGLE_CHK 0x20 136 #define MS_BUS_WIDTH_1 0x00 137 #define MS_BUS_WIDTH_4 0x10 138 #define MS_BUS_WIDTH_8 0x18 139 #define MS_2K_SECTOR_MODE 0x04 140 #define MS_512_SECTOR_MODE 0x00 141 #define MS_TOGGLE_TIMEOUT_EN 0x00 142 #define MS_TOGGLE_TIMEOUT_DISEN 0x01 143 #define MS_NO_CHECK_INT 0x02 144 #define MS_TPC 0xFD41 145 #define MS_TRANS_CFG 0xFD42 146 #define WAIT_INT 0x80 147 #define NO_WAIT_INT 0x00 148 #define NO_AUTO_READ_INT_REG 0x00 149 #define AUTO_READ_INT_REG 0x40 150 #define MS_CRC16_ERR 0x20 151 #define MS_RDY_TIMEOUT 0x10 152 #define MS_INT_CMDNK 0x08 153 #define MS_INT_BREQ 0x04 154 #define MS_INT_ERR 0x02 155 #define MS_INT_CED 0x01 156 #define MS_TRANSFER 0xFD43 157 #define MS_TRANSFER_START 0x80 158 #define MS_TRANSFER_END 0x40 159 #define MS_TRANSFER_ERR 0x20 160 #define MS_BS_STATE 0x10 161 #define MS_TM_READ_BYTES 0x00 162 #define MS_TM_NORMAL_READ 0x01 163 #define MS_TM_WRITE_BYTES 0x04 164 #define MS_TM_NORMAL_WRITE 0x05 165 #define MS_TM_AUTO_READ 0x08 166 #define MS_TM_AUTO_WRITE 0x0C 167 #define MS_INT_REG 0xFD44 168 #define MS_BYTE_CNT 0xFD45 169 #define MS_SECTOR_CNT_L 0xFD46 170 #define MS_SECTOR_CNT_H 0xFD47 171 #define MS_DBUS_H 0xFD48 172 173 #define SD_CFG1 0xFDA0 174 #define SD_CLK_DIVIDE_0 0x00 175 #define SD_CLK_DIVIDE_256 0xC0 176 #define SD_CLK_DIVIDE_128 0x80 177 #define SD_BUS_WIDTH_1BIT 0x00 178 #define SD_BUS_WIDTH_4BIT 0x01 179 #define SD_BUS_WIDTH_8BIT 0x02 180 #define SD_ASYNC_FIFO_NOT_RST 0x10 181 #define SD_20_MODE 0x00 182 #define SD_DDR_MODE 0x04 183 #define SD_30_MODE 0x08 184 #define SD_CLK_DIVIDE_MASK 0xC0 185 #define SD_MODE_SELECT_MASK 0x0C 186 #define SD_CFG2 0xFDA1 187 #define SD_CALCULATE_CRC7 0x00 188 #define SD_NO_CALCULATE_CRC7 0x80 189 #define SD_CHECK_CRC16 0x00 190 #define SD_NO_CHECK_CRC16 0x40 191 #define SD_NO_CHECK_WAIT_CRC_TO 0x20 192 #define SD_WAIT_BUSY_END 0x08 193 #define SD_NO_WAIT_BUSY_END 0x00 194 #define SD_CHECK_CRC7 0x00 195 #define SD_NO_CHECK_CRC7 0x04 196 #define SD_RSP_LEN_0 0x00 197 #define SD_RSP_LEN_6 0x01 198 #define SD_RSP_LEN_17 0x02 199 #define SD_RSP_TYPE_R0 0x04 200 #define SD_RSP_TYPE_R1 0x01 201 #define SD_RSP_TYPE_R1b 0x09 202 #define SD_RSP_TYPE_R2 0x02 203 #define SD_RSP_TYPE_R3 0x05 204 #define SD_RSP_TYPE_R4 0x05 205 #define SD_RSP_TYPE_R5 0x01 206 #define SD_RSP_TYPE_R6 0x01 207 #define SD_RSP_TYPE_R7 0x01 208 #define SD_CFG3 0xFDA2 209 #define SD30_CLK_END_EN 0x10 210 #define SD_RSP_80CLK_TIMEOUT_EN 0x01 211 212 #define SD_STAT1 0xFDA3 213 #define SD_CRC7_ERR 0x80 214 #define SD_CRC16_ERR 0x40 215 #define SD_CRC_WRITE_ERR 0x20 216 #define SD_CRC_WRITE_ERR_MASK 0x1C 217 #define GET_CRC_TIME_OUT 0x02 218 #define SD_TUNING_COMPARE_ERR 0x01 219 #define SD_STAT2 0xFDA4 220 #define SD_RSP_80CLK_TIMEOUT 0x01 221 222 #define SD_BUS_STAT 0xFDA5 223 #define SD_CLK_TOGGLE_EN 0x80 224 #define SD_CLK_FORCE_STOP 0x40 225 #define SD_DAT3_STATUS 0x10 226 #define SD_DAT2_STATUS 0x08 227 #define SD_DAT1_STATUS 0x04 228 #define SD_DAT0_STATUS 0x02 229 #define SD_CMD_STATUS 0x01 230 #define SD_PAD_CTL 0xFDA6 231 #define SD_IO_USING_1V8 0x80 232 #define SD_IO_USING_3V3 0x7F 233 #define TYPE_A_DRIVING 0x00 234 #define TYPE_B_DRIVING 0x01 235 #define TYPE_C_DRIVING 0x02 236 #define TYPE_D_DRIVING 0x03 237 #define SD_SAMPLE_POINT_CTL 0xFDA7 238 #define DDR_FIX_RX_DAT 0x00 239 #define DDR_VAR_RX_DAT 0x80 240 #define DDR_FIX_RX_DAT_EDGE 0x00 241 #define DDR_FIX_RX_DAT_14_DELAY 0x40 242 #define DDR_FIX_RX_CMD 0x00 243 #define DDR_VAR_RX_CMD 0x20 244 #define DDR_FIX_RX_CMD_POS_EDGE 0x00 245 #define DDR_FIX_RX_CMD_14_DELAY 0x10 246 #define SD20_RX_POS_EDGE 0x00 247 #define SD20_RX_14_DELAY 0x08 248 #define SD20_RX_SEL_MASK 0x08 249 #define SD_PUSH_POINT_CTL 0xFDA8 250 #define DDR_FIX_TX_CMD_DAT 0x00 251 #define DDR_VAR_TX_CMD_DAT 0x80 252 #define DDR_FIX_TX_DAT_14_TSU 0x00 253 #define DDR_FIX_TX_DAT_12_TSU 0x40 254 #define DDR_FIX_TX_CMD_NEG_EDGE 0x00 255 #define DDR_FIX_TX_CMD_14_AHEAD 0x20 256 #define SD20_TX_NEG_EDGE 0x00 257 #define SD20_TX_14_AHEAD 0x10 258 #define SD20_TX_SEL_MASK 0x10 259 #define DDR_VAR_SDCLK_POL_SWAP 0x01 260 #define SD_CMD0 0xFDA9 261 #define SD_CMD_START 0x40 262 #define SD_CMD1 0xFDAA 263 #define SD_CMD2 0xFDAB 264 #define SD_CMD3 0xFDAC 265 #define SD_CMD4 0xFDAD 266 #define SD_CMD5 0xFDAE 267 #define SD_BYTE_CNT_L 0xFDAF 268 #define SD_BYTE_CNT_H 0xFDB0 269 #define SD_BLOCK_CNT_L 0xFDB1 270 #define SD_BLOCK_CNT_H 0xFDB2 271 #define SD_TRANSFER 0xFDB3 272 #define SD_TRANSFER_START 0x80 273 #define SD_TRANSFER_END 0x40 274 #define SD_STAT_IDLE 0x20 275 #define SD_TRANSFER_ERR 0x10 276 #define SD_TM_NORMAL_WRITE 0x00 277 #define SD_TM_AUTO_WRITE_3 0x01 278 #define SD_TM_AUTO_WRITE_4 0x02 279 #define SD_TM_AUTO_READ_3 0x05 280 #define SD_TM_AUTO_READ_4 0x06 281 #define SD_TM_CMD_RSP 0x08 282 #define SD_TM_AUTO_WRITE_1 0x09 283 #define SD_TM_AUTO_WRITE_2 0x0A 284 #define SD_TM_NORMAL_READ 0x0C 285 #define SD_TM_AUTO_READ_1 0x0D 286 #define SD_TM_AUTO_READ_2 0x0E 287 #define SD_TM_AUTO_TUNING 0x0F 288 #define SD_CMD_STATE 0xFDB5 289 #define SD_CMD_IDLE 0x80 290 291 #define SD_DATA_STATE 0xFDB6 292 #define SD_DATA_IDLE 0x80 293 #define REG_SD_STOP_SDCLK_CFG 0xFDB8 294 #define SD30_CLK_STOP_CFG_EN 0x04 295 #define SD30_CLK_STOP_CFG1 0x02 296 #define SD30_CLK_STOP_CFG0 0x01 297 #define REG_PRE_RW_MODE 0xFD70 298 #define EN_INFINITE_MODE 0x01 299 #define REG_CRC_DUMMY_0 0xFD71 300 #define CFG_SD_POW_AUTO_PD (1<<0) 301 302 #define SRCTL 0xFC13 303 304 #define DCM_DRP_CTL 0xFC23 305 #define DCM_RESET 0x08 306 #define DCM_LOCKED 0x04 307 #define DCM_208M 0x00 308 #define DCM_TX 0x01 309 #define DCM_RX 0x02 310 #define DCM_DRP_TRIG 0xFC24 311 #define DRP_START 0x80 312 #define DRP_DONE 0x40 313 #define DCM_DRP_CFG 0xFC25 314 #define DRP_WRITE 0x80 315 #define DRP_READ 0x00 316 #define DCM_WRITE_ADDRESS_50 0x50 317 #define DCM_WRITE_ADDRESS_51 0x51 318 #define DCM_READ_ADDRESS_00 0x00 319 #define DCM_READ_ADDRESS_51 0x51 320 #define DCM_DRP_WR_DATA_L 0xFC26 321 #define DCM_DRP_WR_DATA_H 0xFC27 322 #define DCM_DRP_RD_DATA_L 0xFC28 323 #define DCM_DRP_RD_DATA_H 0xFC29 324 #define SD_VPCLK0_CTL 0xFC2A 325 #define SD_VPCLK1_CTL 0xFC2B 326 #define PHASE_SELECT_MASK 0x1F 327 #define SD_DCMPS0_CTL 0xFC2C 328 #define SD_DCMPS1_CTL 0xFC2D 329 #define SD_VPTX_CTL SD_VPCLK0_CTL 330 #define SD_VPRX_CTL SD_VPCLK1_CTL 331 #define PHASE_CHANGE 0x80 332 #define PHASE_NOT_RESET 0x40 333 #define SD_DCMPS_TX_CTL SD_DCMPS0_CTL 334 #define SD_DCMPS_RX_CTL SD_DCMPS1_CTL 335 #define DCMPS_CHANGE 0x80 336 #define DCMPS_CHANGE_DONE 0x40 337 #define DCMPS_ERROR 0x20 338 #define DCMPS_CURRENT_PHASE 0x1F 339 #define CARD_CLK_SOURCE 0xFC2E 340 #define CRC_FIX_CLK (0x00 << 0) 341 #define CRC_VAR_CLK0 (0x01 << 0) 342 #define CRC_VAR_CLK1 (0x02 << 0) 343 #define SD30_FIX_CLK (0x00 << 2) 344 #define SD30_VAR_CLK0 (0x01 << 2) 345 #define SD30_VAR_CLK1 (0x02 << 2) 346 #define SAMPLE_FIX_CLK (0x00 << 4) 347 #define SAMPLE_VAR_CLK0 (0x01 << 4) 348 #define SAMPLE_VAR_CLK1 (0x02 << 4) 349 #define CARD_PWR_CTL 0xFD50 350 #define PMOS_STRG_MASK 0x10 351 #define PMOS_STRG_800mA 0x10 352 #define PMOS_STRG_400mA 0x00 353 #define SD_POWER_OFF 0x03 354 #define SD_PARTIAL_POWER_ON 0x01 355 #define SD_POWER_ON 0x00 356 #define SD_POWER_MASK 0x03 357 #define MS_POWER_OFF 0x0C 358 #define MS_PARTIAL_POWER_ON 0x04 359 #define MS_POWER_ON 0x00 360 #define MS_POWER_MASK 0x0C 361 #define BPP_POWER_OFF 0x0F 362 #define BPP_POWER_5_PERCENT_ON 0x0E 363 #define BPP_POWER_10_PERCENT_ON 0x0C 364 #define BPP_POWER_15_PERCENT_ON 0x08 365 #define BPP_POWER_ON 0x00 366 #define BPP_POWER_MASK 0x0F 367 #define SD_VCC_PARTIAL_POWER_ON 0x02 368 #define SD_VCC_POWER_ON 0x00 369 #define CARD_CLK_SWITCH 0xFD51 370 #define RTL8411B_PACKAGE_MODE 0xFD51 371 #define CARD_SHARE_MODE 0xFD52 372 #define CARD_SHARE_MASK 0x0F 373 #define CARD_SHARE_MULTI_LUN 0x00 374 #define CARD_SHARE_NORMAL 0x00 375 #define CARD_SHARE_48_SD 0x04 376 #define CARD_SHARE_48_MS 0x08 377 #define CARD_SHARE_BAROSSA_SD 0x01 378 #define CARD_SHARE_BAROSSA_MS 0x02 379 #define CARD_DRIVE_SEL 0xFD53 380 #define MS_DRIVE_8mA (0x01 << 6) 381 #define MMC_DRIVE_8mA (0x01 << 4) 382 #define XD_DRIVE_8mA (0x01 << 2) 383 #define GPIO_DRIVE_8mA 0x01 384 #define RTS5209_CARD_DRIVE_DEFAULT (MS_DRIVE_8mA | MMC_DRIVE_8mA |\ 385 XD_DRIVE_8mA | GPIO_DRIVE_8mA) 386 #define RTL8411_CARD_DRIVE_DEFAULT (MS_DRIVE_8mA | MMC_DRIVE_8mA |\ 387 XD_DRIVE_8mA) 388 #define RTSX_CARD_DRIVE_DEFAULT (MS_DRIVE_8mA | GPIO_DRIVE_8mA) 389 390 #define CARD_STOP 0xFD54 391 #define SPI_STOP 0x01 392 #define XD_STOP 0x02 393 #define SD_STOP 0x04 394 #define MS_STOP 0x08 395 #define SPI_CLR_ERR 0x10 396 #define XD_CLR_ERR 0x20 397 #define SD_CLR_ERR 0x40 398 #define MS_CLR_ERR 0x80 399 #define CARD_OE 0xFD55 400 #define SD_OUTPUT_EN 0x04 401 #define MS_OUTPUT_EN 0x08 402 #define CARD_AUTO_BLINK 0xFD56 403 #define CARD_GPIO_DIR 0xFD57 404 #define CARD_GPIO 0xFD58 405 #define CARD_DATA_SOURCE 0xFD5B 406 #define PINGPONG_BUFFER 0x01 407 #define RING_BUFFER 0x00 408 #define SD30_CLK_DRIVE_SEL 0xFD5A 409 #define DRIVER_TYPE_A 0x05 410 #define DRIVER_TYPE_B 0x03 411 #define DRIVER_TYPE_C 0x02 412 #define DRIVER_TYPE_D 0x01 413 #define CARD_SELECT 0xFD5C 414 #define SD_MOD_SEL 2 415 #define MS_MOD_SEL 3 416 #define SD30_DRIVE_SEL 0xFD5E 417 #define CFG_DRIVER_TYPE_A 0x02 418 #define CFG_DRIVER_TYPE_B 0x03 419 #define CFG_DRIVER_TYPE_C 0x01 420 #define CFG_DRIVER_TYPE_D 0x00 421 #define SD30_CMD_DRIVE_SEL 0xFD5E 422 #define SD30_DAT_DRIVE_SEL 0xFD5F 423 #define CARD_CLK_EN 0xFD69 424 #define SD_CLK_EN 0x04 425 #define MS_CLK_EN 0x08 426 #define SD40_CLK_EN 0x10 427 #define SDIO_CTRL 0xFD6B 428 #define CD_PAD_CTL 0xFD73 429 #define CD_DISABLE_MASK 0x07 430 #define MS_CD_DISABLE 0x04 431 #define SD_CD_DISABLE 0x02 432 #define XD_CD_DISABLE 0x01 433 #define CD_DISABLE 0x07 434 #define CD_ENABLE 0x00 435 #define MS_CD_EN_ONLY 0x03 436 #define SD_CD_EN_ONLY 0x05 437 #define XD_CD_EN_ONLY 0x06 438 #define FORCE_CD_LOW_MASK 0x38 439 #define FORCE_CD_XD_LOW 0x08 440 #define FORCE_CD_SD_LOW 0x10 441 #define FORCE_CD_MS_LOW 0x20 442 #define CD_AUTO_DISABLE 0x40 443 #define FPDCTL 0xFC00 444 #define SSC_POWER_DOWN 0x01 445 #define SD_OC_POWER_DOWN 0x02 446 #define ALL_POWER_DOWN 0x03 447 #define OC_POWER_DOWN 0x02 448 #define PDINFO 0xFC01 449 450 #define CLK_CTL 0xFC02 451 #define CHANGE_CLK 0x01 452 #define CLK_LOW_FREQ 0x01 453 454 #define CLK_DIV 0xFC03 455 #define CLK_DIV_1 0x01 456 #define CLK_DIV_2 0x02 457 #define CLK_DIV_4 0x03 458 #define CLK_DIV_8 0x04 459 #define CLK_SEL 0xFC04 460 461 #define SSC_DIV_N_0 0xFC0F 462 #define SSC_DIV_N_1 0xFC10 463 #define SSC_CTL1 0xFC11 464 #define SSC_RSTB 0x80 465 #define SSC_8X_EN 0x40 466 #define SSC_FIX_FRAC 0x20 467 #define SSC_SEL_1M 0x00 468 #define SSC_SEL_2M 0x08 469 #define SSC_SEL_4M 0x10 470 #define SSC_SEL_8M 0x18 471 #define SSC_CTL2 0xFC12 472 #define SSC_DEPTH_MASK 0x07 473 #define SSC_DEPTH_DISALBE 0x00 474 #define SSC_DEPTH_4M 0x01 475 #define SSC_DEPTH_2M 0x02 476 #define SSC_DEPTH_1M 0x03 477 #define SSC_DEPTH_500K 0x04 478 #define SSC_DEPTH_250K 0x05 479 #define RCCTL 0xFC14 480 481 #define FPGA_PULL_CTL 0xFC1D 482 #define OLT_LED_CTL 0xFC1E 483 #define LED_SHINE_MASK 0x08 484 #define LED_SHINE_EN 0x08 485 #define LED_SHINE_DISABLE 0x00 486 #define GPIO_CTL 0xFC1F 487 488 #define LDO_CTL 0xFC1E 489 #define BPP_ASIC_1V7 0x00 490 #define BPP_ASIC_1V8 0x01 491 #define BPP_ASIC_1V9 0x02 492 #define BPP_ASIC_2V0 0x03 493 #define BPP_ASIC_2V7 0x04 494 #define BPP_ASIC_2V8 0x05 495 #define BPP_ASIC_3V2 0x06 496 #define BPP_ASIC_3V3 0x07 497 #define BPP_REG_TUNED18 0x07 498 #define BPP_TUNED18_SHIFT_8402 5 499 #define BPP_TUNED18_SHIFT_8411 4 500 #define BPP_PAD_MASK 0x04 501 #define BPP_PAD_3V3 0x04 502 #define BPP_PAD_1V8 0x00 503 #define BPP_LDO_POWB 0x03 504 #define BPP_LDO_ON 0x00 505 #define BPP_LDO_SUSPEND 0x02 506 #define BPP_LDO_OFF 0x03 507 #define EFUSE_CTL 0xFC30 508 #define EFUSE_ADD 0xFC31 509 #define SYS_VER 0xFC32 510 #define EFUSE_DATAL 0xFC34 511 #define EFUSE_DATAH 0xFC35 512 513 #define CARD_PULL_CTL1 0xFD60 514 #define CARD_PULL_CTL2 0xFD61 515 #define CARD_PULL_CTL3 0xFD62 516 #define CARD_PULL_CTL4 0xFD63 517 #define CARD_PULL_CTL5 0xFD64 518 #define CARD_PULL_CTL6 0xFD65 519 520 /* PCI Express Related Registers */ 521 #define IRQEN0 0xFE20 522 #define IRQSTAT0 0xFE21 523 #define DMA_DONE_INT 0x80 524 #define SUSPEND_INT 0x40 525 #define LINK_RDY_INT 0x20 526 #define LINK_DOWN_INT 0x10 527 #define IRQEN1 0xFE22 528 #define IRQSTAT1 0xFE23 529 #define TLPRIEN 0xFE24 530 #define TLPRISTAT 0xFE25 531 #define TLPTIEN 0xFE26 532 #define TLPTISTAT 0xFE27 533 #define DMATC0 0xFE28 534 #define DMATC1 0xFE29 535 #define DMATC2 0xFE2A 536 #define DMATC3 0xFE2B 537 #define DMACTL 0xFE2C 538 #define DMA_RST 0x80 539 #define DMA_BUSY 0x04 540 #define DMA_DIR_TO_CARD 0x00 541 #define DMA_DIR_FROM_CARD 0x02 542 #define DMA_EN 0x01 543 #define DMA_128 (0 << 4) 544 #define DMA_256 (1 << 4) 545 #define DMA_512 (2 << 4) 546 #define DMA_1024 (3 << 4) 547 #define DMA_PACK_SIZE_MASK 0x30 548 #define BCTL 0xFE2D 549 #define RBBC0 0xFE2E 550 #define RBBC1 0xFE2F 551 #define RBDAT 0xFE30 552 #define RBCTL 0xFE34 553 #define U_AUTO_DMA_EN_MASK 0x20 554 #define U_AUTO_DMA_DISABLE 0x00 555 #define RB_FLUSH 0x80 556 #define CFGADDR0 0xFE35 557 #define CFGADDR1 0xFE36 558 #define CFGDATA0 0xFE37 559 #define CFGDATA1 0xFE38 560 #define CFGDATA2 0xFE39 561 #define CFGDATA3 0xFE3A 562 #define CFGRWCTL 0xFE3B 563 #define PHYRWCTL 0xFE3C 564 #define PHYDATA0 0xFE3D 565 #define PHYDATA1 0xFE3E 566 #define PHYADDR 0xFE3F 567 #define MSGRXDATA0 0xFE40 568 #define MSGRXDATA1 0xFE41 569 #define MSGRXDATA2 0xFE42 570 #define MSGRXDATA3 0xFE43 571 #define MSGTXDATA0 0xFE44 572 #define MSGTXDATA1 0xFE45 573 #define MSGTXDATA2 0xFE46 574 #define MSGTXDATA3 0xFE47 575 #define MSGTXCTL 0xFE48 576 #define LTR_CTL 0xFE4A 577 #define LTR_TX_EN_MASK BIT(7) 578 #define LTR_TX_EN_1 BIT(7) 579 #define LTR_TX_EN_0 0 580 #define LTR_LATENCY_MODE_MASK BIT(6) 581 #define LTR_LATENCY_MODE_HW 0 582 #define LTR_LATENCY_MODE_SW BIT(6) 583 #define OBFF_CFG 0xFE4C 584 #define OBFF_EN_MASK 0x03 585 #define OBFF_DISABLE 0x00 586 587 #define CDRESUMECTL 0xFE52 588 #define CDGW 0xFE53 589 #define WAKE_SEL_CTL 0xFE54 590 #define PCLK_CTL 0xFE55 591 #define PCLK_MODE_SEL 0x20 592 #define PME_FORCE_CTL 0xFE56 593 594 #define ASPM_FORCE_CTL 0xFE57 595 #define FORCE_ASPM_CTL0 0x10 596 #define FORCE_ASPM_CTL1 0x20 597 #define FORCE_ASPM_VAL_MASK 0x03 598 #define FORCE_ASPM_L1_EN 0x02 599 #define FORCE_ASPM_L0_EN 0x01 600 #define FORCE_ASPM_NO_ASPM 0x00 601 #define PM_CLK_FORCE_CTL 0xFE58 602 #define CLK_PM_EN 0x01 603 #define FUNC_FORCE_CTL 0xFE59 604 #define FUNC_FORCE_UPME_XMT_DBG 0x02 605 #define PERST_GLITCH_WIDTH 0xFE5C 606 #define CHANGE_LINK_STATE 0xFE5B 607 #define RESET_LOAD_REG 0xFE5E 608 #define EFUSE_CONTENT 0xFE5F 609 #define HOST_SLEEP_STATE 0xFE60 610 #define HOST_ENTER_S1 1 611 #define HOST_ENTER_S3 2 612 613 #define SDIO_CFG 0xFE70 614 #define PM_EVENT_DEBUG 0xFE71 615 #define PME_DEBUG_0 0x08 616 #define NFTS_TX_CTRL 0xFE72 617 618 #define PWR_GATE_CTRL 0xFE75 619 #define PWR_GATE_EN 0x01 620 #define LDO3318_PWR_MASK 0x06 621 #define LDO_ON 0x00 622 #define LDO_SUSPEND 0x04 623 #define LDO_OFF 0x06 624 #define PWD_SUSPEND_EN 0xFE76 625 #define LDO_PWR_SEL 0xFE78 626 627 #define L1SUB_CONFIG1 0xFE8D 628 #define AUX_CLK_ACTIVE_SEL_MASK 0x01 629 #define MAC_CKSW_DONE 0x00 630 #define L1SUB_CONFIG2 0xFE8E 631 #define L1SUB_AUTO_CFG 0x02 632 #define L1SUB_CONFIG3 0xFE8F 633 #define L1OFF_MBIAS2_EN_5250 BIT(7) 634 635 #define DUMMY_REG_RESET_0 0xFE90 636 #define IC_VERSION_MASK 0x0F 637 638 #define REG_VREF 0xFE97 639 #define PWD_SUSPND_EN 0x10 640 #define RTS5260_DMA_RST_CTL_0 0xFEBF 641 #define RTS5260_DMA_RST 0x80 642 #define RTS5260_ADMA3_RST 0x40 643 #define AUTOLOAD_CFG_BASE 0xFF00 644 #define RELINK_TIME_MASK 0x01 645 #define PETXCFG 0xFF03 646 #define FORCE_CLKREQ_DELINK_MASK BIT(7) 647 #define FORCE_CLKREQ_LOW 0x80 648 #define FORCE_CLKREQ_HIGH 0x00 649 650 #define PM_CTRL1 0xFF44 651 #define CD_RESUME_EN_MASK 0xF0 652 653 #define PM_CTRL2 0xFF45 654 #define PM_CTRL3 0xFF46 655 #define SDIO_SEND_PME_EN 0x80 656 #define FORCE_RC_MODE_ON 0x40 657 #define FORCE_RX50_LINK_ON 0x20 658 #define D3_DELINK_MODE_EN 0x10 659 #define USE_PESRTB_CTL_DELINK 0x08 660 #define DELAY_PIN_WAKE 0x04 661 #define RESET_PIN_WAKE 0x02 662 #define PM_WAKE_EN 0x01 663 #define PM_CTRL4 0xFF47 664 665 /* FW config info register */ 666 #define RTS5261_FW_CFG_INFO0 0xFF50 667 #define RTS5261_FW_EXPRESS_TEST_MASK (0x01 << 0) 668 #define RTS5261_FW_EA_MODE_MASK (0x01 << 5) 669 #define RTS5261_FW_CFG0 0xFF54 670 #define RTS5261_FW_ENTER_EXPRESS (0x01 << 0) 671 672 #define RTS5261_FW_CFG1 0xFF55 673 #define RTS5261_SYS_CLK_SEL_MCU_CLK (0x01 << 7) 674 #define RTS5261_CRC_CLK_SEL_MCU_CLK (0x01 << 6) 675 #define RTS5261_FAKE_MCU_CLOCK_GATING (0x01 << 5) 676 #define RTS5261_MCU_BUS_SEL_MASK (0x01 << 4) 677 #define RTS5261_MCU_CLOCK_SEL_MASK (0x03 << 2) 678 #define RTS5261_MCU_CLOCK_SEL_16M (0x01 << 2) 679 #define RTS5261_MCU_CLOCK_GATING (0x01 << 1) 680 #define RTS5261_DRIVER_ENABLE_FW (0x01 << 0) 681 682 #define REG_CFG_OOBS_OFF_TIMER 0xFEA6 683 #define REG_CFG_OOBS_ON_TIMER 0xFEA7 684 #define REG_CFG_VCM_ON_TIMER 0xFEA8 685 #define REG_CFG_OOBS_POLLING 0xFEA9 686 687 /* Memory mapping */ 688 #define SRAM_BASE 0xE600 689 #define RBUF_BASE 0xF400 690 #define PPBUF_BASE1 0xF800 691 #define PPBUF_BASE2 0xFA00 692 #define IMAGE_FLAG_ADDR0 0xCE80 693 #define IMAGE_FLAG_ADDR1 0xCE81 694 695 #define RREF_CFG 0xFF6C 696 #define RREF_VBGSEL_MASK 0x38 697 #define RREF_VBGSEL_1V25 0x28 698 699 #define OOBS_CONFIG 0xFF6E 700 #define OOBS_AUTOK_DIS 0x80 701 #define OOBS_VAL_MASK 0x1F 702 703 #define LDO_DV18_CFG 0xFF70 704 #define LDO_DV18_SR_MASK 0xC0 705 #define LDO_DV18_SR_DF 0x40 706 #define DV331812_MASK 0x70 707 #define DV331812_33 0x70 708 #define DV331812_17 0x30 709 710 #define LDO_CONFIG2 0xFF71 711 #define LDO_D3318_MASK 0x07 712 #define LDO_D3318_33V 0x07 713 #define LDO_D3318_18V 0x02 714 #define DV331812_VDD1 0x04 715 #define DV331812_POWERON 0x08 716 #define DV331812_POWEROFF 0x00 717 718 #define LDO_VCC_CFG0 0xFF72 719 #define LDO_VCC_LMTVTH_MASK 0x30 720 #define LDO_VCC_LMTVTH_2A 0x10 721 /*RTS5260*/ 722 #define RTS5260_DVCC_TUNE_MASK 0x70 723 #define RTS5260_DVCC_33 0x70 724 725 /*RTS5261*/ 726 #define RTS5261_LDO1_CFG0 0xFF72 727 #define RTS5261_LDO1_OCP_THD_MASK (0x07 << 5) 728 #define RTS5261_LDO1_OCP_EN (0x01 << 4) 729 #define RTS5261_LDO1_OCP_LMT_THD_MASK (0x03 << 2) 730 #define RTS5261_LDO1_OCP_LMT_EN (0x01 << 1) 731 732 #define LDO_VCC_CFG1 0xFF73 733 #define LDO_VCC_REF_TUNE_MASK 0x30 734 #define LDO_VCC_REF_1V2 0x20 735 #define LDO_VCC_TUNE_MASK 0x07 736 #define LDO_VCC_1V8 0x04 737 #define LDO_VCC_3V3 0x07 738 #define LDO_VCC_LMT_EN 0x08 739 /*RTS5260*/ 740 #define LDO_POW_SDVDD1_MASK 0x08 741 #define LDO_POW_SDVDD1_ON 0x08 742 #define LDO_POW_SDVDD1_OFF 0x00 743 744 #define LDO_VIO_CFG 0xFF75 745 #define LDO_VIO_SR_MASK 0xC0 746 #define LDO_VIO_SR_DF 0x40 747 #define LDO_VIO_REF_TUNE_MASK 0x30 748 #define LDO_VIO_REF_1V2 0x20 749 #define LDO_VIO_TUNE_MASK 0x07 750 #define LDO_VIO_1V7 0x03 751 #define LDO_VIO_1V8 0x04 752 #define LDO_VIO_3V3 0x07 753 754 #define LDO_DV12S_CFG 0xFF76 755 #define LDO_REF12_TUNE_MASK 0x18 756 #define LDO_REF12_TUNE_DF 0x10 757 #define LDO_D12_TUNE_MASK 0x07 758 #define LDO_D12_TUNE_DF 0x04 759 760 #define LDO_AV12S_CFG 0xFF77 761 #define LDO_AV12S_TUNE_MASK 0x07 762 #define LDO_AV12S_TUNE_DF 0x04 763 764 #define SD40_LDO_CTL1 0xFE7D 765 #define SD40_VIO_TUNE_MASK 0x70 766 #define SD40_VIO_TUNE_1V7 0x30 767 #define SD_VIO_LDO_1V8 0x40 768 #define SD_VIO_LDO_3V3 0x70 769 770 #define RTS5264_AUTOLOAD_CFG2 0xFF7D 771 #define RTS5264_CHIP_RST_N_SEL (1 << 6) 772 773 #define RTS5260_AUTOLOAD_CFG4 0xFF7F 774 #define RTS5260_MIMO_DISABLE 0x8A 775 /*RTS5261*/ 776 #define RTS5261_AUX_CLK_16M_EN (1 << 5) 777 778 #define RTS5260_REG_GPIO_CTL0 0xFC1A 779 #define RTS5260_REG_GPIO_MASK 0x01 780 #define RTS5260_REG_GPIO_ON 0x01 781 #define RTS5260_REG_GPIO_OFF 0x00 782 783 #define PWR_GLOBAL_CTRL 0xF200 784 #define PCIE_L1_2_EN 0x0C 785 #define PCIE_L1_1_EN 0x0A 786 #define PCIE_L1_0_EN 0x09 787 #define PWR_FE_CTL 0xF201 788 #define PCIE_L1_2_PD_FE_EN 0x0C 789 #define PCIE_L1_1_PD_FE_EN 0x0A 790 #define PCIE_L1_0_PD_FE_EN 0x09 791 #define CFG_PCIE_APHY_OFF_0 0xF204 792 #define CFG_PCIE_APHY_OFF_0_DEFAULT 0xBF 793 #define CFG_PCIE_APHY_OFF_1 0xF205 794 #define CFG_PCIE_APHY_OFF_1_DEFAULT 0xFF 795 #define CFG_PCIE_APHY_OFF_2 0xF206 796 #define CFG_PCIE_APHY_OFF_2_DEFAULT 0x01 797 #define CFG_PCIE_APHY_OFF_3 0xF207 798 #define CFG_PCIE_APHY_OFF_3_DEFAULT 0x00 799 #define CFG_L1_0_PCIE_MAC_RET_VALUE 0xF20C 800 #define CFG_L1_0_PCIE_DPHY_RET_VALUE 0xF20E 801 #define CFG_L1_0_SYS_RET_VALUE 0xF210 802 #define CFG_L1_0_CRC_MISC_RET_VALUE 0xF212 803 #define CFG_L1_0_CRC_SD30_RET_VALUE 0xF214 804 #define CFG_L1_0_CRC_SD40_RET_VALUE 0xF216 805 #define CFG_LP_FPWM_VALUE 0xF219 806 #define CFG_LP_FPWM_VALUE_DEFAULT 0x18 807 #define PWC_CDR 0xF253 808 #define PWC_CDR_DEFAULT 0x03 809 #define CFG_L1_0_RET_VALUE_DEFAULT 0x1B 810 #define CFG_L1_0_CRC_MISC_RET_VALUE_DEFAULT 0x0C 811 812 /* OCPCTL */ 813 #define SD_DETECT_EN 0x08 814 #define SD_OCP_INT_EN 0x04 815 #define SD_OCP_INT_CLR 0x02 816 #define SD_OC_CLR 0x01 817 818 #define SDVIO_DETECT_EN (1 << 7) 819 #define SDVIO_OCP_INT_EN (1 << 6) 820 #define SDVIO_OCP_INT_CLR (1 << 5) 821 #define SDVIO_OC_CLR (1 << 4) 822 823 /* OCPSTAT */ 824 #define SD_OCP_DETECT 0x08 825 #define SD_OC_NOW 0x04 826 #define SD_OC_EVER 0x02 827 828 #define SDVIO_OC_NOW (1 << 6) 829 #define SDVIO_OC_EVER (1 << 5) 830 831 #define REG_OCPCTL 0xFD6A 832 #define REG_OCPSTAT 0xFD6E 833 #define REG_OCPGLITCH 0xFD6C 834 #define REG_OCPPARA1 0xFD6B 835 #define REG_OCPPARA2 0xFD6D 836 837 /* rts5260 DV3318 OCP-related registers */ 838 #define REG_DV3318_OCPCTL 0xFD89 839 #define DV3318_OCP_TIME_MASK 0xF0 840 #define DV3318_DETECT_EN 0x08 841 #define DV3318_OCP_INT_EN 0x04 842 #define DV3318_OCP_INT_CLR 0x02 843 #define DV3318_OCP_CLR 0x01 844 845 #define REG_DV3318_OCPSTAT 0xFD8A 846 #define DV3318_OCP_GlITCH_TIME_MASK 0xF0 847 #define DV3318_OCP_DETECT 0x08 848 #define DV3318_OCP_NOW 0x04 849 #define DV3318_OCP_EVER 0x02 850 851 #define SD_OCP_GLITCH_MASK 0x0F 852 853 /* OCPPARA1 */ 854 #define SDVIO_OCP_TIME_60 0x00 855 #define SDVIO_OCP_TIME_100 0x10 856 #define SDVIO_OCP_TIME_200 0x20 857 #define SDVIO_OCP_TIME_400 0x30 858 #define SDVIO_OCP_TIME_600 0x40 859 #define SDVIO_OCP_TIME_800 0x50 860 #define SDVIO_OCP_TIME_1100 0x60 861 #define SDVIO_OCP_TIME_MASK 0x70 862 863 #define SD_OCP_TIME_60 0x00 864 #define SD_OCP_TIME_100 0x01 865 #define SD_OCP_TIME_200 0x02 866 #define SD_OCP_TIME_400 0x03 867 #define SD_OCP_TIME_600 0x04 868 #define SD_OCP_TIME_800 0x05 869 #define SD_OCP_TIME_1100 0x06 870 #define SD_OCP_TIME_MASK 0x07 871 872 /* OCPPARA2 */ 873 #define SDVIO_OCP_THD_190 0x00 874 #define SDVIO_OCP_THD_250 0x10 875 #define SDVIO_OCP_THD_320 0x20 876 #define SDVIO_OCP_THD_380 0x30 877 #define SDVIO_OCP_THD_440 0x40 878 #define SDVIO_OCP_THD_500 0x50 879 #define SDVIO_OCP_THD_570 0x60 880 #define SDVIO_OCP_THD_630 0x70 881 #define SDVIO_OCP_THD_MASK 0x70 882 883 #define SD_OCP_THD_450 0x00 884 #define SD_OCP_THD_550 0x01 885 #define SD_OCP_THD_650 0x02 886 #define SD_OCP_THD_750 0x03 887 #define SD_OCP_THD_850 0x04 888 #define SD_OCP_THD_950 0x05 889 #define SD_OCP_THD_1050 0x06 890 #define SD_OCP_THD_1150 0x07 891 #define SD_OCP_THD_MASK 0x07 892 893 #define SDVIO_OCP_GLITCH_MASK 0xF0 894 #define SDVIO_OCP_GLITCH_NONE 0x00 895 #define SDVIO_OCP_GLITCH_50U 0x10 896 #define SDVIO_OCP_GLITCH_100U 0x20 897 #define SDVIO_OCP_GLITCH_200U 0x30 898 #define SDVIO_OCP_GLITCH_600U 0x40 899 #define SDVIO_OCP_GLITCH_800U 0x50 900 #define SDVIO_OCP_GLITCH_1M 0x60 901 #define SDVIO_OCP_GLITCH_2M 0x70 902 #define SDVIO_OCP_GLITCH_3M 0x80 903 #define SDVIO_OCP_GLITCH_4M 0x90 904 #define SDVIO_OCP_GLIVCH_5M 0xA0 905 #define SDVIO_OCP_GLITCH_6M 0xB0 906 #define SDVIO_OCP_GLITCH_7M 0xC0 907 #define SDVIO_OCP_GLITCH_8M 0xD0 908 #define SDVIO_OCP_GLITCH_9M 0xE0 909 #define SDVIO_OCP_GLITCH_10M 0xF0 910 911 #define SD_OCP_GLITCH_MASK 0x0F 912 #define SD_OCP_GLITCH_NONE 0x00 913 #define SD_OCP_GLITCH_50U 0x01 914 #define SD_OCP_GLITCH_100U 0x02 915 #define SD_OCP_GLITCH_200U 0x03 916 #define SD_OCP_GLITCH_600U 0x04 917 #define SD_OCP_GLITCH_800U 0x05 918 #define SD_OCP_GLITCH_1M 0x06 919 #define SD_OCP_GLITCH_2M 0x07 920 #define SD_OCP_GLITCH_3M 0x08 921 #define SD_OCP_GLITCH_4M 0x09 922 #define SD_OCP_GLIVCH_5M 0x0A 923 #define SD_OCP_GLITCH_6M 0x0B 924 #define SD_OCP_GLITCH_7M 0x0C 925 #define SD_OCP_GLITCH_8M 0x0D 926 #define SD_OCP_GLITCH_9M 0x0E 927 #define SD_OCP_GLITCH_10M 0x0F 928 929 /* Phy register */ 930 #define PHY_PCR 0x00 931 #define PHY_PCR_FORCE_CODE 0xB000 932 #define PHY_PCR_OOBS_CALI_50 0x0800 933 #define PHY_PCR_OOBS_VCM_08 0x0200 934 #define PHY_PCR_OOBS_SEN_90 0x0040 935 #define PHY_PCR_RSSI_EN 0x0002 936 #define PHY_PCR_RX10K 0x0001 937 938 #define PHY_RCR0 0x01 939 #define PHY_RCR1 0x02 940 #define PHY_RCR1_ADP_TIME_4 0x0400 941 #define PHY_RCR1_VCO_COARSE 0x001F 942 #define PHY_RCR1_INIT_27S 0x0A1F 943 #define PHY_SSCCR2 0x02 944 #define PHY_SSCCR2_PLL_NCODE 0x0A00 945 #define PHY_SSCCR2_TIME0 0x001C 946 #define PHY_SSCCR2_TIME2_WIDTH 0x0003 947 948 #define PHY_RCR2 0x03 949 #define PHY_RCR2_EMPHASE_EN 0x8000 950 #define PHY_RCR2_NADJR 0x4000 951 #define PHY_RCR2_CDR_SR_2 0x0100 952 #define PHY_RCR2_FREQSEL_12 0x0040 953 #define PHY_RCR2_CDR_SC_12P 0x0010 954 #define PHY_RCR2_CALIB_LATE 0x0002 955 #define PHY_RCR2_INIT_27S 0xC152 956 #define PHY_SSCCR3 0x03 957 #define PHY_SSCCR3_STEP_IN 0x2740 958 #define PHY_SSCCR3_CHECK_DELAY 0x0008 959 #define _PHY_ANA03 0x03 960 #define _PHY_ANA03_TIMER_MAX 0x2700 961 #define _PHY_ANA03_OOBS_DEB_EN 0x0040 962 #define _PHY_CMU_DEBUG_EN 0x0008 963 964 #define PHY_RTCR 0x04 965 #define PHY_RDR 0x05 966 #define PHY_RDR_RXDSEL_1_9 0x4000 967 #define PHY_SSC_AUTO_PWD 0x0600 968 #define PHY_TCR0 0x06 969 #define PHY_TCR1 0x07 970 #define PHY_TUNE 0x08 971 #define PHY_TUNE_TUNEREF_1_0 0x4000 972 #define PHY_TUNE_VBGSEL_1252 0x0C00 973 #define PHY_TUNE_SDBUS_33 0x0200 974 #define PHY_TUNE_TUNED18 0x01C0 975 #define PHY_TUNE_TUNED12 0X0020 976 #define PHY_TUNE_TUNEA12 0x0004 977 #define PHY_TUNE_VOLTAGE_MASK 0xFC3F 978 #define PHY_TUNE_VOLTAGE_3V3 0x03C0 979 #define PHY_TUNE_D18_1V8 0x0100 980 #define PHY_TUNE_D18_1V7 0x0080 981 #define PHY_ANA08 0x08 982 #define PHY_ANA08_RX_EQ_DCGAIN 0x5000 983 #define PHY_ANA08_SEL_RX_EN 0x0400 984 #define PHY_ANA08_RX_EQ_VAL 0x03C0 985 #define PHY_ANA08_SCP 0x0020 986 #define PHY_ANA08_SEL_IPI 0x0004 987 988 #define PHY_IMR 0x09 989 #define PHY_BPCR 0x0A 990 #define PHY_BPCR_IBRXSEL 0x0400 991 #define PHY_BPCR_IBTXSEL 0x0100 992 #define PHY_BPCR_IB_FILTER 0x0080 993 #define PHY_BPCR_CMIRROR_EN 0x0040 994 995 #define PHY_BIST 0x0B 996 #define PHY_RAW_L 0x0C 997 #define PHY_RAW_H 0x0D 998 #define PHY_RAW_DATA 0x0E 999 #define PHY_HOST_CLK_CTRL 0x0F 1000 #define PHY_DMR 0x10 1001 #define PHY_BACR 0x11 1002 #define PHY_BACR_BASIC_MASK 0xFFF3 1003 #define PHY_IER 0x12 1004 #define PHY_BCSR 0x13 1005 #define PHY_BPR 0x14 1006 #define PHY_BPNR2 0x15 1007 #define PHY_BPNR 0x16 1008 #define PHY_BRNR2 0x17 1009 #define PHY_BENR 0x18 1010 #define PHY_REV 0x19 1011 #define PHY_REV_RESV 0xE000 1012 #define PHY_REV_RXIDLE_LATCHED 0x1000 1013 #define PHY_REV_P1_EN 0x0800 1014 #define PHY_REV_RXIDLE_EN 0x0400 1015 #define PHY_REV_CLKREQ_TX_EN 0x0200 1016 #define PHY_REV_CLKREQ_RX_EN 0x0100 1017 #define PHY_REV_CLKREQ_DT_1_0 0x0040 1018 #define PHY_REV_STOP_CLKRD 0x0020 1019 #define PHY_REV_RX_PWST 0x0008 1020 #define PHY_REV_STOP_CLKWR 0x0004 1021 #define _PHY_REV0 0x19 1022 #define _PHY_REV0_FILTER_OUT 0x3800 1023 #define _PHY_REV0_CDR_BYPASS_PFD 0x0100 1024 #define _PHY_REV0_CDR_RX_IDLE_BYPASS 0x0002 1025 1026 #define PHY_FLD0 0x1A 1027 #define PHY_ANA1A 0x1A 1028 #define PHY_ANA1A_TXR_LOOPBACK 0x2000 1029 #define PHY_ANA1A_RXT_BIST 0x0500 1030 #define PHY_ANA1A_TXR_BIST 0x0040 1031 #define PHY_ANA1A_REV 0x0006 1032 #define PHY_FLD0_INIT_27S 0x2546 1033 #define PHY_FLD1 0x1B 1034 #define PHY_FLD2 0x1C 1035 #define PHY_FLD3 0x1D 1036 #define PHY_FLD3_TIMER_4 0x0800 1037 #define PHY_FLD3_TIMER_6 0x0020 1038 #define PHY_FLD3_RXDELINK 0x0004 1039 #define PHY_FLD3_INIT_27S 0x0004 1040 #define PHY_ANA1D 0x1D 1041 #define PHY_ANA1D_DEBUG_ADDR 0x0004 1042 #define _PHY_FLD0 0x1D 1043 #define _PHY_FLD0_CLK_REQ_20C 0x8000 1044 #define _PHY_FLD0_RX_IDLE_EN 0x1000 1045 #define _PHY_FLD0_BIT_ERR_RSTN 0x0800 1046 #define _PHY_FLD0_BER_COUNT 0x01E0 1047 #define _PHY_FLD0_BER_TIMER 0x001E 1048 #define _PHY_FLD0_CHECK_EN 0x0001 1049 1050 #define PHY_FLD4 0x1E 1051 #define PHY_FLD4_FLDEN_SEL 0x4000 1052 #define PHY_FLD4_REQ_REF 0x2000 1053 #define PHY_FLD4_RXAMP_OFF 0x1000 1054 #define PHY_FLD4_REQ_ADDA 0x0800 1055 #define PHY_FLD4_BER_COUNT 0x00E0 1056 #define PHY_FLD4_BER_TIMER 0x000A 1057 #define PHY_FLD4_BER_CHK_EN 0x0001 1058 #define PHY_FLD4_INIT_27S 0x5C7F 1059 #define PHY_DIG1E 0x1E 1060 #define PHY_DIG1E_REV 0x4000 1061 #define PHY_DIG1E_D0_X_D1 0x1000 1062 #define PHY_DIG1E_RX_ON_HOST 0x0800 1063 #define PHY_DIG1E_RCLK_REF_HOST 0x0400 1064 #define PHY_DIG1E_RCLK_TX_EN_KEEP 0x0040 1065 #define PHY_DIG1E_RCLK_TX_TERM_KEEP 0x0020 1066 #define PHY_DIG1E_RCLK_RX_EIDLE_ON 0x0010 1067 #define PHY_DIG1E_TX_TERM_KEEP 0x0008 1068 #define PHY_DIG1E_RX_TERM_KEEP 0x0004 1069 #define PHY_DIG1E_TX_EN_KEEP 0x0002 1070 #define PHY_DIG1E_RX_EN_KEEP 0x0001 1071 #define PHY_DUM_REG 0x1F 1072 1073 #define PCR_SETTING_REG1 0x724 1074 #define PCR_SETTING_REG2 0x814 1075 #define PCR_SETTING_REG3 0x747 1076 #define PCR_SETTING_REG4 0x818 1077 #define PCR_SETTING_REG5 0x81C 1078 1079 1080 #define rtsx_pci_init_cmd(pcr) ((pcr)->ci = 0) 1081 1082 #define RTS5227_DEVICE_ID 0x5227 1083 #define RTS_MAX_TIMES_FREQ_REDUCTION 8 1084 1085 struct rtsx_pcr; 1086 1087 struct pcr_handle { 1088 struct rtsx_pcr *pcr; 1089 }; 1090 1091 struct pcr_ops { 1092 int (*write_phy)(struct rtsx_pcr *pcr, u8 addr, u16 val); 1093 int (*read_phy)(struct rtsx_pcr *pcr, u8 addr, u16 *val); 1094 int (*extra_init_hw)(struct rtsx_pcr *pcr); 1095 int (*optimize_phy)(struct rtsx_pcr *pcr); 1096 int (*turn_on_led)(struct rtsx_pcr *pcr); 1097 int (*turn_off_led)(struct rtsx_pcr *pcr); 1098 int (*enable_auto_blink)(struct rtsx_pcr *pcr); 1099 int (*disable_auto_blink)(struct rtsx_pcr *pcr); 1100 int (*card_power_on)(struct rtsx_pcr *pcr, int card); 1101 int (*card_power_off)(struct rtsx_pcr *pcr, int card); 1102 int (*switch_output_voltage)(struct rtsx_pcr *pcr, 1103 u8 voltage); 1104 unsigned int (*cd_deglitch)(struct rtsx_pcr *pcr); 1105 int (*conv_clk_and_div_n)(int clk, int dir); 1106 void (*fetch_vendor_settings)(struct rtsx_pcr *pcr); 1107 void (*force_power_down)(struct rtsx_pcr *pcr, u8 pm_state, bool runtime); 1108 void (*stop_cmd)(struct rtsx_pcr *pcr); 1109 1110 void (*set_aspm)(struct rtsx_pcr *pcr, bool enable); 1111 void (*set_l1off_cfg_sub_d0)(struct rtsx_pcr *pcr, int active); 1112 void (*enable_ocp)(struct rtsx_pcr *pcr); 1113 void (*disable_ocp)(struct rtsx_pcr *pcr); 1114 void (*init_ocp)(struct rtsx_pcr *pcr); 1115 void (*process_ocp)(struct rtsx_pcr *pcr); 1116 int (*get_ocpstat)(struct rtsx_pcr *pcr, u8 *val); 1117 void (*clear_ocpstat)(struct rtsx_pcr *pcr); 1118 }; 1119 1120 enum PDEV_STAT {PDEV_STAT_IDLE, PDEV_STAT_RUN}; 1121 enum ASPM_MODE {ASPM_MODE_CFG, ASPM_MODE_REG}; 1122 1123 #define ASPM_L1_1_EN BIT(0) 1124 #define ASPM_L1_2_EN BIT(1) 1125 #define PM_L1_1_EN BIT(2) 1126 #define PM_L1_2_EN BIT(3) 1127 #define LTR_L1SS_PWR_GATE_EN BIT(4) 1128 #define L1_SNOOZE_TEST_EN BIT(5) 1129 #define LTR_L1SS_PWR_GATE_CHECK_CARD_EN BIT(6) 1130 1131 /* 1132 * struct rtsx_cr_option - card reader option 1133 * @dev_flags: device flags 1134 * @force_clkreq_0: force clock request 1135 * @ltr_en: enable ltr mode flag 1136 * @ltr_enabled: ltr mode in configure space flag 1137 * @ltr_active: ltr mode status 1138 * @ltr_active_latency: ltr mode active latency 1139 * @ltr_idle_latency: ltr mode idle latency 1140 * @ltr_l1off_latency: ltr mode l1off latency 1141 * @l1_snooze_delay: l1 snooze delay 1142 * @ltr_l1off_sspwrgate: ltr l1off sspwrgate 1143 * @ltr_l1off_snooze_sspwrgate: ltr l1off snooze sspwrgate 1144 * @ocp_en: enable ocp flag 1145 * @sd_400mA_ocp_thd: 400mA ocp thd 1146 * @sd_800mA_ocp_thd: 800mA ocp thd 1147 */ 1148 struct rtsx_cr_option { 1149 u32 dev_flags; 1150 bool force_clkreq_0; 1151 bool ltr_en; 1152 bool ltr_enabled; 1153 bool ltr_active; 1154 u32 ltr_active_latency; 1155 u32 ltr_idle_latency; 1156 u32 ltr_l1off_latency; 1157 u32 l1_snooze_delay; 1158 u8 ltr_l1off_sspwrgate; 1159 u8 ltr_l1off_snooze_sspwrgate; 1160 bool ocp_en; 1161 u8 sd_400mA_ocp_thd; 1162 u8 sd_800mA_ocp_thd; 1163 }; 1164 1165 /* 1166 * struct rtsx_hw_param - card reader hardware param 1167 * @interrupt_en: indicate which interrutp enable 1168 * @ocp_glitch: ocp glitch time 1169 */ 1170 struct rtsx_hw_param { 1171 u32 interrupt_en; 1172 u8 ocp_glitch; 1173 }; 1174 1175 #define rtsx_set_dev_flag(cr, flag) \ 1176 ((cr)->option.dev_flags |= (flag)) 1177 #define rtsx_clear_dev_flag(cr, flag) \ 1178 ((cr)->option.dev_flags &= ~(flag)) 1179 #define rtsx_check_dev_flag(cr, flag) \ 1180 ((cr)->option.dev_flags & (flag)) 1181 1182 struct rtsx_pcr { 1183 struct pci_dev *pci; 1184 unsigned int id; 1185 struct rtsx_cr_option option; 1186 struct rtsx_hw_param hw_param; 1187 1188 /* pci resources */ 1189 unsigned long addr; 1190 void __iomem *remap_addr; 1191 int irq; 1192 1193 /* host reserved buffer */ 1194 void *rtsx_resv_buf; 1195 dma_addr_t rtsx_resv_buf_addr; 1196 1197 void *host_cmds_ptr; 1198 dma_addr_t host_cmds_addr; 1199 int ci; 1200 1201 void *host_sg_tbl_ptr; 1202 dma_addr_t host_sg_tbl_addr; 1203 int sgi; 1204 1205 u32 bier; 1206 char trans_result; 1207 1208 unsigned int card_inserted; 1209 unsigned int card_removed; 1210 unsigned int card_exist; 1211 1212 struct delayed_work carddet_work; 1213 1214 spinlock_t lock; 1215 struct mutex pcr_mutex; 1216 struct completion *done; 1217 struct completion *finish_me; 1218 1219 unsigned int cur_clock; 1220 bool remove_pci; 1221 bool msi_en; 1222 1223 #define EXTRA_CAPS_SD_SDR50 (1 << 0) 1224 #define EXTRA_CAPS_SD_SDR104 (1 << 1) 1225 #define EXTRA_CAPS_SD_DDR50 (1 << 2) 1226 #define EXTRA_CAPS_MMC_HSDDR (1 << 3) 1227 #define EXTRA_CAPS_MMC_HS200 (1 << 4) 1228 #define EXTRA_CAPS_MMC_8BIT (1 << 5) 1229 #define EXTRA_CAPS_NO_MMC (1 << 7) 1230 #define EXTRA_CAPS_SD_EXPRESS (1 << 8) 1231 u32 extra_caps; 1232 1233 #define IC_VER_A 0 1234 #define IC_VER_B 1 1235 #define IC_VER_C 2 1236 #define IC_VER_D 3 1237 u8 ic_version; 1238 1239 u8 sd30_drive_sel_1v8; 1240 u8 sd30_drive_sel_3v3; 1241 u8 card_drive_sel; 1242 #define ASPM_L1_EN 0x02 1243 u8 aspm_en; 1244 enum ASPM_MODE aspm_mode; 1245 bool aspm_enabled; 1246 1247 #define PCR_MS_PMOS (1 << 0) 1248 #define PCR_REVERSE_SOCKET (1 << 1) 1249 u32 flags; 1250 1251 u32 tx_initial_phase; 1252 u32 rx_initial_phase; 1253 1254 const u32 *sd_pull_ctl_enable_tbl; 1255 const u32 *sd_pull_ctl_disable_tbl; 1256 const u32 *ms_pull_ctl_enable_tbl; 1257 const u32 *ms_pull_ctl_disable_tbl; 1258 1259 const struct pcr_ops *ops; 1260 enum PDEV_STAT state; 1261 1262 u16 reg_pm_ctrl3; 1263 1264 int num_slots; 1265 struct rtsx_slot *slots; 1266 1267 u8 dma_error_count; 1268 u8 ocp_stat; 1269 u8 ocp_stat2; 1270 u8 ovp_stat; 1271 u8 rtd3_en; 1272 }; 1273 1274 #define PID_524A 0x524A 1275 #define PID_5249 0x5249 1276 #define PID_5250 0x5250 1277 #define PID_525A 0x525A 1278 #define PID_5260 0x5260 1279 #define PID_5261 0x5261 1280 #define PID_5228 0x5228 1281 #define PID_5264 0x5264 1282 1283 #define CHK_PCI_PID(pcr, pid) ((pcr)->pci->device == (pid)) 1284 #define PCI_VID(pcr) ((pcr)->pci->vendor) 1285 #define PCI_PID(pcr) ((pcr)->pci->device) 1286 #define is_version(pcr, pid, ver) \ 1287 (CHK_PCI_PID(pcr, pid) && (pcr)->ic_version == (ver)) 1288 #define is_version_higher_than(pcr, pid, ver) \ 1289 (CHK_PCI_PID(pcr, pid) && (pcr)->ic_version > (ver)) 1290 #define pcr_dbg(pcr, fmt, arg...) \ 1291 dev_dbg(&(pcr)->pci->dev, fmt, ##arg) 1292 1293 #define SDR104_PHASE(val) ((val) & 0xFF) 1294 #define SDR50_PHASE(val) (((val) >> 8) & 0xFF) 1295 #define DDR50_PHASE(val) (((val) >> 16) & 0xFF) 1296 #define SDR104_TX_PHASE(pcr) SDR104_PHASE((pcr)->tx_initial_phase) 1297 #define SDR50_TX_PHASE(pcr) SDR50_PHASE((pcr)->tx_initial_phase) 1298 #define DDR50_TX_PHASE(pcr) DDR50_PHASE((pcr)->tx_initial_phase) 1299 #define SDR104_RX_PHASE(pcr) SDR104_PHASE((pcr)->rx_initial_phase) 1300 #define SDR50_RX_PHASE(pcr) SDR50_PHASE((pcr)->rx_initial_phase) 1301 #define DDR50_RX_PHASE(pcr) DDR50_PHASE((pcr)->rx_initial_phase) 1302 #define SET_CLOCK_PHASE(sdr104, sdr50, ddr50) \ 1303 (((ddr50) << 16) | ((sdr50) << 8) | (sdr104)) 1304 1305 void rtsx_pci_start_run(struct rtsx_pcr *pcr); 1306 int rtsx_pci_write_register(struct rtsx_pcr *pcr, u16 addr, u8 mask, u8 data); 1307 int rtsx_pci_read_register(struct rtsx_pcr *pcr, u16 addr, u8 *data); 1308 int rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val); 1309 int rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val); 1310 void rtsx_pci_stop_cmd(struct rtsx_pcr *pcr); 1311 void rtsx_pci_add_cmd(struct rtsx_pcr *pcr, 1312 u8 cmd_type, u16 reg_addr, u8 mask, u8 data); 1313 void rtsx_pci_send_cmd_no_wait(struct rtsx_pcr *pcr); 1314 int rtsx_pci_send_cmd(struct rtsx_pcr *pcr, int timeout); 1315 int rtsx_pci_transfer_data(struct rtsx_pcr *pcr, struct scatterlist *sglist, 1316 int num_sg, bool read, int timeout); 1317 int rtsx_pci_dma_map_sg(struct rtsx_pcr *pcr, struct scatterlist *sglist, 1318 int num_sg, bool read); 1319 void rtsx_pci_dma_unmap_sg(struct rtsx_pcr *pcr, struct scatterlist *sglist, 1320 int num_sg, bool read); 1321 int rtsx_pci_dma_transfer(struct rtsx_pcr *pcr, struct scatterlist *sglist, 1322 int count, bool read, int timeout); 1323 int rtsx_pci_read_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len); 1324 int rtsx_pci_write_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len); 1325 int rtsx_pci_card_pull_ctl_enable(struct rtsx_pcr *pcr, int card); 1326 int rtsx_pci_card_pull_ctl_disable(struct rtsx_pcr *pcr, int card); 1327 int rtsx_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock, 1328 u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk); 1329 int rtsx_pci_card_power_on(struct rtsx_pcr *pcr, int card); 1330 int rtsx_pci_card_power_off(struct rtsx_pcr *pcr, int card); 1331 int rtsx_pci_card_exclusive_check(struct rtsx_pcr *pcr, int card); 1332 int rtsx_pci_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage); 1333 unsigned int rtsx_pci_card_exist(struct rtsx_pcr *pcr); 1334 void rtsx_pci_complete_unfinished_transfer(struct rtsx_pcr *pcr); 1335 1336 static inline u8 *rtsx_pci_get_cmd_data(struct rtsx_pcr *pcr) 1337 { 1338 return (u8 *)(pcr->host_cmds_ptr); 1339 } 1340 1341 static inline void rtsx_pci_write_be32(struct rtsx_pcr *pcr, u16 reg, u32 val) 1342 { 1343 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg, 0xFF, val >> 24); 1344 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg + 1, 0xFF, val >> 16); 1345 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg + 2, 0xFF, val >> 8); 1346 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg + 3, 0xFF, val); 1347 } 1348 1349 static inline int rtsx_pci_update_phy(struct rtsx_pcr *pcr, u8 addr, 1350 u16 mask, u16 append) 1351 { 1352 int err; 1353 u16 val; 1354 1355 err = rtsx_pci_read_phy_register(pcr, addr, &val); 1356 if (err < 0) 1357 return err; 1358 1359 return rtsx_pci_write_phy_register(pcr, addr, (val & mask) | append); 1360 } 1361 1362 #endif 1363