1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. 4 * 5 */ 6 7 #include <linux/platform_device.h> 8 #ifndef __LLCC_QCOM__ 9 #define __LLCC_QCOM__ 10 11 #define LLCC_CPUSS 1 12 #define LLCC_VIDSC0 2 13 #define LLCC_VIDSC1 3 14 #define LLCC_ROTATOR 4 15 #define LLCC_VOICE 5 16 #define LLCC_AUDIO 6 17 #define LLCC_MDMHPGRW 7 18 #define LLCC_MDM 8 19 #define LLCC_MODHW 9 20 #define LLCC_CMPT 10 21 #define LLCC_GPUHTW 11 22 #define LLCC_GPU 12 23 #define LLCC_MMUHWT 13 24 #define LLCC_CMPTDMA 15 25 #define LLCC_DISP 16 26 #define LLCC_VIDFW 17 27 #define LLCC_MDMHPFX 20 28 #define LLCC_MDMPNG 21 29 #define LLCC_AUDHW 22 30 #define LLCC_NPU 23 31 #define LLCC_WLHW 24 32 #define LLCC_PIMEM 25 33 #define LLCC_DRE 26 34 #define LLCC_CVP 28 35 #define LLCC_MODPE 29 36 #define LLCC_APTCM 30 37 #define LLCC_WRCACHE 31 38 #define LLCC_CVPFW 32 39 #define LLCC_CPUSS1 33 40 #define LLCC_CAMEXP0 34 41 #define LLCC_CPUMTE 35 42 #define LLCC_CPUHWT 36 43 #define LLCC_MDMCLAD2 37 44 #define LLCC_CAMEXP1 38 45 #define LLCC_CMPTHCP 39 46 #define LLCC_LCPDARE 40 47 #define LLCC_AENPU 45 48 #define LLCC_ISLAND1 46 49 #define LLCC_ISLAND2 47 50 #define LLCC_ISLAND3 48 51 #define LLCC_ISLAND4 49 52 #define LLCC_CAMEXP2 50 53 #define LLCC_CAMEXP3 51 54 #define LLCC_CAMEXP4 52 55 #define LLCC_DISP_WB 53 56 #define LLCC_DISP_1 54 57 #define LLCC_VIDVSP 64 58 59 /** 60 * struct llcc_slice_desc - Cache slice descriptor 61 * @slice_id: llcc slice id 62 * @slice_size: Size allocated for the llcc slice 63 */ 64 struct llcc_slice_desc { 65 u32 slice_id; 66 size_t slice_size; 67 }; 68 69 /** 70 * struct llcc_edac_reg_data - llcc edac registers data for each error type 71 * @name: Name of the error 72 * @synd_reg: Syndrome register address 73 * @count_status_reg: Status register address to read the error count 74 * @ways_status_reg: Status register address to read the error ways 75 * @reg_cnt: Number of registers 76 * @count_mask: Mask value to get the error count 77 * @ways_mask: Mask value to get the error ways 78 * @count_shift: Shift value to get the error count 79 * @ways_shift: Shift value to get the error ways 80 */ 81 struct llcc_edac_reg_data { 82 char *name; 83 u64 synd_reg; 84 u64 count_status_reg; 85 u64 ways_status_reg; 86 u32 reg_cnt; 87 u32 count_mask; 88 u32 ways_mask; 89 u8 count_shift; 90 u8 ways_shift; 91 }; 92 93 struct llcc_edac_reg_offset { 94 /* LLCC TRP registers */ 95 u32 trp_ecc_error_status0; 96 u32 trp_ecc_error_status1; 97 u32 trp_ecc_sb_err_syn0; 98 u32 trp_ecc_db_err_syn0; 99 u32 trp_ecc_error_cntr_clear; 100 u32 trp_interrupt_0_status; 101 u32 trp_interrupt_0_clear; 102 u32 trp_interrupt_0_enable; 103 104 /* LLCC Common registers */ 105 u32 cmn_status0; 106 u32 cmn_interrupt_0_enable; 107 u32 cmn_interrupt_2_enable; 108 109 /* LLCC DRP registers */ 110 u32 drp_ecc_error_cfg; 111 u32 drp_ecc_error_cntr_clear; 112 u32 drp_interrupt_status; 113 u32 drp_interrupt_clear; 114 u32 drp_interrupt_enable; 115 u32 drp_ecc_error_status0; 116 u32 drp_ecc_error_status1; 117 u32 drp_ecc_sb_err_syn0; 118 u32 drp_ecc_db_err_syn0; 119 }; 120 121 /** 122 * struct llcc_drv_data - Data associated with the llcc driver 123 * @regmap: regmap associated with the llcc device 124 * @bcast_regmap: regmap associated with llcc broadcast offset 125 * @cfg: pointer to the data structure for slice configuration 126 * @edac_reg_offset: Offset of the LLCC EDAC registers 127 * @lock: mutex associated with each slice 128 * @cfg_size: size of the config data table 129 * @max_slices: max slices as read from device tree 130 * @num_banks: Number of llcc banks 131 * @bitmap: Bit map to track the active slice ids 132 * @offsets: Pointer to the bank offsets array 133 * @ecc_irq: interrupt for llcc cache error detection and reporting 134 * @version: Indicates the LLCC version 135 */ 136 struct llcc_drv_data { 137 struct regmap *regmap; 138 struct regmap *bcast_regmap; 139 const struct llcc_slice_config *cfg; 140 const struct llcc_edac_reg_offset *edac_reg_offset; 141 struct mutex lock; 142 u32 cfg_size; 143 u32 max_slices; 144 u32 num_banks; 145 unsigned long *bitmap; 146 u32 *offsets; 147 int ecc_irq; 148 u32 version; 149 }; 150 151 #if IS_ENABLED(CONFIG_QCOM_LLCC) 152 /** 153 * llcc_slice_getd - get llcc slice descriptor 154 * @uid: usecase_id of the client 155 */ 156 struct llcc_slice_desc *llcc_slice_getd(u32 uid); 157 158 /** 159 * llcc_slice_putd - llcc slice descritpor 160 * @desc: Pointer to llcc slice descriptor 161 */ 162 void llcc_slice_putd(struct llcc_slice_desc *desc); 163 164 /** 165 * llcc_get_slice_id - get slice id 166 * @desc: Pointer to llcc slice descriptor 167 */ 168 int llcc_get_slice_id(struct llcc_slice_desc *desc); 169 170 /** 171 * llcc_get_slice_size - llcc slice size 172 * @desc: Pointer to llcc slice descriptor 173 */ 174 size_t llcc_get_slice_size(struct llcc_slice_desc *desc); 175 176 /** 177 * llcc_slice_activate - Activate the llcc slice 178 * @desc: Pointer to llcc slice descriptor 179 */ 180 int llcc_slice_activate(struct llcc_slice_desc *desc); 181 182 /** 183 * llcc_slice_deactivate - Deactivate the llcc slice 184 * @desc: Pointer to llcc slice descriptor 185 */ 186 int llcc_slice_deactivate(struct llcc_slice_desc *desc); 187 188 #else 189 static inline struct llcc_slice_desc *llcc_slice_getd(u32 uid) 190 { 191 return NULL; 192 } 193 194 static inline void llcc_slice_putd(struct llcc_slice_desc *desc) 195 { 196 197 }; 198 199 static inline int llcc_get_slice_id(struct llcc_slice_desc *desc) 200 { 201 return -EINVAL; 202 } 203 204 static inline size_t llcc_get_slice_size(struct llcc_slice_desc *desc) 205 { 206 return 0; 207 } 208 static inline int llcc_slice_activate(struct llcc_slice_desc *desc) 209 { 210 return -EINVAL; 211 } 212 213 static inline int llcc_slice_deactivate(struct llcc_slice_desc *desc) 214 { 215 return -EINVAL; 216 } 217 #endif 218 219 #endif 220