1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */ 2 /* Copyright(c) 2015-17 Intel Corporation. */ 3 4 #ifndef __SOUNDWIRE_H 5 #define __SOUNDWIRE_H 6 7 #include <linux/bug.h> 8 #include <linux/mod_devicetable.h> 9 #include <linux/bitfield.h> 10 11 struct sdw_bus; 12 struct sdw_slave; 13 14 /* SDW spec defines and enums, as defined by MIPI 1.1. Spec */ 15 16 /* SDW Broadcast Device Number */ 17 #define SDW_BROADCAST_DEV_NUM 15 18 19 /* SDW Enumeration Device Number */ 20 #define SDW_ENUM_DEV_NUM 0 21 22 /* SDW Group Device Numbers */ 23 #define SDW_GROUP12_DEV_NUM 12 24 #define SDW_GROUP13_DEV_NUM 13 25 26 /* SDW Master Device Number, not supported yet */ 27 #define SDW_MASTER_DEV_NUM 14 28 29 #define SDW_NUM_DEV_ID_REGISTERS 6 30 /* frame shape defines */ 31 32 /* 33 * Note: The maximum row define in SoundWire spec 1.1 is 23. In order to 34 * fill hole with 0, one more dummy entry is added 35 */ 36 #define SDW_FRAME_ROWS 24 37 #define SDW_FRAME_COLS 8 38 #define SDW_FRAME_ROW_COLS (SDW_FRAME_ROWS * SDW_FRAME_COLS) 39 40 #define SDW_FRAME_CTRL_BITS 48 41 #define SDW_MAX_DEVICES 11 42 43 #define SDW_MAX_PORTS 15 44 #define SDW_VALID_PORT_RANGE(n) ((n) < SDW_MAX_PORTS && (n) >= 1) 45 46 enum { 47 SDW_PORT_DIRN_SINK = 0, 48 SDW_PORT_DIRN_SOURCE, 49 SDW_PORT_DIRN_MAX, 50 }; 51 52 /* 53 * constants for flow control, ports and transport 54 * 55 * these are bit masks as devices can have multiple capabilities 56 */ 57 58 /* 59 * flow modes for SDW port. These can be isochronous, tx controlled, 60 * rx controlled or async 61 */ 62 #define SDW_PORT_FLOW_MODE_ISOCH 0 63 #define SDW_PORT_FLOW_MODE_TX_CNTRL BIT(0) 64 #define SDW_PORT_FLOW_MODE_RX_CNTRL BIT(1) 65 #define SDW_PORT_FLOW_MODE_ASYNC GENMASK(1, 0) 66 67 /* sample packaging for block. It can be per port or per channel */ 68 #define SDW_BLOCK_PACKG_PER_PORT BIT(0) 69 #define SDW_BLOCK_PACKG_PER_CH BIT(1) 70 71 /** 72 * enum sdw_slave_status - Slave status 73 * @SDW_SLAVE_UNATTACHED: Slave is not attached with the bus. 74 * @SDW_SLAVE_ATTACHED: Slave is attached with bus. 75 * @SDW_SLAVE_ALERT: Some alert condition on the Slave 76 * @SDW_SLAVE_RESERVED: Reserved for future use 77 */ 78 enum sdw_slave_status { 79 SDW_SLAVE_UNATTACHED = 0, 80 SDW_SLAVE_ATTACHED = 1, 81 SDW_SLAVE_ALERT = 2, 82 SDW_SLAVE_RESERVED = 3, 83 }; 84 85 /** 86 * enum sdw_clk_stop_type: clock stop operations 87 * 88 * @SDW_CLK_PRE_PREPARE: pre clock stop prepare 89 * @SDW_CLK_POST_PREPARE: post clock stop prepare 90 * @SDW_CLK_PRE_DEPREPARE: pre clock stop de-prepare 91 * @SDW_CLK_POST_DEPREPARE: post clock stop de-prepare 92 */ 93 enum sdw_clk_stop_type { 94 SDW_CLK_PRE_PREPARE = 0, 95 SDW_CLK_POST_PREPARE, 96 SDW_CLK_PRE_DEPREPARE, 97 SDW_CLK_POST_DEPREPARE, 98 }; 99 100 /** 101 * enum sdw_command_response - Command response as defined by SDW spec 102 * @SDW_CMD_OK: cmd was successful 103 * @SDW_CMD_IGNORED: cmd was ignored 104 * @SDW_CMD_FAIL: cmd was NACKed 105 * @SDW_CMD_TIMEOUT: cmd timedout 106 * @SDW_CMD_FAIL_OTHER: cmd failed due to other reason than above 107 * 108 * NOTE: The enum is different than actual Spec as response in the Spec is 109 * combination of ACK/NAK bits 110 * 111 * SDW_CMD_TIMEOUT/FAIL_OTHER is defined for SW use, not in spec 112 */ 113 enum sdw_command_response { 114 SDW_CMD_OK = 0, 115 SDW_CMD_IGNORED = 1, 116 SDW_CMD_FAIL = 2, 117 SDW_CMD_TIMEOUT = 3, 118 SDW_CMD_FAIL_OTHER = 4, 119 }; 120 121 /* block group count enum */ 122 enum sdw_dpn_grouping { 123 SDW_BLK_GRP_CNT_1 = 0, 124 SDW_BLK_GRP_CNT_2 = 1, 125 SDW_BLK_GRP_CNT_3 = 2, 126 SDW_BLK_GRP_CNT_4 = 3, 127 }; 128 129 /* block packing mode enum */ 130 enum sdw_dpn_pkg_mode { 131 SDW_BLK_PKG_PER_PORT = 0, 132 SDW_BLK_PKG_PER_CHANNEL = 1 133 }; 134 135 /** 136 * enum sdw_stream_type: data stream type 137 * 138 * @SDW_STREAM_PCM: PCM data stream 139 * @SDW_STREAM_PDM: PDM data stream 140 * 141 * spec doesn't define this, but is used in implementation 142 */ 143 enum sdw_stream_type { 144 SDW_STREAM_PCM = 0, 145 SDW_STREAM_PDM = 1, 146 }; 147 148 /** 149 * enum sdw_data_direction: Data direction 150 * 151 * @SDW_DATA_DIR_RX: Data into Port 152 * @SDW_DATA_DIR_TX: Data out of Port 153 */ 154 enum sdw_data_direction { 155 SDW_DATA_DIR_RX = 0, 156 SDW_DATA_DIR_TX = 1, 157 }; 158 159 /** 160 * enum sdw_port_data_mode: Data Port mode 161 * 162 * @SDW_PORT_DATA_MODE_NORMAL: Normal data mode where audio data is received 163 * and transmitted. 164 * @SDW_PORT_DATA_MODE_PRBS: Test mode which uses a PRBS generator to produce 165 * a pseudo random data pattern that is transferred 166 * @SDW_PORT_DATA_MODE_STATIC_0: Simple test mode which uses static value of 167 * logic 0. The encoding will result in no signal transitions 168 * @SDW_PORT_DATA_MODE_STATIC_1: Simple test mode which uses static value of 169 * logic 1. The encoding will result in signal transitions at every bitslot 170 * owned by this Port 171 */ 172 enum sdw_port_data_mode { 173 SDW_PORT_DATA_MODE_NORMAL = 0, 174 SDW_PORT_DATA_MODE_PRBS = 1, 175 SDW_PORT_DATA_MODE_STATIC_0 = 2, 176 SDW_PORT_DATA_MODE_STATIC_1 = 3, 177 }; 178 179 /* 180 * SDW properties, defined in MIPI DisCo spec v1.0 181 */ 182 enum sdw_clk_stop_reset_behave { 183 SDW_CLK_STOP_KEEP_STATUS = 1, 184 }; 185 186 /** 187 * enum sdw_p15_behave - Slave Port 15 behaviour when the Master attempts a 188 * read 189 * @SDW_P15_READ_IGNORED: Read is ignored 190 * @SDW_P15_CMD_OK: Command is ok 191 */ 192 enum sdw_p15_behave { 193 SDW_P15_READ_IGNORED = 0, 194 SDW_P15_CMD_OK = 1, 195 }; 196 197 /** 198 * enum sdw_dpn_type - Data port types 199 * @SDW_DPN_FULL: Full Data Port is supported 200 * @SDW_DPN_SIMPLE: Simplified Data Port as defined in spec. 201 * DPN_SampleCtrl2, DPN_OffsetCtrl2, DPN_HCtrl and DPN_BlockCtrl3 202 * are not implemented. 203 * @SDW_DPN_REDUCED: Reduced Data Port as defined in spec. 204 * DPN_SampleCtrl2, DPN_HCtrl are not implemented. 205 */ 206 enum sdw_dpn_type { 207 SDW_DPN_FULL = 0, 208 SDW_DPN_SIMPLE = 1, 209 SDW_DPN_REDUCED = 2, 210 }; 211 212 /** 213 * enum sdw_clk_stop_mode - Clock Stop modes 214 * @SDW_CLK_STOP_MODE0: Slave can continue operation seamlessly on clock 215 * restart 216 * @SDW_CLK_STOP_MODE1: Slave may have entered a deeper power-saving mode, 217 * not capable of continuing operation seamlessly when the clock restarts 218 */ 219 enum sdw_clk_stop_mode { 220 SDW_CLK_STOP_MODE0 = 0, 221 SDW_CLK_STOP_MODE1 = 1, 222 }; 223 224 /** 225 * struct sdw_dp0_prop - DP0 properties 226 * @max_word: Maximum number of bits in a Payload Channel Sample, 1 to 64 227 * (inclusive) 228 * @min_word: Minimum number of bits in a Payload Channel Sample, 1 to 64 229 * (inclusive) 230 * @num_words: number of wordlengths supported 231 * @words: wordlengths supported 232 * @BRA_flow_controlled: Slave implementation results in an OK_NotReady 233 * response 234 * @simple_ch_prep_sm: If channel prepare sequence is required 235 * @imp_def_interrupts: If set, each bit corresponds to support for 236 * implementation-defined interrupts 237 * 238 * The wordlengths are specified by Spec as max, min AND number of 239 * discrete values, implementation can define based on the wordlengths they 240 * support 241 */ 242 struct sdw_dp0_prop { 243 u32 max_word; 244 u32 min_word; 245 u32 num_words; 246 u32 *words; 247 bool BRA_flow_controlled; 248 bool simple_ch_prep_sm; 249 bool imp_def_interrupts; 250 }; 251 252 /** 253 * struct sdw_dpn_audio_mode - Audio mode properties for DPn 254 * @bus_min_freq: Minimum bus frequency, in Hz 255 * @bus_max_freq: Maximum bus frequency, in Hz 256 * @bus_num_freq: Number of discrete frequencies supported 257 * @bus_freq: Discrete bus frequencies, in Hz 258 * @min_freq: Minimum sampling frequency, in Hz 259 * @max_freq: Maximum sampling bus frequency, in Hz 260 * @num_freq: Number of discrete sampling frequency supported 261 * @freq: Discrete sampling frequencies, in Hz 262 * @prep_ch_behave: Specifies the dependencies between Channel Prepare 263 * sequence and bus clock configuration 264 * If 0, Channel Prepare can happen at any Bus clock rate 265 * If 1, Channel Prepare sequence shall happen only after Bus clock is 266 * changed to a frequency supported by this mode or compatible modes 267 * described by the next field 268 * @glitchless: Bitmap describing possible glitchless transitions from this 269 * Audio Mode to other Audio Modes 270 */ 271 struct sdw_dpn_audio_mode { 272 u32 bus_min_freq; 273 u32 bus_max_freq; 274 u32 bus_num_freq; 275 u32 *bus_freq; 276 u32 max_freq; 277 u32 min_freq; 278 u32 num_freq; 279 u32 *freq; 280 u32 prep_ch_behave; 281 u32 glitchless; 282 }; 283 284 /** 285 * struct sdw_dpn_prop - Data Port DPn properties 286 * @num: port number 287 * @max_word: Maximum number of bits in a Payload Channel Sample, 1 to 64 288 * (inclusive) 289 * @min_word: Minimum number of bits in a Payload Channel Sample, 1 to 64 290 * (inclusive) 291 * @num_words: Number of discrete supported wordlengths 292 * @words: Discrete supported wordlength 293 * @type: Data port type. Full, Simplified or Reduced 294 * @max_grouping: Maximum number of samples that can be grouped together for 295 * a full data port 296 * @simple_ch_prep_sm: If the port supports simplified channel prepare state 297 * machine 298 * @ch_prep_timeout: Port-specific timeout value, in milliseconds 299 * @imp_def_interrupts: If set, each bit corresponds to support for 300 * implementation-defined interrupts 301 * @max_ch: Maximum channels supported 302 * @min_ch: Minimum channels supported 303 * @num_channels: Number of discrete channels supported 304 * @channels: Discrete channels supported 305 * @num_ch_combinations: Number of channel combinations supported 306 * @ch_combinations: Channel combinations supported 307 * @modes: SDW mode supported 308 * @max_async_buffer: Number of samples that this port can buffer in 309 * asynchronous modes 310 * @block_pack_mode: Type of block port mode supported 311 * @read_only_wordlength: Read Only wordlength field in DPN_BlockCtrl1 register 312 * @port_encoding: Payload Channel Sample encoding schemes supported 313 * @audio_modes: Audio modes supported 314 */ 315 struct sdw_dpn_prop { 316 u32 num; 317 u32 max_word; 318 u32 min_word; 319 u32 num_words; 320 u32 *words; 321 enum sdw_dpn_type type; 322 u32 max_grouping; 323 bool simple_ch_prep_sm; 324 u32 ch_prep_timeout; 325 u32 imp_def_interrupts; 326 u32 max_ch; 327 u32 min_ch; 328 u32 num_channels; 329 u32 *channels; 330 u32 num_ch_combinations; 331 u32 *ch_combinations; 332 u32 modes; 333 u32 max_async_buffer; 334 bool block_pack_mode; 335 bool read_only_wordlength; 336 u32 port_encoding; 337 struct sdw_dpn_audio_mode *audio_modes; 338 }; 339 340 /** 341 * struct sdw_slave_prop - SoundWire Slave properties 342 * @mipi_revision: Spec version of the implementation 343 * @wake_capable: Wake-up events are supported 344 * @test_mode_capable: If test mode is supported 345 * @clk_stop_mode1: Clock-Stop Mode 1 is supported 346 * @simple_clk_stop_capable: Simple clock mode is supported 347 * @clk_stop_timeout: Worst-case latency of the Clock Stop Prepare State 348 * Machine transitions, in milliseconds 349 * @ch_prep_timeout: Worst-case latency of the Channel Prepare State Machine 350 * transitions, in milliseconds 351 * @reset_behave: Slave keeps the status of the SlaveStopClockPrepare 352 * state machine (P=1 SCSP_SM) after exit from clock-stop mode1 353 * @high_PHY_capable: Slave is HighPHY capable 354 * @paging_support: Slave implements paging registers SCP_AddrPage1 and 355 * SCP_AddrPage2 356 * @bank_delay_support: Slave implements bank delay/bridge support registers 357 * SCP_BankDelay and SCP_NextFrame 358 * @p15_behave: Slave behavior when the Master attempts a read to the Port15 359 * alias 360 * @lane_control_support: Slave supports lane control 361 * @master_count: Number of Masters present on this Slave 362 * @source_ports: Bitmap identifying source ports 363 * @sink_ports: Bitmap identifying sink ports 364 * @dp0_prop: Data Port 0 properties 365 * @src_dpn_prop: Source Data Port N properties 366 * @sink_dpn_prop: Sink Data Port N properties 367 * @scp_int1_mask: SCP_INT1_MASK desired settings 368 * @quirks: bitmask identifying deltas from the MIPI specification 369 * @clock_reg_supported: the Peripheral implements the clock base and scale 370 * registers introduced with the SoundWire 1.2 specification. SDCA devices 371 * do not need to set this boolean property as the registers are required. 372 */ 373 struct sdw_slave_prop { 374 u32 mipi_revision; 375 bool wake_capable; 376 bool test_mode_capable; 377 bool clk_stop_mode1; 378 bool simple_clk_stop_capable; 379 u32 clk_stop_timeout; 380 u32 ch_prep_timeout; 381 enum sdw_clk_stop_reset_behave reset_behave; 382 bool high_PHY_capable; 383 bool paging_support; 384 bool bank_delay_support; 385 enum sdw_p15_behave p15_behave; 386 bool lane_control_support; 387 u32 master_count; 388 u32 source_ports; 389 u32 sink_ports; 390 struct sdw_dp0_prop *dp0_prop; 391 struct sdw_dpn_prop *src_dpn_prop; 392 struct sdw_dpn_prop *sink_dpn_prop; 393 u8 scp_int1_mask; 394 u32 quirks; 395 bool clock_reg_supported; 396 }; 397 398 #define SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY BIT(0) 399 400 /** 401 * struct sdw_master_prop - Master properties 402 * @revision: MIPI spec version of the implementation 403 * @clk_stop_modes: Bitmap, bit N set when clock-stop-modeN supported 404 * @max_clk_freq: Maximum Bus clock frequency, in Hz 405 * @num_clk_gears: Number of clock gears supported 406 * @clk_gears: Clock gears supported 407 * @num_clk_freq: Number of clock frequencies supported, in Hz 408 * @clk_freq: Clock frequencies supported, in Hz 409 * @default_frame_rate: Controller default Frame rate, in Hz 410 * @default_row: Number of rows 411 * @default_col: Number of columns 412 * @dynamic_frame: Dynamic frame shape supported 413 * @err_threshold: Number of times that software may retry sending a single 414 * command 415 * @mclk_freq: clock reference passed to SoundWire Master, in Hz. 416 * @hw_disabled: if true, the Master is not functional, typically due to pin-mux 417 * @quirks: bitmask identifying optional behavior beyond the scope of the MIPI specification 418 */ 419 struct sdw_master_prop { 420 u32 revision; 421 u32 clk_stop_modes; 422 u32 max_clk_freq; 423 u32 num_clk_gears; 424 u32 *clk_gears; 425 u32 num_clk_freq; 426 u32 *clk_freq; 427 u32 default_frame_rate; 428 u32 default_row; 429 u32 default_col; 430 bool dynamic_frame; 431 u32 err_threshold; 432 u32 mclk_freq; 433 bool hw_disabled; 434 u64 quirks; 435 }; 436 437 /* Definitions for Master quirks */ 438 439 /* 440 * In a number of platforms bus clashes are reported after a hardware 441 * reset but without any explanations or evidence of a real problem. 442 * The following quirk will discard all initial bus clash interrupts 443 * but will leave the detection on should real bus clashes happen 444 */ 445 #define SDW_MASTER_QUIRKS_CLEAR_INITIAL_CLASH BIT(0) 446 447 /* 448 * Some Slave devices have known issues with incorrect parity errors 449 * reported after a hardware reset. However during integration unexplained 450 * parity errors can be reported by Slave devices, possibly due to electrical 451 * issues at the Master level. 452 * The following quirk will discard all initial parity errors but will leave 453 * the detection on should real parity errors happen. 454 */ 455 #define SDW_MASTER_QUIRKS_CLEAR_INITIAL_PARITY BIT(1) 456 457 int sdw_master_read_prop(struct sdw_bus *bus); 458 int sdw_slave_read_prop(struct sdw_slave *slave); 459 460 /* 461 * SDW Slave Structures and APIs 462 */ 463 464 #define SDW_IGNORED_UNIQUE_ID 0xFF 465 466 /** 467 * struct sdw_slave_id - Slave ID 468 * @mfg_id: MIPI Manufacturer ID 469 * @part_id: Device Part ID 470 * @class_id: MIPI Class ID (defined starting with SoundWire 1.2 spec) 471 * @unique_id: Device unique ID 472 * @sdw_version: SDW version implemented 473 * 474 * The order of the IDs here does not follow the DisCo spec definitions 475 */ 476 struct sdw_slave_id { 477 __u16 mfg_id; 478 __u16 part_id; 479 __u8 class_id; 480 __u8 unique_id; 481 __u8 sdw_version:4; 482 }; 483 484 /* 485 * Helper macros to extract the MIPI-defined IDs 486 * 487 * Spec definition 488 * Register Bit Contents 489 * DevId_0 [7:4] 47:44 sdw_version 490 * DevId_0 [3:0] 43:40 unique_id 491 * DevId_1 39:32 mfg_id [15:8] 492 * DevId_2 31:24 mfg_id [7:0] 493 * DevId_3 23:16 part_id [15:8] 494 * DevId_4 15:08 part_id [7:0] 495 * DevId_5 07:00 class_id 496 * 497 * The MIPI DisCo for SoundWire defines in addition the link_id as bits 51:48 498 */ 499 #define SDW_DISCO_LINK_ID_MASK GENMASK_ULL(51, 48) 500 #define SDW_VERSION_MASK GENMASK_ULL(47, 44) 501 #define SDW_UNIQUE_ID_MASK GENMASK_ULL(43, 40) 502 #define SDW_MFG_ID_MASK GENMASK_ULL(39, 24) 503 #define SDW_PART_ID_MASK GENMASK_ULL(23, 8) 504 #define SDW_CLASS_ID_MASK GENMASK_ULL(7, 0) 505 506 #define SDW_DISCO_LINK_ID(addr) FIELD_GET(SDW_DISCO_LINK_ID_MASK, addr) 507 #define SDW_VERSION(addr) FIELD_GET(SDW_VERSION_MASK, addr) 508 #define SDW_UNIQUE_ID(addr) FIELD_GET(SDW_UNIQUE_ID_MASK, addr) 509 #define SDW_MFG_ID(addr) FIELD_GET(SDW_MFG_ID_MASK, addr) 510 #define SDW_PART_ID(addr) FIELD_GET(SDW_PART_ID_MASK, addr) 511 #define SDW_CLASS_ID(addr) FIELD_GET(SDW_CLASS_ID_MASK, addr) 512 513 /** 514 * struct sdw_slave_intr_status - Slave interrupt status 515 * @sdca_cascade: set if the Slave device reports an SDCA interrupt 516 * @control_port: control port status 517 * @port: data port status 518 */ 519 struct sdw_slave_intr_status { 520 bool sdca_cascade; 521 u8 control_port; 522 u8 port[15]; 523 }; 524 525 /** 526 * sdw_reg_bank - SoundWire register banks 527 * @SDW_BANK0: Soundwire register bank 0 528 * @SDW_BANK1: Soundwire register bank 1 529 */ 530 enum sdw_reg_bank { 531 SDW_BANK0, 532 SDW_BANK1, 533 }; 534 535 /** 536 * struct sdw_bus_conf: Bus configuration 537 * 538 * @clk_freq: Clock frequency, in Hz 539 * @num_rows: Number of rows in frame 540 * @num_cols: Number of columns in frame 541 * @bank: Next register bank 542 */ 543 struct sdw_bus_conf { 544 unsigned int clk_freq; 545 unsigned int num_rows; 546 unsigned int num_cols; 547 unsigned int bank; 548 }; 549 550 /** 551 * struct sdw_prepare_ch: Prepare/De-prepare Data Port channel 552 * 553 * @num: Port number 554 * @ch_mask: Active channel mask 555 * @prepare: Prepare (true) /de-prepare (false) channel 556 * @bank: Register bank, which bank Slave/Master driver should program for 557 * implementation defined registers. This is always updated to next_bank 558 * value read from bus params. 559 * 560 */ 561 struct sdw_prepare_ch { 562 unsigned int num; 563 unsigned int ch_mask; 564 bool prepare; 565 unsigned int bank; 566 }; 567 568 /** 569 * enum sdw_port_prep_ops: Prepare operations for Data Port 570 * 571 * @SDW_OPS_PORT_PRE_PREP: Pre prepare operation for the Port 572 * @SDW_OPS_PORT_PRE_DEPREP: Pre deprepare operation for the Port 573 * @SDW_OPS_PORT_POST_PREP: Post prepare operation for the Port 574 * @SDW_OPS_PORT_POST_DEPREP: Post deprepare operation for the Port 575 */ 576 enum sdw_port_prep_ops { 577 SDW_OPS_PORT_PRE_PREP = 0, 578 SDW_OPS_PORT_PRE_DEPREP, 579 SDW_OPS_PORT_POST_PREP, 580 SDW_OPS_PORT_POST_DEPREP, 581 }; 582 583 /** 584 * struct sdw_bus_params: Structure holding bus configuration 585 * 586 * @curr_bank: Current bank in use (BANK0/BANK1) 587 * @next_bank: Next bank to use (BANK0/BANK1). next_bank will always be 588 * set to !curr_bank 589 * @max_dr_freq: Maximum double rate clock frequency supported, in Hz 590 * @curr_dr_freq: Current double rate clock frequency, in Hz 591 * @bandwidth: Current bandwidth 592 * @col: Active columns 593 * @row: Active rows 594 * @s_data_mode: NORMAL, STATIC or PRBS mode for all Slave ports 595 * @m_data_mode: NORMAL, STATIC or PRBS mode for all Master ports. The value 596 * should be the same to detect transmission issues, but can be different to 597 * test the interrupt reports 598 */ 599 struct sdw_bus_params { 600 enum sdw_reg_bank curr_bank; 601 enum sdw_reg_bank next_bank; 602 unsigned int max_dr_freq; 603 unsigned int curr_dr_freq; 604 unsigned int bandwidth; 605 unsigned int col; 606 unsigned int row; 607 int s_data_mode; 608 int m_data_mode; 609 }; 610 611 /** 612 * struct sdw_slave_ops: Slave driver callback ops 613 * 614 * @read_prop: Read Slave properties 615 * @interrupt_callback: Device interrupt notification (invoked in thread 616 * context) 617 * @update_status: Update Slave status 618 * @bus_config: Update the bus config for Slave 619 * @port_prep: Prepare the port with parameters 620 * @clk_stop: handle imp-def sequences before and after prepare and de-prepare 621 */ 622 struct sdw_slave_ops { 623 int (*read_prop)(struct sdw_slave *sdw); 624 int (*interrupt_callback)(struct sdw_slave *slave, 625 struct sdw_slave_intr_status *status); 626 int (*update_status)(struct sdw_slave *slave, 627 enum sdw_slave_status status); 628 int (*bus_config)(struct sdw_slave *slave, 629 struct sdw_bus_params *params); 630 int (*port_prep)(struct sdw_slave *slave, 631 struct sdw_prepare_ch *prepare_ch, 632 enum sdw_port_prep_ops pre_ops); 633 int (*clk_stop)(struct sdw_slave *slave, 634 enum sdw_clk_stop_mode mode, 635 enum sdw_clk_stop_type type); 636 637 }; 638 639 /** 640 * struct sdw_slave - SoundWire Slave 641 * @id: MIPI device ID 642 * @dev: Linux device 643 * @status: Status reported by the Slave 644 * @bus: Bus handle 645 * @prop: Slave properties 646 * @debugfs: Slave debugfs 647 * @node: node for bus list 648 * @port_ready: Port ready completion flag for each Slave port 649 * @m_port_map: static Master port map for each Slave port 650 * @dev_num: Current Device Number, values can be 0 or dev_num_sticky 651 * @dev_num_sticky: one-time static Device Number assigned by Bus 652 * @probed: boolean tracking driver state 653 * @enumeration_complete: completion utility to control potential races 654 * on startup between device enumeration and read/write access to the 655 * Slave device 656 * @initialization_complete: completion utility to control potential races 657 * on startup between device enumeration and settings being restored 658 * @unattach_request: mask field to keep track why the Slave re-attached and 659 * was re-initialized. This is useful to deal with potential race conditions 660 * between the Master suspending and the codec resuming, and make sure that 661 * when the Master triggered a reset the Slave is properly enumerated and 662 * initialized 663 * @first_interrupt_done: status flag tracking if the interrupt handling 664 * for a Slave happens for the first time after enumeration 665 * @is_mockup_device: status flag used to squelch errors in the command/control 666 * protocol for SoundWire mockup devices 667 * @sdw_dev_lock: mutex used to protect callbacks/remove races 668 */ 669 struct sdw_slave { 670 struct sdw_slave_id id; 671 struct device dev; 672 enum sdw_slave_status status; 673 struct sdw_bus *bus; 674 struct sdw_slave_prop prop; 675 #ifdef CONFIG_DEBUG_FS 676 struct dentry *debugfs; 677 #endif 678 struct list_head node; 679 struct completion port_ready[SDW_MAX_PORTS]; 680 unsigned int m_port_map[SDW_MAX_PORTS]; 681 u16 dev_num; 682 u16 dev_num_sticky; 683 bool probed; 684 struct completion enumeration_complete; 685 struct completion initialization_complete; 686 u32 unattach_request; 687 bool first_interrupt_done; 688 bool is_mockup_device; 689 struct mutex sdw_dev_lock; /* protect callbacks/remove races */ 690 }; 691 692 #define dev_to_sdw_dev(_dev) container_of(_dev, struct sdw_slave, dev) 693 694 /** 695 * struct sdw_master_device - SoundWire 'Master Device' representation 696 * @dev: Linux device for this Master 697 * @bus: Bus handle shortcut 698 */ 699 struct sdw_master_device { 700 struct device dev; 701 struct sdw_bus *bus; 702 }; 703 704 #define dev_to_sdw_master_device(d) \ 705 container_of(d, struct sdw_master_device, dev) 706 707 struct sdw_driver { 708 const char *name; 709 710 int (*probe)(struct sdw_slave *sdw, 711 const struct sdw_device_id *id); 712 int (*remove)(struct sdw_slave *sdw); 713 void (*shutdown)(struct sdw_slave *sdw); 714 715 const struct sdw_device_id *id_table; 716 const struct sdw_slave_ops *ops; 717 718 struct device_driver driver; 719 }; 720 721 #define SDW_SLAVE_ENTRY_EXT(_mfg_id, _part_id, _version, _c_id, _drv_data) \ 722 { .mfg_id = (_mfg_id), .part_id = (_part_id), \ 723 .sdw_version = (_version), .class_id = (_c_id), \ 724 .driver_data = (unsigned long)(_drv_data) } 725 726 #define SDW_SLAVE_ENTRY(_mfg_id, _part_id, _drv_data) \ 727 SDW_SLAVE_ENTRY_EXT((_mfg_id), (_part_id), 0, 0, (_drv_data)) 728 729 int sdw_handle_slave_status(struct sdw_bus *bus, 730 enum sdw_slave_status status[]); 731 732 /* 733 * SDW master structures and APIs 734 */ 735 736 /** 737 * struct sdw_port_params: Data Port parameters 738 * 739 * @num: Port number 740 * @bps: Word length of the Port 741 * @flow_mode: Port Data flow mode 742 * @data_mode: Test modes or normal mode 743 * 744 * This is used to program the Data Port based on Data Port stream 745 * parameters. 746 */ 747 struct sdw_port_params { 748 unsigned int num; 749 unsigned int bps; 750 unsigned int flow_mode; 751 unsigned int data_mode; 752 }; 753 754 /** 755 * struct sdw_transport_params: Data Port Transport Parameters 756 * 757 * @blk_grp_ctrl_valid: Port implements block group control 758 * @num: Port number 759 * @blk_grp_ctrl: Block group control value 760 * @sample_interval: Sample interval 761 * @offset1: Blockoffset of the payload data 762 * @offset2: Blockoffset of the payload data 763 * @hstart: Horizontal start of the payload data 764 * @hstop: Horizontal stop of the payload data 765 * @blk_pkg_mode: Block per channel or block per port 766 * @lane_ctrl: Data lane Port uses for Data transfer. Currently only single 767 * data lane is supported in bus 768 * 769 * This is used to program the Data Port based on Data Port transport 770 * parameters. All these parameters are banked and can be modified 771 * during a bank switch without any artifacts in audio stream. 772 */ 773 struct sdw_transport_params { 774 bool blk_grp_ctrl_valid; 775 unsigned int port_num; 776 unsigned int blk_grp_ctrl; 777 unsigned int sample_interval; 778 unsigned int offset1; 779 unsigned int offset2; 780 unsigned int hstart; 781 unsigned int hstop; 782 unsigned int blk_pkg_mode; 783 unsigned int lane_ctrl; 784 }; 785 786 /** 787 * struct sdw_enable_ch: Enable/disable Data Port channel 788 * 789 * @num: Port number 790 * @ch_mask: Active channel mask 791 * @enable: Enable (true) /disable (false) channel 792 */ 793 struct sdw_enable_ch { 794 unsigned int port_num; 795 unsigned int ch_mask; 796 bool enable; 797 }; 798 799 /** 800 * struct sdw_master_port_ops: Callback functions from bus to Master 801 * driver to set Master Data ports. 802 * 803 * @dpn_set_port_params: Set the Port parameters for the Master Port. 804 * Mandatory callback 805 * @dpn_set_port_transport_params: Set transport parameters for the Master 806 * Port. Mandatory callback 807 * @dpn_port_prep: Port prepare operations for the Master Data Port. 808 * @dpn_port_enable_ch: Enable the channels of Master Port. 809 */ 810 struct sdw_master_port_ops { 811 int (*dpn_set_port_params)(struct sdw_bus *bus, 812 struct sdw_port_params *port_params, 813 unsigned int bank); 814 int (*dpn_set_port_transport_params)(struct sdw_bus *bus, 815 struct sdw_transport_params *transport_params, 816 enum sdw_reg_bank bank); 817 int (*dpn_port_prep)(struct sdw_bus *bus, 818 struct sdw_prepare_ch *prepare_ch); 819 int (*dpn_port_enable_ch)(struct sdw_bus *bus, 820 struct sdw_enable_ch *enable_ch, unsigned int bank); 821 }; 822 823 struct sdw_msg; 824 825 /** 826 * struct sdw_defer - SDW deffered message 827 * @length: message length 828 * @complete: message completion 829 * @msg: SDW message 830 */ 831 struct sdw_defer { 832 int length; 833 struct completion complete; 834 struct sdw_msg *msg; 835 }; 836 837 /** 838 * struct sdw_master_ops - Master driver ops 839 * @read_prop: Read Master properties 840 * @override_adr: Override value read from firmware (quirk for buggy firmware) 841 * @xfer_msg: Transfer message callback 842 * @xfer_msg_defer: Defer version of transfer message callback. The message is handled with the 843 * bus struct @sdw_defer 844 * @set_bus_conf: Set the bus configuration 845 * @pre_bank_switch: Callback for pre bank switch 846 * @post_bank_switch: Callback for post bank switch 847 * @read_ping_status: Read status from PING frames, reported with two bits per Device. 848 * Bits 31:24 are reserved. 849 */ 850 struct sdw_master_ops { 851 int (*read_prop)(struct sdw_bus *bus); 852 u64 (*override_adr) 853 (struct sdw_bus *bus, u64 addr); 854 enum sdw_command_response (*xfer_msg) 855 (struct sdw_bus *bus, struct sdw_msg *msg); 856 enum sdw_command_response (*xfer_msg_defer) 857 (struct sdw_bus *bus); 858 int (*set_bus_conf)(struct sdw_bus *bus, 859 struct sdw_bus_params *params); 860 int (*pre_bank_switch)(struct sdw_bus *bus); 861 int (*post_bank_switch)(struct sdw_bus *bus); 862 u32 (*read_ping_status)(struct sdw_bus *bus); 863 864 }; 865 866 /** 867 * struct sdw_bus - SoundWire bus 868 * @dev: Shortcut to &bus->md->dev to avoid changing the entire code. 869 * @md: Master device 870 * @link_id: Link id number, can be 0 to N, unique for each Master 871 * @id: bus system-wide unique id 872 * @slaves: list of Slaves on this bus 873 * @assigned: Bitmap for Slave device numbers. 874 * Bit set implies used number, bit clear implies unused number. 875 * @bus_lock: bus lock 876 * @msg_lock: message lock 877 * @compute_params: points to Bus resource management implementation 878 * @ops: Master callback ops 879 * @port_ops: Master port callback ops 880 * @params: Current bus parameters 881 * @prop: Master properties 882 * @m_rt_list: List of Master instance of all stream(s) running on Bus. This 883 * is used to compute and program bus bandwidth, clock, frame shape, 884 * transport and port parameters 885 * @debugfs: Bus debugfs 886 * @defer_msg: Defer message 887 * @clk_stop_timeout: Clock stop timeout computed 888 * @bank_switch_timeout: Bank switch timeout computed 889 * @multi_link: Store bus property that indicates if multi links 890 * are supported. This flag is populated by drivers after reading 891 * appropriate firmware (ACPI/DT). 892 * @hw_sync_min_links: Number of links used by a stream above which 893 * hardware-based synchronization is required. This value is only 894 * meaningful if multi_link is set. If set to 1, hardware-based 895 * synchronization will be used even if a stream only uses a single 896 * SoundWire segment. 897 * @dev_num_ida_min: if set, defines the minimum values for the IDA 898 * used to allocate system-unique device numbers. This value needs to be 899 * identical across all SoundWire bus in the system. 900 */ 901 struct sdw_bus { 902 struct device *dev; 903 struct sdw_master_device *md; 904 unsigned int link_id; 905 int id; 906 struct list_head slaves; 907 DECLARE_BITMAP(assigned, SDW_MAX_DEVICES); 908 struct mutex bus_lock; 909 struct mutex msg_lock; 910 int (*compute_params)(struct sdw_bus *bus); 911 const struct sdw_master_ops *ops; 912 const struct sdw_master_port_ops *port_ops; 913 struct sdw_bus_params params; 914 struct sdw_master_prop prop; 915 struct list_head m_rt_list; 916 #ifdef CONFIG_DEBUG_FS 917 struct dentry *debugfs; 918 #endif 919 struct sdw_defer defer_msg; 920 unsigned int clk_stop_timeout; 921 u32 bank_switch_timeout; 922 bool multi_link; 923 int hw_sync_min_links; 924 int dev_num_ida_min; 925 }; 926 927 int sdw_bus_master_add(struct sdw_bus *bus, struct device *parent, 928 struct fwnode_handle *fwnode); 929 void sdw_bus_master_delete(struct sdw_bus *bus); 930 931 void sdw_show_ping_status(struct sdw_bus *bus, bool sync_delay); 932 933 /** 934 * sdw_port_config: Master or Slave Port configuration 935 * 936 * @num: Port number 937 * @ch_mask: channels mask for port 938 */ 939 struct sdw_port_config { 940 unsigned int num; 941 unsigned int ch_mask; 942 }; 943 944 /** 945 * sdw_stream_config: Master or Slave stream configuration 946 * 947 * @frame_rate: Audio frame rate of the stream, in Hz 948 * @ch_count: Channel count of the stream 949 * @bps: Number of bits per audio sample 950 * @direction: Data direction 951 * @type: Stream type PCM or PDM 952 */ 953 struct sdw_stream_config { 954 unsigned int frame_rate; 955 unsigned int ch_count; 956 unsigned int bps; 957 enum sdw_data_direction direction; 958 enum sdw_stream_type type; 959 }; 960 961 /** 962 * sdw_stream_state: Stream states 963 * 964 * @SDW_STREAM_ALLOCATED: New stream allocated. 965 * @SDW_STREAM_CONFIGURED: Stream configured 966 * @SDW_STREAM_PREPARED: Stream prepared 967 * @SDW_STREAM_ENABLED: Stream enabled 968 * @SDW_STREAM_DISABLED: Stream disabled 969 * @SDW_STREAM_DEPREPARED: Stream de-prepared 970 * @SDW_STREAM_RELEASED: Stream released 971 */ 972 enum sdw_stream_state { 973 SDW_STREAM_ALLOCATED = 0, 974 SDW_STREAM_CONFIGURED = 1, 975 SDW_STREAM_PREPARED = 2, 976 SDW_STREAM_ENABLED = 3, 977 SDW_STREAM_DISABLED = 4, 978 SDW_STREAM_DEPREPARED = 5, 979 SDW_STREAM_RELEASED = 6, 980 }; 981 982 /** 983 * sdw_stream_params: Stream parameters 984 * 985 * @rate: Sampling frequency, in Hz 986 * @ch_count: Number of channels 987 * @bps: bits per channel sample 988 */ 989 struct sdw_stream_params { 990 unsigned int rate; 991 unsigned int ch_count; 992 unsigned int bps; 993 }; 994 995 /** 996 * sdw_stream_runtime: Runtime stream parameters 997 * 998 * @name: SoundWire stream name 999 * @params: Stream parameters 1000 * @state: Current state of the stream 1001 * @type: Stream type PCM or PDM 1002 * @master_list: List of Master runtime(s) in this stream. 1003 * master_list can contain only one m_rt per Master instance 1004 * for a stream 1005 * @m_rt_count: Count of Master runtime(s) in this stream 1006 */ 1007 struct sdw_stream_runtime { 1008 const char *name; 1009 struct sdw_stream_params params; 1010 enum sdw_stream_state state; 1011 enum sdw_stream_type type; 1012 struct list_head master_list; 1013 int m_rt_count; 1014 }; 1015 1016 struct sdw_stream_runtime *sdw_alloc_stream(const char *stream_name); 1017 void sdw_release_stream(struct sdw_stream_runtime *stream); 1018 1019 int sdw_compute_params(struct sdw_bus *bus); 1020 1021 int sdw_stream_add_master(struct sdw_bus *bus, 1022 struct sdw_stream_config *stream_config, 1023 struct sdw_port_config *port_config, 1024 unsigned int num_ports, 1025 struct sdw_stream_runtime *stream); 1026 int sdw_stream_remove_master(struct sdw_bus *bus, 1027 struct sdw_stream_runtime *stream); 1028 int sdw_startup_stream(void *sdw_substream); 1029 int sdw_prepare_stream(struct sdw_stream_runtime *stream); 1030 int sdw_enable_stream(struct sdw_stream_runtime *stream); 1031 int sdw_disable_stream(struct sdw_stream_runtime *stream); 1032 int sdw_deprepare_stream(struct sdw_stream_runtime *stream); 1033 void sdw_shutdown_stream(void *sdw_substream); 1034 int sdw_bus_prep_clk_stop(struct sdw_bus *bus); 1035 int sdw_bus_clk_stop(struct sdw_bus *bus); 1036 int sdw_bus_exit_clk_stop(struct sdw_bus *bus); 1037 1038 int sdw_compare_devid(struct sdw_slave *slave, struct sdw_slave_id id); 1039 void sdw_extract_slave_id(struct sdw_bus *bus, u64 addr, struct sdw_slave_id *id); 1040 1041 #if IS_ENABLED(CONFIG_SOUNDWIRE) 1042 1043 int sdw_stream_add_slave(struct sdw_slave *slave, 1044 struct sdw_stream_config *stream_config, 1045 struct sdw_port_config *port_config, 1046 unsigned int num_ports, 1047 struct sdw_stream_runtime *stream); 1048 int sdw_stream_remove_slave(struct sdw_slave *slave, 1049 struct sdw_stream_runtime *stream); 1050 1051 /* messaging and data APIs */ 1052 int sdw_read(struct sdw_slave *slave, u32 addr); 1053 int sdw_write(struct sdw_slave *slave, u32 addr, u8 value); 1054 int sdw_write_no_pm(struct sdw_slave *slave, u32 addr, u8 value); 1055 int sdw_read_no_pm(struct sdw_slave *slave, u32 addr); 1056 int sdw_nread(struct sdw_slave *slave, u32 addr, size_t count, u8 *val); 1057 int sdw_nread_no_pm(struct sdw_slave *slave, u32 addr, size_t count, u8 *val); 1058 int sdw_nwrite(struct sdw_slave *slave, u32 addr, size_t count, const u8 *val); 1059 int sdw_nwrite_no_pm(struct sdw_slave *slave, u32 addr, size_t count, const u8 *val); 1060 int sdw_update(struct sdw_slave *slave, u32 addr, u8 mask, u8 val); 1061 int sdw_update_no_pm(struct sdw_slave *slave, u32 addr, u8 mask, u8 val); 1062 1063 #else 1064 1065 static inline int sdw_stream_add_slave(struct sdw_slave *slave, 1066 struct sdw_stream_config *stream_config, 1067 struct sdw_port_config *port_config, 1068 unsigned int num_ports, 1069 struct sdw_stream_runtime *stream) 1070 { 1071 WARN_ONCE(1, "SoundWire API is disabled"); 1072 return -EINVAL; 1073 } 1074 1075 static inline int sdw_stream_remove_slave(struct sdw_slave *slave, 1076 struct sdw_stream_runtime *stream) 1077 { 1078 WARN_ONCE(1, "SoundWire API is disabled"); 1079 return -EINVAL; 1080 } 1081 1082 /* messaging and data APIs */ 1083 static inline int sdw_read(struct sdw_slave *slave, u32 addr) 1084 { 1085 WARN_ONCE(1, "SoundWire API is disabled"); 1086 return -EINVAL; 1087 } 1088 1089 static inline int sdw_write(struct sdw_slave *slave, u32 addr, u8 value) 1090 { 1091 WARN_ONCE(1, "SoundWire API is disabled"); 1092 return -EINVAL; 1093 } 1094 1095 static inline int sdw_write_no_pm(struct sdw_slave *slave, u32 addr, u8 value) 1096 { 1097 WARN_ONCE(1, "SoundWire API is disabled"); 1098 return -EINVAL; 1099 } 1100 1101 static inline int sdw_read_no_pm(struct sdw_slave *slave, u32 addr) 1102 { 1103 WARN_ONCE(1, "SoundWire API is disabled"); 1104 return -EINVAL; 1105 } 1106 1107 static inline int sdw_nread(struct sdw_slave *slave, u32 addr, size_t count, u8 *val) 1108 { 1109 WARN_ONCE(1, "SoundWire API is disabled"); 1110 return -EINVAL; 1111 } 1112 1113 static inline int sdw_nread_no_pm(struct sdw_slave *slave, u32 addr, size_t count, u8 *val) 1114 { 1115 WARN_ONCE(1, "SoundWire API is disabled"); 1116 return -EINVAL; 1117 } 1118 1119 static inline int sdw_nwrite(struct sdw_slave *slave, u32 addr, size_t count, const u8 *val) 1120 { 1121 WARN_ONCE(1, "SoundWire API is disabled"); 1122 return -EINVAL; 1123 } 1124 1125 static inline int sdw_nwrite_no_pm(struct sdw_slave *slave, u32 addr, size_t count, const u8 *val) 1126 { 1127 WARN_ONCE(1, "SoundWire API is disabled"); 1128 return -EINVAL; 1129 } 1130 1131 static inline int sdw_update(struct sdw_slave *slave, u32 addr, u8 mask, u8 val) 1132 { 1133 WARN_ONCE(1, "SoundWire API is disabled"); 1134 return -EINVAL; 1135 } 1136 1137 static inline int sdw_update_no_pm(struct sdw_slave *slave, u32 addr, u8 mask, u8 val) 1138 { 1139 WARN_ONCE(1, "SoundWire API is disabled"); 1140 return -EINVAL; 1141 } 1142 1143 #endif /* CONFIG_SOUNDWIRE */ 1144 1145 #endif /* __SOUNDWIRE_H */ 1146