1 /* SPDX-License-Identifier: GPL-2.0-or-later 2 * 3 * Copyright (C) 2005 David Brownell 4 */ 5 6 #ifndef __LINUX_SPI_H 7 #define __LINUX_SPI_H 8 9 #include <linux/device.h> 10 #include <linux/mod_devicetable.h> 11 #include <linux/slab.h> 12 #include <linux/kthread.h> 13 #include <linux/completion.h> 14 #include <linux/scatterlist.h> 15 #include <linux/gpio/consumer.h> 16 17 struct dma_chan; 18 struct property_entry; 19 struct spi_controller; 20 struct spi_transfer; 21 struct spi_controller_mem_ops; 22 23 /* 24 * INTERFACES between SPI master-side drivers and SPI slave protocol handlers, 25 * and SPI infrastructure. 26 */ 27 extern struct bus_type spi_bus_type; 28 29 /** 30 * struct spi_statistics - statistics for spi transfers 31 * @lock: lock protecting this structure 32 * 33 * @messages: number of spi-messages handled 34 * @transfers: number of spi_transfers handled 35 * @errors: number of errors during spi_transfer 36 * @timedout: number of timeouts during spi_transfer 37 * 38 * @spi_sync: number of times spi_sync is used 39 * @spi_sync_immediate: 40 * number of times spi_sync is executed immediately 41 * in calling context without queuing and scheduling 42 * @spi_async: number of times spi_async is used 43 * 44 * @bytes: number of bytes transferred to/from device 45 * @bytes_tx: number of bytes sent to device 46 * @bytes_rx: number of bytes received from device 47 * 48 * @transfer_bytes_histo: 49 * transfer bytes histogramm 50 * 51 * @transfers_split_maxsize: 52 * number of transfers that have been split because of 53 * maxsize limit 54 */ 55 struct spi_statistics { 56 spinlock_t lock; /* lock for the whole structure */ 57 58 unsigned long messages; 59 unsigned long transfers; 60 unsigned long errors; 61 unsigned long timedout; 62 63 unsigned long spi_sync; 64 unsigned long spi_sync_immediate; 65 unsigned long spi_async; 66 67 unsigned long long bytes; 68 unsigned long long bytes_rx; 69 unsigned long long bytes_tx; 70 71 #define SPI_STATISTICS_HISTO_SIZE 17 72 unsigned long transfer_bytes_histo[SPI_STATISTICS_HISTO_SIZE]; 73 74 unsigned long transfers_split_maxsize; 75 }; 76 77 void spi_statistics_add_transfer_stats(struct spi_statistics *stats, 78 struct spi_transfer *xfer, 79 struct spi_controller *ctlr); 80 81 #define SPI_STATISTICS_ADD_TO_FIELD(stats, field, count) \ 82 do { \ 83 unsigned long flags; \ 84 spin_lock_irqsave(&(stats)->lock, flags); \ 85 (stats)->field += count; \ 86 spin_unlock_irqrestore(&(stats)->lock, flags); \ 87 } while (0) 88 89 #define SPI_STATISTICS_INCREMENT_FIELD(stats, field) \ 90 SPI_STATISTICS_ADD_TO_FIELD(stats, field, 1) 91 92 /** 93 * struct spi_device - Controller side proxy for an SPI slave device 94 * @dev: Driver model representation of the device. 95 * @controller: SPI controller used with the device. 96 * @master: Copy of controller, for backwards compatibility. 97 * @max_speed_hz: Maximum clock rate to be used with this chip 98 * (on this board); may be changed by the device's driver. 99 * The spi_transfer.speed_hz can override this for each transfer. 100 * @chip_select: Chipselect, distinguishing chips handled by @controller. 101 * @mode: The spi mode defines how data is clocked out and in. 102 * This may be changed by the device's driver. 103 * The "active low" default for chipselect mode can be overridden 104 * (by specifying SPI_CS_HIGH) as can the "MSB first" default for 105 * each word in a transfer (by specifying SPI_LSB_FIRST). 106 * @bits_per_word: Data transfers involve one or more words; word sizes 107 * like eight or 12 bits are common. In-memory wordsizes are 108 * powers of two bytes (e.g. 20 bit samples use 32 bits). 109 * This may be changed by the device's driver, or left at the 110 * default (0) indicating protocol words are eight bit bytes. 111 * The spi_transfer.bits_per_word can override this for each transfer. 112 * @irq: Negative, or the number passed to request_irq() to receive 113 * interrupts from this device. 114 * @controller_state: Controller's runtime state 115 * @controller_data: Board-specific definitions for controller, such as 116 * FIFO initialization parameters; from board_info.controller_data 117 * @modalias: Name of the driver to use with this device, or an alias 118 * for that name. This appears in the sysfs "modalias" attribute 119 * for driver coldplugging, and in uevents used for hotplugging 120 * @cs_gpio: LEGACY: gpio number of the chipselect line (optional, -ENOENT when 121 * not using a GPIO line) use cs_gpiod in new drivers by opting in on 122 * the spi_master. 123 * @cs_gpiod: gpio descriptor of the chipselect line (optional, NULL when 124 * not using a GPIO line) 125 * @word_delay_usecs: microsecond delay to be inserted between consecutive 126 * words of a transfer 127 * 128 * @statistics: statistics for the spi_device 129 * 130 * A @spi_device is used to interchange data between an SPI slave 131 * (usually a discrete chip) and CPU memory. 132 * 133 * In @dev, the platform_data is used to hold information about this 134 * device that's meaningful to the device's protocol driver, but not 135 * to its controller. One example might be an identifier for a chip 136 * variant with slightly different functionality; another might be 137 * information about how this particular board wires the chip's pins. 138 */ 139 struct spi_device { 140 struct device dev; 141 struct spi_controller *controller; 142 struct spi_controller *master; /* compatibility layer */ 143 u32 max_speed_hz; 144 u8 chip_select; 145 u8 bits_per_word; 146 u32 mode; 147 #define SPI_CPHA 0x01 /* clock phase */ 148 #define SPI_CPOL 0x02 /* clock polarity */ 149 #define SPI_MODE_0 (0|0) /* (original MicroWire) */ 150 #define SPI_MODE_1 (0|SPI_CPHA) 151 #define SPI_MODE_2 (SPI_CPOL|0) 152 #define SPI_MODE_3 (SPI_CPOL|SPI_CPHA) 153 #define SPI_CS_HIGH 0x04 /* chipselect active high? */ 154 #define SPI_LSB_FIRST 0x08 /* per-word bits-on-wire */ 155 #define SPI_3WIRE 0x10 /* SI/SO signals shared */ 156 #define SPI_LOOP 0x20 /* loopback mode */ 157 #define SPI_NO_CS 0x40 /* 1 dev/bus, no chipselect */ 158 #define SPI_READY 0x80 /* slave pulls low to pause */ 159 #define SPI_TX_DUAL 0x100 /* transmit with 2 wires */ 160 #define SPI_TX_QUAD 0x200 /* transmit with 4 wires */ 161 #define SPI_RX_DUAL 0x400 /* receive with 2 wires */ 162 #define SPI_RX_QUAD 0x800 /* receive with 4 wires */ 163 #define SPI_CS_WORD 0x1000 /* toggle cs after each word */ 164 #define SPI_TX_OCTAL 0x2000 /* transmit with 8 wires */ 165 #define SPI_RX_OCTAL 0x4000 /* receive with 8 wires */ 166 #define SPI_3WIRE_HIZ 0x8000 /* high impedance turnaround */ 167 int irq; 168 void *controller_state; 169 void *controller_data; 170 char modalias[SPI_NAME_SIZE]; 171 const char *driver_override; 172 int cs_gpio; /* LEGACY: chip select gpio */ 173 struct gpio_desc *cs_gpiod; /* chip select gpio desc */ 174 uint8_t word_delay_usecs; /* inter-word delay */ 175 176 /* the statistics */ 177 struct spi_statistics statistics; 178 179 /* 180 * likely need more hooks for more protocol options affecting how 181 * the controller talks to each chip, like: 182 * - memory packing (12 bit samples into low bits, others zeroed) 183 * - priority 184 * - chipselect delays 185 * - ... 186 */ 187 }; 188 189 static inline struct spi_device *to_spi_device(struct device *dev) 190 { 191 return dev ? container_of(dev, struct spi_device, dev) : NULL; 192 } 193 194 /* most drivers won't need to care about device refcounting */ 195 static inline struct spi_device *spi_dev_get(struct spi_device *spi) 196 { 197 return (spi && get_device(&spi->dev)) ? spi : NULL; 198 } 199 200 static inline void spi_dev_put(struct spi_device *spi) 201 { 202 if (spi) 203 put_device(&spi->dev); 204 } 205 206 /* ctldata is for the bus_controller driver's runtime state */ 207 static inline void *spi_get_ctldata(struct spi_device *spi) 208 { 209 return spi->controller_state; 210 } 211 212 static inline void spi_set_ctldata(struct spi_device *spi, void *state) 213 { 214 spi->controller_state = state; 215 } 216 217 /* device driver data */ 218 219 static inline void spi_set_drvdata(struct spi_device *spi, void *data) 220 { 221 dev_set_drvdata(&spi->dev, data); 222 } 223 224 static inline void *spi_get_drvdata(struct spi_device *spi) 225 { 226 return dev_get_drvdata(&spi->dev); 227 } 228 229 struct spi_message; 230 struct spi_transfer; 231 232 /** 233 * struct spi_driver - Host side "protocol" driver 234 * @id_table: List of SPI devices supported by this driver 235 * @probe: Binds this driver to the spi device. Drivers can verify 236 * that the device is actually present, and may need to configure 237 * characteristics (such as bits_per_word) which weren't needed for 238 * the initial configuration done during system setup. 239 * @remove: Unbinds this driver from the spi device 240 * @shutdown: Standard shutdown callback used during system state 241 * transitions such as powerdown/halt and kexec 242 * @driver: SPI device drivers should initialize the name and owner 243 * field of this structure. 244 * 245 * This represents the kind of device driver that uses SPI messages to 246 * interact with the hardware at the other end of a SPI link. It's called 247 * a "protocol" driver because it works through messages rather than talking 248 * directly to SPI hardware (which is what the underlying SPI controller 249 * driver does to pass those messages). These protocols are defined in the 250 * specification for the device(s) supported by the driver. 251 * 252 * As a rule, those device protocols represent the lowest level interface 253 * supported by a driver, and it will support upper level interfaces too. 254 * Examples of such upper levels include frameworks like MTD, networking, 255 * MMC, RTC, filesystem character device nodes, and hardware monitoring. 256 */ 257 struct spi_driver { 258 const struct spi_device_id *id_table; 259 int (*probe)(struct spi_device *spi); 260 int (*remove)(struct spi_device *spi); 261 void (*shutdown)(struct spi_device *spi); 262 struct device_driver driver; 263 }; 264 265 static inline struct spi_driver *to_spi_driver(struct device_driver *drv) 266 { 267 return drv ? container_of(drv, struct spi_driver, driver) : NULL; 268 } 269 270 extern int __spi_register_driver(struct module *owner, struct spi_driver *sdrv); 271 272 /** 273 * spi_unregister_driver - reverse effect of spi_register_driver 274 * @sdrv: the driver to unregister 275 * Context: can sleep 276 */ 277 static inline void spi_unregister_driver(struct spi_driver *sdrv) 278 { 279 if (sdrv) 280 driver_unregister(&sdrv->driver); 281 } 282 283 /* use a define to avoid include chaining to get THIS_MODULE */ 284 #define spi_register_driver(driver) \ 285 __spi_register_driver(THIS_MODULE, driver) 286 287 /** 288 * module_spi_driver() - Helper macro for registering a SPI driver 289 * @__spi_driver: spi_driver struct 290 * 291 * Helper macro for SPI drivers which do not do anything special in module 292 * init/exit. This eliminates a lot of boilerplate. Each module may only 293 * use this macro once, and calling it replaces module_init() and module_exit() 294 */ 295 #define module_spi_driver(__spi_driver) \ 296 module_driver(__spi_driver, spi_register_driver, \ 297 spi_unregister_driver) 298 299 /** 300 * struct spi_controller - interface to SPI master or slave controller 301 * @dev: device interface to this driver 302 * @list: link with the global spi_controller list 303 * @bus_num: board-specific (and often SOC-specific) identifier for a 304 * given SPI controller. 305 * @num_chipselect: chipselects are used to distinguish individual 306 * SPI slaves, and are numbered from zero to num_chipselects. 307 * each slave has a chipselect signal, but it's common that not 308 * every chipselect is connected to a slave. 309 * @dma_alignment: SPI controller constraint on DMA buffers alignment. 310 * @mode_bits: flags understood by this controller driver 311 * @bits_per_word_mask: A mask indicating which values of bits_per_word are 312 * supported by the driver. Bit n indicates that a bits_per_word n+1 is 313 * supported. If set, the SPI core will reject any transfer with an 314 * unsupported bits_per_word. If not set, this value is simply ignored, 315 * and it's up to the individual driver to perform any validation. 316 * @min_speed_hz: Lowest supported transfer speed 317 * @max_speed_hz: Highest supported transfer speed 318 * @flags: other constraints relevant to this driver 319 * @slave: indicates that this is an SPI slave controller 320 * @max_transfer_size: function that returns the max transfer size for 321 * a &spi_device; may be %NULL, so the default %SIZE_MAX will be used. 322 * @max_message_size: function that returns the max message size for 323 * a &spi_device; may be %NULL, so the default %SIZE_MAX will be used. 324 * @io_mutex: mutex for physical bus access 325 * @bus_lock_spinlock: spinlock for SPI bus locking 326 * @bus_lock_mutex: mutex for exclusion of multiple callers 327 * @bus_lock_flag: indicates that the SPI bus is locked for exclusive use 328 * @setup: updates the device mode and clocking records used by a 329 * device's SPI controller; protocol code may call this. This 330 * must fail if an unrecognized or unsupported mode is requested. 331 * It's always safe to call this unless transfers are pending on 332 * the device whose settings are being modified. 333 * @set_cs_timing: optional hook for SPI devices to request SPI master 334 * controller for configuring specific CS setup time, hold time and inactive 335 * delay interms of clock counts 336 * @transfer: adds a message to the controller's transfer queue. 337 * @cleanup: frees controller-specific state 338 * @can_dma: determine whether this controller supports DMA 339 * @queued: whether this controller is providing an internal message queue 340 * @kworker: thread struct for message pump 341 * @kworker_task: pointer to task for message pump kworker thread 342 * @pump_messages: work struct for scheduling work to the message pump 343 * @queue_lock: spinlock to syncronise access to message queue 344 * @queue: message queue 345 * @idling: the device is entering idle state 346 * @cur_msg: the currently in-flight message 347 * @cur_msg_prepared: spi_prepare_message was called for the currently 348 * in-flight message 349 * @cur_msg_mapped: message has been mapped for DMA 350 * @xfer_completion: used by core transfer_one_message() 351 * @busy: message pump is busy 352 * @running: message pump is running 353 * @rt: whether this queue is set to run as a realtime task 354 * @auto_runtime_pm: the core should ensure a runtime PM reference is held 355 * while the hardware is prepared, using the parent 356 * device for the spidev 357 * @max_dma_len: Maximum length of a DMA transfer for the device. 358 * @prepare_transfer_hardware: a message will soon arrive from the queue 359 * so the subsystem requests the driver to prepare the transfer hardware 360 * by issuing this call 361 * @transfer_one_message: the subsystem calls the driver to transfer a single 362 * message while queuing transfers that arrive in the meantime. When the 363 * driver is finished with this message, it must call 364 * spi_finalize_current_message() so the subsystem can issue the next 365 * message 366 * @unprepare_transfer_hardware: there are currently no more messages on the 367 * queue so the subsystem notifies the driver that it may relax the 368 * hardware by issuing this call 369 * 370 * @set_cs: set the logic level of the chip select line. May be called 371 * from interrupt context. 372 * @prepare_message: set up the controller to transfer a single message, 373 * for example doing DMA mapping. Called from threaded 374 * context. 375 * @transfer_one: transfer a single spi_transfer. 376 * - return 0 if the transfer is finished, 377 * - return 1 if the transfer is still in progress. When 378 * the driver is finished with this transfer it must 379 * call spi_finalize_current_transfer() so the subsystem 380 * can issue the next transfer. Note: transfer_one and 381 * transfer_one_message are mutually exclusive; when both 382 * are set, the generic subsystem does not call your 383 * transfer_one callback. 384 * @handle_err: the subsystem calls the driver to handle an error that occurs 385 * in the generic implementation of transfer_one_message(). 386 * @mem_ops: optimized/dedicated operations for interactions with SPI memory. 387 * This field is optional and should only be implemented if the 388 * controller has native support for memory like operations. 389 * @unprepare_message: undo any work done by prepare_message(). 390 * @slave_abort: abort the ongoing transfer request on an SPI slave controller 391 * @cs_gpios: LEGACY: array of GPIO descs to use as chip select lines; one per 392 * CS number. Any individual value may be -ENOENT for CS lines that 393 * are not GPIOs (driven by the SPI controller itself). Use the cs_gpiods 394 * in new drivers. 395 * @cs_gpiods: Array of GPIO descs to use as chip select lines; one per CS 396 * number. Any individual value may be NULL for CS lines that 397 * are not GPIOs (driven by the SPI controller itself). 398 * @use_gpio_descriptors: Turns on the code in the SPI core to parse and grab 399 * GPIO descriptors rather than using global GPIO numbers grabbed by the 400 * driver. This will fill in @cs_gpiods and @cs_gpios should not be used, 401 * and SPI devices will have the cs_gpiod assigned rather than cs_gpio. 402 * @statistics: statistics for the spi_controller 403 * @dma_tx: DMA transmit channel 404 * @dma_rx: DMA receive channel 405 * @dummy_rx: dummy receive buffer for full-duplex devices 406 * @dummy_tx: dummy transmit buffer for full-duplex devices 407 * @fw_translate_cs: If the boot firmware uses different numbering scheme 408 * what Linux expects, this optional hook can be used to translate 409 * between the two. 410 * 411 * Each SPI controller can communicate with one or more @spi_device 412 * children. These make a small bus, sharing MOSI, MISO and SCK signals 413 * but not chip select signals. Each device may be configured to use a 414 * different clock rate, since those shared signals are ignored unless 415 * the chip is selected. 416 * 417 * The driver for an SPI controller manages access to those devices through 418 * a queue of spi_message transactions, copying data between CPU memory and 419 * an SPI slave device. For each such message it queues, it calls the 420 * message's completion function when the transaction completes. 421 */ 422 struct spi_controller { 423 struct device dev; 424 425 struct list_head list; 426 427 /* other than negative (== assign one dynamically), bus_num is fully 428 * board-specific. usually that simplifies to being SOC-specific. 429 * example: one SOC has three SPI controllers, numbered 0..2, 430 * and one board's schematics might show it using SPI-2. software 431 * would normally use bus_num=2 for that controller. 432 */ 433 s16 bus_num; 434 435 /* chipselects will be integral to many controllers; some others 436 * might use board-specific GPIOs. 437 */ 438 u16 num_chipselect; 439 440 /* some SPI controllers pose alignment requirements on DMAable 441 * buffers; let protocol drivers know about these requirements. 442 */ 443 u16 dma_alignment; 444 445 /* spi_device.mode flags understood by this controller driver */ 446 u32 mode_bits; 447 448 /* bitmask of supported bits_per_word for transfers */ 449 u32 bits_per_word_mask; 450 #define SPI_BPW_MASK(bits) BIT((bits) - 1) 451 #define SPI_BPW_RANGE_MASK(min, max) GENMASK((max) - 1, (min) - 1) 452 453 /* limits on transfer speed */ 454 u32 min_speed_hz; 455 u32 max_speed_hz; 456 457 /* other constraints relevant to this driver */ 458 u16 flags; 459 #define SPI_CONTROLLER_HALF_DUPLEX BIT(0) /* can't do full duplex */ 460 #define SPI_CONTROLLER_NO_RX BIT(1) /* can't do buffer read */ 461 #define SPI_CONTROLLER_NO_TX BIT(2) /* can't do buffer write */ 462 #define SPI_CONTROLLER_MUST_RX BIT(3) /* requires rx */ 463 #define SPI_CONTROLLER_MUST_TX BIT(4) /* requires tx */ 464 465 #define SPI_MASTER_GPIO_SS BIT(5) /* GPIO CS must select slave */ 466 467 /* flag indicating this is an SPI slave controller */ 468 bool slave; 469 470 /* 471 * on some hardware transfer / message size may be constrained 472 * the limit may depend on device transfer settings 473 */ 474 size_t (*max_transfer_size)(struct spi_device *spi); 475 size_t (*max_message_size)(struct spi_device *spi); 476 477 /* I/O mutex */ 478 struct mutex io_mutex; 479 480 /* lock and mutex for SPI bus locking */ 481 spinlock_t bus_lock_spinlock; 482 struct mutex bus_lock_mutex; 483 484 /* flag indicating that the SPI bus is locked for exclusive use */ 485 bool bus_lock_flag; 486 487 /* Setup mode and clock, etc (spi driver may call many times). 488 * 489 * IMPORTANT: this may be called when transfers to another 490 * device are active. DO NOT UPDATE SHARED REGISTERS in ways 491 * which could break those transfers. 492 */ 493 int (*setup)(struct spi_device *spi); 494 495 /* 496 * set_cs_timing() method is for SPI controllers that supports 497 * configuring CS timing. 498 * 499 * This hook allows SPI client drivers to request SPI controllers 500 * to configure specific CS timing through spi_set_cs_timing() after 501 * spi_setup(). 502 */ 503 void (*set_cs_timing)(struct spi_device *spi, u8 setup_clk_cycles, 504 u8 hold_clk_cycles, u8 inactive_clk_cycles); 505 506 /* bidirectional bulk transfers 507 * 508 * + The transfer() method may not sleep; its main role is 509 * just to add the message to the queue. 510 * + For now there's no remove-from-queue operation, or 511 * any other request management 512 * + To a given spi_device, message queueing is pure fifo 513 * 514 * + The controller's main job is to process its message queue, 515 * selecting a chip (for masters), then transferring data 516 * + If there are multiple spi_device children, the i/o queue 517 * arbitration algorithm is unspecified (round robin, fifo, 518 * priority, reservations, preemption, etc) 519 * 520 * + Chipselect stays active during the entire message 521 * (unless modified by spi_transfer.cs_change != 0). 522 * + The message transfers use clock and SPI mode parameters 523 * previously established by setup() for this device 524 */ 525 int (*transfer)(struct spi_device *spi, 526 struct spi_message *mesg); 527 528 /* called on release() to free memory provided by spi_controller */ 529 void (*cleanup)(struct spi_device *spi); 530 531 /* 532 * Used to enable core support for DMA handling, if can_dma() 533 * exists and returns true then the transfer will be mapped 534 * prior to transfer_one() being called. The driver should 535 * not modify or store xfer and dma_tx and dma_rx must be set 536 * while the device is prepared. 537 */ 538 bool (*can_dma)(struct spi_controller *ctlr, 539 struct spi_device *spi, 540 struct spi_transfer *xfer); 541 542 /* 543 * These hooks are for drivers that want to use the generic 544 * controller transfer queueing mechanism. If these are used, the 545 * transfer() function above must NOT be specified by the driver. 546 * Over time we expect SPI drivers to be phased over to this API. 547 */ 548 bool queued; 549 struct kthread_worker kworker; 550 struct task_struct *kworker_task; 551 struct kthread_work pump_messages; 552 spinlock_t queue_lock; 553 struct list_head queue; 554 struct spi_message *cur_msg; 555 bool idling; 556 bool busy; 557 bool running; 558 bool rt; 559 bool auto_runtime_pm; 560 bool cur_msg_prepared; 561 bool cur_msg_mapped; 562 struct completion xfer_completion; 563 size_t max_dma_len; 564 565 int (*prepare_transfer_hardware)(struct spi_controller *ctlr); 566 int (*transfer_one_message)(struct spi_controller *ctlr, 567 struct spi_message *mesg); 568 int (*unprepare_transfer_hardware)(struct spi_controller *ctlr); 569 int (*prepare_message)(struct spi_controller *ctlr, 570 struct spi_message *message); 571 int (*unprepare_message)(struct spi_controller *ctlr, 572 struct spi_message *message); 573 int (*slave_abort)(struct spi_controller *ctlr); 574 575 /* 576 * These hooks are for drivers that use a generic implementation 577 * of transfer_one_message() provied by the core. 578 */ 579 void (*set_cs)(struct spi_device *spi, bool enable); 580 int (*transfer_one)(struct spi_controller *ctlr, struct spi_device *spi, 581 struct spi_transfer *transfer); 582 void (*handle_err)(struct spi_controller *ctlr, 583 struct spi_message *message); 584 585 /* Optimized handlers for SPI memory-like operations. */ 586 const struct spi_controller_mem_ops *mem_ops; 587 588 /* gpio chip select */ 589 int *cs_gpios; 590 struct gpio_desc **cs_gpiods; 591 bool use_gpio_descriptors; 592 593 /* statistics */ 594 struct spi_statistics statistics; 595 596 /* DMA channels for use with core dmaengine helpers */ 597 struct dma_chan *dma_tx; 598 struct dma_chan *dma_rx; 599 600 /* dummy data for full duplex devices */ 601 void *dummy_rx; 602 void *dummy_tx; 603 604 int (*fw_translate_cs)(struct spi_controller *ctlr, unsigned cs); 605 }; 606 607 static inline void *spi_controller_get_devdata(struct spi_controller *ctlr) 608 { 609 return dev_get_drvdata(&ctlr->dev); 610 } 611 612 static inline void spi_controller_set_devdata(struct spi_controller *ctlr, 613 void *data) 614 { 615 dev_set_drvdata(&ctlr->dev, data); 616 } 617 618 static inline struct spi_controller *spi_controller_get(struct spi_controller *ctlr) 619 { 620 if (!ctlr || !get_device(&ctlr->dev)) 621 return NULL; 622 return ctlr; 623 } 624 625 static inline void spi_controller_put(struct spi_controller *ctlr) 626 { 627 if (ctlr) 628 put_device(&ctlr->dev); 629 } 630 631 static inline bool spi_controller_is_slave(struct spi_controller *ctlr) 632 { 633 return IS_ENABLED(CONFIG_SPI_SLAVE) && ctlr->slave; 634 } 635 636 /* PM calls that need to be issued by the driver */ 637 extern int spi_controller_suspend(struct spi_controller *ctlr); 638 extern int spi_controller_resume(struct spi_controller *ctlr); 639 640 /* Calls the driver make to interact with the message queue */ 641 extern struct spi_message *spi_get_next_queued_message(struct spi_controller *ctlr); 642 extern void spi_finalize_current_message(struct spi_controller *ctlr); 643 extern void spi_finalize_current_transfer(struct spi_controller *ctlr); 644 645 /* the spi driver core manages memory for the spi_controller classdev */ 646 extern struct spi_controller *__spi_alloc_controller(struct device *host, 647 unsigned int size, bool slave); 648 649 static inline struct spi_controller *spi_alloc_master(struct device *host, 650 unsigned int size) 651 { 652 return __spi_alloc_controller(host, size, false); 653 } 654 655 static inline struct spi_controller *spi_alloc_slave(struct device *host, 656 unsigned int size) 657 { 658 if (!IS_ENABLED(CONFIG_SPI_SLAVE)) 659 return NULL; 660 661 return __spi_alloc_controller(host, size, true); 662 } 663 664 extern int spi_register_controller(struct spi_controller *ctlr); 665 extern int devm_spi_register_controller(struct device *dev, 666 struct spi_controller *ctlr); 667 extern void spi_unregister_controller(struct spi_controller *ctlr); 668 669 extern struct spi_controller *spi_busnum_to_master(u16 busnum); 670 671 /* 672 * SPI resource management while processing a SPI message 673 */ 674 675 typedef void (*spi_res_release_t)(struct spi_controller *ctlr, 676 struct spi_message *msg, 677 void *res); 678 679 /** 680 * struct spi_res - spi resource management structure 681 * @entry: list entry 682 * @release: release code called prior to freeing this resource 683 * @data: extra data allocated for the specific use-case 684 * 685 * this is based on ideas from devres, but focused on life-cycle 686 * management during spi_message processing 687 */ 688 struct spi_res { 689 struct list_head entry; 690 spi_res_release_t release; 691 unsigned long long data[]; /* guarantee ull alignment */ 692 }; 693 694 extern void *spi_res_alloc(struct spi_device *spi, 695 spi_res_release_t release, 696 size_t size, gfp_t gfp); 697 extern void spi_res_add(struct spi_message *message, void *res); 698 extern void spi_res_free(void *res); 699 700 extern void spi_res_release(struct spi_controller *ctlr, 701 struct spi_message *message); 702 703 /*---------------------------------------------------------------------------*/ 704 705 /* 706 * I/O INTERFACE between SPI controller and protocol drivers 707 * 708 * Protocol drivers use a queue of spi_messages, each transferring data 709 * between the controller and memory buffers. 710 * 711 * The spi_messages themselves consist of a series of read+write transfer 712 * segments. Those segments always read the same number of bits as they 713 * write; but one or the other is easily ignored by passing a null buffer 714 * pointer. (This is unlike most types of I/O API, because SPI hardware 715 * is full duplex.) 716 * 717 * NOTE: Allocation of spi_transfer and spi_message memory is entirely 718 * up to the protocol driver, which guarantees the integrity of both (as 719 * well as the data buffers) for as long as the message is queued. 720 */ 721 722 /** 723 * struct spi_transfer - a read/write buffer pair 724 * @tx_buf: data to be written (dma-safe memory), or NULL 725 * @rx_buf: data to be read (dma-safe memory), or NULL 726 * @tx_dma: DMA address of tx_buf, if @spi_message.is_dma_mapped 727 * @rx_dma: DMA address of rx_buf, if @spi_message.is_dma_mapped 728 * @tx_nbits: number of bits used for writing. If 0 the default 729 * (SPI_NBITS_SINGLE) is used. 730 * @rx_nbits: number of bits used for reading. If 0 the default 731 * (SPI_NBITS_SINGLE) is used. 732 * @len: size of rx and tx buffers (in bytes) 733 * @speed_hz: Select a speed other than the device default for this 734 * transfer. If 0 the default (from @spi_device) is used. 735 * @bits_per_word: select a bits_per_word other than the device default 736 * for this transfer. If 0 the default (from @spi_device) is used. 737 * @cs_change: affects chipselect after this transfer completes 738 * @delay_usecs: microseconds to delay after this transfer before 739 * (optionally) changing the chipselect status, then starting 740 * the next transfer or completing this @spi_message. 741 * @word_delay_usecs: microseconds to inter word delay after each word size 742 * (set by bits_per_word) transmission. 743 * @word_delay: clock cycles to inter word delay after each word size 744 * (set by bits_per_word) transmission. 745 * @transfer_list: transfers are sequenced through @spi_message.transfers 746 * @tx_sg: Scatterlist for transmit, currently not for client use 747 * @rx_sg: Scatterlist for receive, currently not for client use 748 * 749 * SPI transfers always write the same number of bytes as they read. 750 * Protocol drivers should always provide @rx_buf and/or @tx_buf. 751 * In some cases, they may also want to provide DMA addresses for 752 * the data being transferred; that may reduce overhead, when the 753 * underlying driver uses dma. 754 * 755 * If the transmit buffer is null, zeroes will be shifted out 756 * while filling @rx_buf. If the receive buffer is null, the data 757 * shifted in will be discarded. Only "len" bytes shift out (or in). 758 * It's an error to try to shift out a partial word. (For example, by 759 * shifting out three bytes with word size of sixteen or twenty bits; 760 * the former uses two bytes per word, the latter uses four bytes.) 761 * 762 * In-memory data values are always in native CPU byte order, translated 763 * from the wire byte order (big-endian except with SPI_LSB_FIRST). So 764 * for example when bits_per_word is sixteen, buffers are 2N bytes long 765 * (@len = 2N) and hold N sixteen bit words in CPU byte order. 766 * 767 * When the word size of the SPI transfer is not a power-of-two multiple 768 * of eight bits, those in-memory words include extra bits. In-memory 769 * words are always seen by protocol drivers as right-justified, so the 770 * undefined (rx) or unused (tx) bits are always the most significant bits. 771 * 772 * All SPI transfers start with the relevant chipselect active. Normally 773 * it stays selected until after the last transfer in a message. Drivers 774 * can affect the chipselect signal using cs_change. 775 * 776 * (i) If the transfer isn't the last one in the message, this flag is 777 * used to make the chipselect briefly go inactive in the middle of the 778 * message. Toggling chipselect in this way may be needed to terminate 779 * a chip command, letting a single spi_message perform all of group of 780 * chip transactions together. 781 * 782 * (ii) When the transfer is the last one in the message, the chip may 783 * stay selected until the next transfer. On multi-device SPI busses 784 * with nothing blocking messages going to other devices, this is just 785 * a performance hint; starting a message to another device deselects 786 * this one. But in other cases, this can be used to ensure correctness. 787 * Some devices need protocol transactions to be built from a series of 788 * spi_message submissions, where the content of one message is determined 789 * by the results of previous messages and where the whole transaction 790 * ends when the chipselect goes intactive. 791 * 792 * When SPI can transfer in 1x,2x or 4x. It can get this transfer information 793 * from device through @tx_nbits and @rx_nbits. In Bi-direction, these 794 * two should both be set. User can set transfer mode with SPI_NBITS_SINGLE(1x) 795 * SPI_NBITS_DUAL(2x) and SPI_NBITS_QUAD(4x) to support these three transfer. 796 * 797 * The code that submits an spi_message (and its spi_transfers) 798 * to the lower layers is responsible for managing its memory. 799 * Zero-initialize every field you don't set up explicitly, to 800 * insulate against future API updates. After you submit a message 801 * and its transfers, ignore them until its completion callback. 802 */ 803 struct spi_transfer { 804 /* it's ok if tx_buf == rx_buf (right?) 805 * for MicroWire, one buffer must be null 806 * buffers must work with dma_*map_single() calls, unless 807 * spi_message.is_dma_mapped reports a pre-existing mapping 808 */ 809 const void *tx_buf; 810 void *rx_buf; 811 unsigned len; 812 813 dma_addr_t tx_dma; 814 dma_addr_t rx_dma; 815 struct sg_table tx_sg; 816 struct sg_table rx_sg; 817 818 unsigned cs_change:1; 819 unsigned tx_nbits:3; 820 unsigned rx_nbits:3; 821 #define SPI_NBITS_SINGLE 0x01 /* 1bit transfer */ 822 #define SPI_NBITS_DUAL 0x02 /* 2bits transfer */ 823 #define SPI_NBITS_QUAD 0x04 /* 4bits transfer */ 824 u8 bits_per_word; 825 u8 word_delay_usecs; 826 u16 delay_usecs; 827 u32 speed_hz; 828 u16 word_delay; 829 830 struct list_head transfer_list; 831 }; 832 833 /** 834 * struct spi_message - one multi-segment SPI transaction 835 * @transfers: list of transfer segments in this transaction 836 * @spi: SPI device to which the transaction is queued 837 * @is_dma_mapped: if true, the caller provided both dma and cpu virtual 838 * addresses for each transfer buffer 839 * @complete: called to report transaction completions 840 * @context: the argument to complete() when it's called 841 * @frame_length: the total number of bytes in the message 842 * @actual_length: the total number of bytes that were transferred in all 843 * successful segments 844 * @status: zero for success, else negative errno 845 * @queue: for use by whichever driver currently owns the message 846 * @state: for use by whichever driver currently owns the message 847 * @resources: for resource management when the spi message is processed 848 * 849 * A @spi_message is used to execute an atomic sequence of data transfers, 850 * each represented by a struct spi_transfer. The sequence is "atomic" 851 * in the sense that no other spi_message may use that SPI bus until that 852 * sequence completes. On some systems, many such sequences can execute as 853 * as single programmed DMA transfer. On all systems, these messages are 854 * queued, and might complete after transactions to other devices. Messages 855 * sent to a given spi_device are always executed in FIFO order. 856 * 857 * The code that submits an spi_message (and its spi_transfers) 858 * to the lower layers is responsible for managing its memory. 859 * Zero-initialize every field you don't set up explicitly, to 860 * insulate against future API updates. After you submit a message 861 * and its transfers, ignore them until its completion callback. 862 */ 863 struct spi_message { 864 struct list_head transfers; 865 866 struct spi_device *spi; 867 868 unsigned is_dma_mapped:1; 869 870 /* REVISIT: we might want a flag affecting the behavior of the 871 * last transfer ... allowing things like "read 16 bit length L" 872 * immediately followed by "read L bytes". Basically imposing 873 * a specific message scheduling algorithm. 874 * 875 * Some controller drivers (message-at-a-time queue processing) 876 * could provide that as their default scheduling algorithm. But 877 * others (with multi-message pipelines) could need a flag to 878 * tell them about such special cases. 879 */ 880 881 /* completion is reported through a callback */ 882 void (*complete)(void *context); 883 void *context; 884 unsigned frame_length; 885 unsigned actual_length; 886 int status; 887 888 /* for optional use by whatever driver currently owns the 889 * spi_message ... between calls to spi_async and then later 890 * complete(), that's the spi_controller controller driver. 891 */ 892 struct list_head queue; 893 void *state; 894 895 /* list of spi_res reources when the spi message is processed */ 896 struct list_head resources; 897 }; 898 899 static inline void spi_message_init_no_memset(struct spi_message *m) 900 { 901 INIT_LIST_HEAD(&m->transfers); 902 INIT_LIST_HEAD(&m->resources); 903 } 904 905 static inline void spi_message_init(struct spi_message *m) 906 { 907 memset(m, 0, sizeof *m); 908 spi_message_init_no_memset(m); 909 } 910 911 static inline void 912 spi_message_add_tail(struct spi_transfer *t, struct spi_message *m) 913 { 914 list_add_tail(&t->transfer_list, &m->transfers); 915 } 916 917 static inline void 918 spi_transfer_del(struct spi_transfer *t) 919 { 920 list_del(&t->transfer_list); 921 } 922 923 /** 924 * spi_message_init_with_transfers - Initialize spi_message and append transfers 925 * @m: spi_message to be initialized 926 * @xfers: An array of spi transfers 927 * @num_xfers: Number of items in the xfer array 928 * 929 * This function initializes the given spi_message and adds each spi_transfer in 930 * the given array to the message. 931 */ 932 static inline void 933 spi_message_init_with_transfers(struct spi_message *m, 934 struct spi_transfer *xfers, unsigned int num_xfers) 935 { 936 unsigned int i; 937 938 spi_message_init(m); 939 for (i = 0; i < num_xfers; ++i) 940 spi_message_add_tail(&xfers[i], m); 941 } 942 943 /* It's fine to embed message and transaction structures in other data 944 * structures so long as you don't free them while they're in use. 945 */ 946 947 static inline struct spi_message *spi_message_alloc(unsigned ntrans, gfp_t flags) 948 { 949 struct spi_message *m; 950 951 m = kzalloc(sizeof(struct spi_message) 952 + ntrans * sizeof(struct spi_transfer), 953 flags); 954 if (m) { 955 unsigned i; 956 struct spi_transfer *t = (struct spi_transfer *)(m + 1); 957 958 spi_message_init_no_memset(m); 959 for (i = 0; i < ntrans; i++, t++) 960 spi_message_add_tail(t, m); 961 } 962 return m; 963 } 964 965 static inline void spi_message_free(struct spi_message *m) 966 { 967 kfree(m); 968 } 969 970 extern int spi_setup(struct spi_device *spi); 971 extern int spi_async(struct spi_device *spi, struct spi_message *message); 972 extern int spi_async_locked(struct spi_device *spi, 973 struct spi_message *message); 974 extern int spi_slave_abort(struct spi_device *spi); 975 976 static inline size_t 977 spi_max_message_size(struct spi_device *spi) 978 { 979 struct spi_controller *ctlr = spi->controller; 980 981 if (!ctlr->max_message_size) 982 return SIZE_MAX; 983 return ctlr->max_message_size(spi); 984 } 985 986 static inline size_t 987 spi_max_transfer_size(struct spi_device *spi) 988 { 989 struct spi_controller *ctlr = spi->controller; 990 size_t tr_max = SIZE_MAX; 991 size_t msg_max = spi_max_message_size(spi); 992 993 if (ctlr->max_transfer_size) 994 tr_max = ctlr->max_transfer_size(spi); 995 996 /* transfer size limit must not be greater than messsage size limit */ 997 return min(tr_max, msg_max); 998 } 999 1000 /*---------------------------------------------------------------------------*/ 1001 1002 /* SPI transfer replacement methods which make use of spi_res */ 1003 1004 struct spi_replaced_transfers; 1005 typedef void (*spi_replaced_release_t)(struct spi_controller *ctlr, 1006 struct spi_message *msg, 1007 struct spi_replaced_transfers *res); 1008 /** 1009 * struct spi_replaced_transfers - structure describing the spi_transfer 1010 * replacements that have occurred 1011 * so that they can get reverted 1012 * @release: some extra release code to get executed prior to 1013 * relasing this structure 1014 * @extradata: pointer to some extra data if requested or NULL 1015 * @replaced_transfers: transfers that have been replaced and which need 1016 * to get restored 1017 * @replaced_after: the transfer after which the @replaced_transfers 1018 * are to get re-inserted 1019 * @inserted: number of transfers inserted 1020 * @inserted_transfers: array of spi_transfers of array-size @inserted, 1021 * that have been replacing replaced_transfers 1022 * 1023 * note: that @extradata will point to @inserted_transfers[@inserted] 1024 * if some extra allocation is requested, so alignment will be the same 1025 * as for spi_transfers 1026 */ 1027 struct spi_replaced_transfers { 1028 spi_replaced_release_t release; 1029 void *extradata; 1030 struct list_head replaced_transfers; 1031 struct list_head *replaced_after; 1032 size_t inserted; 1033 struct spi_transfer inserted_transfers[]; 1034 }; 1035 1036 extern struct spi_replaced_transfers *spi_replace_transfers( 1037 struct spi_message *msg, 1038 struct spi_transfer *xfer_first, 1039 size_t remove, 1040 size_t insert, 1041 spi_replaced_release_t release, 1042 size_t extradatasize, 1043 gfp_t gfp); 1044 1045 /*---------------------------------------------------------------------------*/ 1046 1047 /* SPI transfer transformation methods */ 1048 1049 extern int spi_split_transfers_maxsize(struct spi_controller *ctlr, 1050 struct spi_message *msg, 1051 size_t maxsize, 1052 gfp_t gfp); 1053 1054 /*---------------------------------------------------------------------------*/ 1055 1056 /* All these synchronous SPI transfer routines are utilities layered 1057 * over the core async transfer primitive. Here, "synchronous" means 1058 * they will sleep uninterruptibly until the async transfer completes. 1059 */ 1060 1061 extern int spi_sync(struct spi_device *spi, struct spi_message *message); 1062 extern int spi_sync_locked(struct spi_device *spi, struct spi_message *message); 1063 extern int spi_bus_lock(struct spi_controller *ctlr); 1064 extern int spi_bus_unlock(struct spi_controller *ctlr); 1065 1066 /** 1067 * spi_sync_transfer - synchronous SPI data transfer 1068 * @spi: device with which data will be exchanged 1069 * @xfers: An array of spi_transfers 1070 * @num_xfers: Number of items in the xfer array 1071 * Context: can sleep 1072 * 1073 * Does a synchronous SPI data transfer of the given spi_transfer array. 1074 * 1075 * For more specific semantics see spi_sync(). 1076 * 1077 * Return: Return: zero on success, else a negative error code. 1078 */ 1079 static inline int 1080 spi_sync_transfer(struct spi_device *spi, struct spi_transfer *xfers, 1081 unsigned int num_xfers) 1082 { 1083 struct spi_message msg; 1084 1085 spi_message_init_with_transfers(&msg, xfers, num_xfers); 1086 1087 return spi_sync(spi, &msg); 1088 } 1089 1090 /** 1091 * spi_write - SPI synchronous write 1092 * @spi: device to which data will be written 1093 * @buf: data buffer 1094 * @len: data buffer size 1095 * Context: can sleep 1096 * 1097 * This function writes the buffer @buf. 1098 * Callable only from contexts that can sleep. 1099 * 1100 * Return: zero on success, else a negative error code. 1101 */ 1102 static inline int 1103 spi_write(struct spi_device *spi, const void *buf, size_t len) 1104 { 1105 struct spi_transfer t = { 1106 .tx_buf = buf, 1107 .len = len, 1108 }; 1109 1110 return spi_sync_transfer(spi, &t, 1); 1111 } 1112 1113 /** 1114 * spi_read - SPI synchronous read 1115 * @spi: device from which data will be read 1116 * @buf: data buffer 1117 * @len: data buffer size 1118 * Context: can sleep 1119 * 1120 * This function reads the buffer @buf. 1121 * Callable only from contexts that can sleep. 1122 * 1123 * Return: zero on success, else a negative error code. 1124 */ 1125 static inline int 1126 spi_read(struct spi_device *spi, void *buf, size_t len) 1127 { 1128 struct spi_transfer t = { 1129 .rx_buf = buf, 1130 .len = len, 1131 }; 1132 1133 return spi_sync_transfer(spi, &t, 1); 1134 } 1135 1136 /* this copies txbuf and rxbuf data; for small transfers only! */ 1137 extern int spi_write_then_read(struct spi_device *spi, 1138 const void *txbuf, unsigned n_tx, 1139 void *rxbuf, unsigned n_rx); 1140 1141 /** 1142 * spi_w8r8 - SPI synchronous 8 bit write followed by 8 bit read 1143 * @spi: device with which data will be exchanged 1144 * @cmd: command to be written before data is read back 1145 * Context: can sleep 1146 * 1147 * Callable only from contexts that can sleep. 1148 * 1149 * Return: the (unsigned) eight bit number returned by the 1150 * device, or else a negative error code. 1151 */ 1152 static inline ssize_t spi_w8r8(struct spi_device *spi, u8 cmd) 1153 { 1154 ssize_t status; 1155 u8 result; 1156 1157 status = spi_write_then_read(spi, &cmd, 1, &result, 1); 1158 1159 /* return negative errno or unsigned value */ 1160 return (status < 0) ? status : result; 1161 } 1162 1163 /** 1164 * spi_w8r16 - SPI synchronous 8 bit write followed by 16 bit read 1165 * @spi: device with which data will be exchanged 1166 * @cmd: command to be written before data is read back 1167 * Context: can sleep 1168 * 1169 * The number is returned in wire-order, which is at least sometimes 1170 * big-endian. 1171 * 1172 * Callable only from contexts that can sleep. 1173 * 1174 * Return: the (unsigned) sixteen bit number returned by the 1175 * device, or else a negative error code. 1176 */ 1177 static inline ssize_t spi_w8r16(struct spi_device *spi, u8 cmd) 1178 { 1179 ssize_t status; 1180 u16 result; 1181 1182 status = spi_write_then_read(spi, &cmd, 1, &result, 2); 1183 1184 /* return negative errno or unsigned value */ 1185 return (status < 0) ? status : result; 1186 } 1187 1188 /** 1189 * spi_w8r16be - SPI synchronous 8 bit write followed by 16 bit big-endian read 1190 * @spi: device with which data will be exchanged 1191 * @cmd: command to be written before data is read back 1192 * Context: can sleep 1193 * 1194 * This function is similar to spi_w8r16, with the exception that it will 1195 * convert the read 16 bit data word from big-endian to native endianness. 1196 * 1197 * Callable only from contexts that can sleep. 1198 * 1199 * Return: the (unsigned) sixteen bit number returned by the device in cpu 1200 * endianness, or else a negative error code. 1201 */ 1202 static inline ssize_t spi_w8r16be(struct spi_device *spi, u8 cmd) 1203 1204 { 1205 ssize_t status; 1206 __be16 result; 1207 1208 status = spi_write_then_read(spi, &cmd, 1, &result, 2); 1209 if (status < 0) 1210 return status; 1211 1212 return be16_to_cpu(result); 1213 } 1214 1215 /*---------------------------------------------------------------------------*/ 1216 1217 /* 1218 * INTERFACE between board init code and SPI infrastructure. 1219 * 1220 * No SPI driver ever sees these SPI device table segments, but 1221 * it's how the SPI core (or adapters that get hotplugged) grows 1222 * the driver model tree. 1223 * 1224 * As a rule, SPI devices can't be probed. Instead, board init code 1225 * provides a table listing the devices which are present, with enough 1226 * information to bind and set up the device's driver. There's basic 1227 * support for nonstatic configurations too; enough to handle adding 1228 * parport adapters, or microcontrollers acting as USB-to-SPI bridges. 1229 */ 1230 1231 /** 1232 * struct spi_board_info - board-specific template for a SPI device 1233 * @modalias: Initializes spi_device.modalias; identifies the driver. 1234 * @platform_data: Initializes spi_device.platform_data; the particular 1235 * data stored there is driver-specific. 1236 * @properties: Additional device properties for the device. 1237 * @controller_data: Initializes spi_device.controller_data; some 1238 * controllers need hints about hardware setup, e.g. for DMA. 1239 * @irq: Initializes spi_device.irq; depends on how the board is wired. 1240 * @max_speed_hz: Initializes spi_device.max_speed_hz; based on limits 1241 * from the chip datasheet and board-specific signal quality issues. 1242 * @bus_num: Identifies which spi_controller parents the spi_device; unused 1243 * by spi_new_device(), and otherwise depends on board wiring. 1244 * @chip_select: Initializes spi_device.chip_select; depends on how 1245 * the board is wired. 1246 * @mode: Initializes spi_device.mode; based on the chip datasheet, board 1247 * wiring (some devices support both 3WIRE and standard modes), and 1248 * possibly presence of an inverter in the chipselect path. 1249 * 1250 * When adding new SPI devices to the device tree, these structures serve 1251 * as a partial device template. They hold information which can't always 1252 * be determined by drivers. Information that probe() can establish (such 1253 * as the default transfer wordsize) is not included here. 1254 * 1255 * These structures are used in two places. Their primary role is to 1256 * be stored in tables of board-specific device descriptors, which are 1257 * declared early in board initialization and then used (much later) to 1258 * populate a controller's device tree after the that controller's driver 1259 * initializes. A secondary (and atypical) role is as a parameter to 1260 * spi_new_device() call, which happens after those controller drivers 1261 * are active in some dynamic board configuration models. 1262 */ 1263 struct spi_board_info { 1264 /* the device name and module name are coupled, like platform_bus; 1265 * "modalias" is normally the driver name. 1266 * 1267 * platform_data goes to spi_device.dev.platform_data, 1268 * controller_data goes to spi_device.controller_data, 1269 * device properties are copied and attached to spi_device, 1270 * irq is copied too 1271 */ 1272 char modalias[SPI_NAME_SIZE]; 1273 const void *platform_data; 1274 const struct property_entry *properties; 1275 void *controller_data; 1276 int irq; 1277 1278 /* slower signaling on noisy or low voltage boards */ 1279 u32 max_speed_hz; 1280 1281 1282 /* bus_num is board specific and matches the bus_num of some 1283 * spi_controller that will probably be registered later. 1284 * 1285 * chip_select reflects how this chip is wired to that master; 1286 * it's less than num_chipselect. 1287 */ 1288 u16 bus_num; 1289 u16 chip_select; 1290 1291 /* mode becomes spi_device.mode, and is essential for chips 1292 * where the default of SPI_CS_HIGH = 0 is wrong. 1293 */ 1294 u32 mode; 1295 1296 /* ... may need additional spi_device chip config data here. 1297 * avoid stuff protocol drivers can set; but include stuff 1298 * needed to behave without being bound to a driver: 1299 * - quirks like clock rate mattering when not selected 1300 */ 1301 }; 1302 1303 #ifdef CONFIG_SPI 1304 extern int 1305 spi_register_board_info(struct spi_board_info const *info, unsigned n); 1306 #else 1307 /* board init code may ignore whether SPI is configured or not */ 1308 static inline int 1309 spi_register_board_info(struct spi_board_info const *info, unsigned n) 1310 { return 0; } 1311 #endif 1312 1313 /* If you're hotplugging an adapter with devices (parport, usb, etc) 1314 * use spi_new_device() to describe each device. You can also call 1315 * spi_unregister_device() to start making that device vanish, but 1316 * normally that would be handled by spi_unregister_controller(). 1317 * 1318 * You can also use spi_alloc_device() and spi_add_device() to use a two 1319 * stage registration sequence for each spi_device. This gives the caller 1320 * some more control over the spi_device structure before it is registered, 1321 * but requires that caller to initialize fields that would otherwise 1322 * be defined using the board info. 1323 */ 1324 extern struct spi_device * 1325 spi_alloc_device(struct spi_controller *ctlr); 1326 1327 extern int 1328 spi_add_device(struct spi_device *spi); 1329 1330 extern struct spi_device * 1331 spi_new_device(struct spi_controller *, struct spi_board_info *); 1332 1333 extern void spi_unregister_device(struct spi_device *spi); 1334 1335 extern const struct spi_device_id * 1336 spi_get_device_id(const struct spi_device *sdev); 1337 1338 static inline bool 1339 spi_transfer_is_last(struct spi_controller *ctlr, struct spi_transfer *xfer) 1340 { 1341 return list_is_last(&xfer->transfer_list, &ctlr->cur_msg->transfers); 1342 } 1343 1344 /* OF support code */ 1345 #if IS_ENABLED(CONFIG_OF) 1346 1347 /* must call put_device() when done with returned spi_device device */ 1348 extern struct spi_device * 1349 of_find_spi_device_by_node(struct device_node *node); 1350 1351 #else 1352 1353 static inline struct spi_device * 1354 of_find_spi_device_by_node(struct device_node *node) 1355 { 1356 return NULL; 1357 } 1358 1359 #endif /* IS_ENABLED(CONFIG_OF) */ 1360 1361 /* Compatibility layer */ 1362 #define spi_master spi_controller 1363 1364 #define SPI_MASTER_HALF_DUPLEX SPI_CONTROLLER_HALF_DUPLEX 1365 #define SPI_MASTER_NO_RX SPI_CONTROLLER_NO_RX 1366 #define SPI_MASTER_NO_TX SPI_CONTROLLER_NO_TX 1367 #define SPI_MASTER_MUST_RX SPI_CONTROLLER_MUST_RX 1368 #define SPI_MASTER_MUST_TX SPI_CONTROLLER_MUST_TX 1369 1370 #define spi_master_get_devdata(_ctlr) spi_controller_get_devdata(_ctlr) 1371 #define spi_master_set_devdata(_ctlr, _data) \ 1372 spi_controller_set_devdata(_ctlr, _data) 1373 #define spi_master_get(_ctlr) spi_controller_get(_ctlr) 1374 #define spi_master_put(_ctlr) spi_controller_put(_ctlr) 1375 #define spi_master_suspend(_ctlr) spi_controller_suspend(_ctlr) 1376 #define spi_master_resume(_ctlr) spi_controller_resume(_ctlr) 1377 1378 #define spi_register_master(_ctlr) spi_register_controller(_ctlr) 1379 #define devm_spi_register_master(_dev, _ctlr) \ 1380 devm_spi_register_controller(_dev, _ctlr) 1381 #define spi_unregister_master(_ctlr) spi_unregister_controller(_ctlr) 1382 1383 #endif /* __LINUX_SPI_H */ 1384