1*ab15d248SHans Verkuil /* SPDX-License-Identifier: GPL-2.0-only */ 2b5dcee22SMauro Carvalho Chehab /* 3b5dcee22SMauro Carvalho Chehab * adv7842 - Analog Devices ADV7842 video decoder driver 4b5dcee22SMauro Carvalho Chehab * 5b5dcee22SMauro Carvalho Chehab * Copyright 2013 Cisco Systems, Inc. and/or its affiliates. All rights reserved. 6b5dcee22SMauro Carvalho Chehab */ 7b5dcee22SMauro Carvalho Chehab 8b5dcee22SMauro Carvalho Chehab #ifndef _ADV7842_ 9b5dcee22SMauro Carvalho Chehab #define _ADV7842_ 10b5dcee22SMauro Carvalho Chehab 11b5dcee22SMauro Carvalho Chehab /* Analog input muxing modes (AFE register 0x02, [2:0]) */ 12b5dcee22SMauro Carvalho Chehab enum adv7842_ain_sel { 13b5dcee22SMauro Carvalho Chehab ADV7842_AIN1_2_3_NC_SYNC_1_2 = 0, 14b5dcee22SMauro Carvalho Chehab ADV7842_AIN4_5_6_NC_SYNC_2_1 = 1, 15b5dcee22SMauro Carvalho Chehab ADV7842_AIN7_8_9_NC_SYNC_3_1 = 2, 16b5dcee22SMauro Carvalho Chehab ADV7842_AIN10_11_12_NC_SYNC_4_1 = 3, 17b5dcee22SMauro Carvalho Chehab ADV7842_AIN9_4_5_6_SYNC_2_1 = 4, 18b5dcee22SMauro Carvalho Chehab }; 19b5dcee22SMauro Carvalho Chehab 20b5dcee22SMauro Carvalho Chehab /* 21b5dcee22SMauro Carvalho Chehab * Bus rotation and reordering. This is used to specify component reordering on 22b5dcee22SMauro Carvalho Chehab * the board and describes the components order on the bus when the ADV7842 23b5dcee22SMauro Carvalho Chehab * outputs RGB. 24b5dcee22SMauro Carvalho Chehab */ 25b5dcee22SMauro Carvalho Chehab enum adv7842_bus_order { 26b5dcee22SMauro Carvalho Chehab ADV7842_BUS_ORDER_RGB, /* No operation */ 27b5dcee22SMauro Carvalho Chehab ADV7842_BUS_ORDER_GRB, /* Swap 1-2 */ 28b5dcee22SMauro Carvalho Chehab ADV7842_BUS_ORDER_RBG, /* Swap 2-3 */ 29b5dcee22SMauro Carvalho Chehab ADV7842_BUS_ORDER_BGR, /* Swap 1-3 */ 30b5dcee22SMauro Carvalho Chehab ADV7842_BUS_ORDER_BRG, /* Rotate right */ 31b5dcee22SMauro Carvalho Chehab ADV7842_BUS_ORDER_GBR, /* Rotate left */ 32b5dcee22SMauro Carvalho Chehab }; 33b5dcee22SMauro Carvalho Chehab 34b5dcee22SMauro Carvalho Chehab /* Input Color Space (IO register 0x02, [7:4]) */ 35b5dcee22SMauro Carvalho Chehab enum adv7842_inp_color_space { 36b5dcee22SMauro Carvalho Chehab ADV7842_INP_COLOR_SPACE_LIM_RGB = 0, 37b5dcee22SMauro Carvalho Chehab ADV7842_INP_COLOR_SPACE_FULL_RGB = 1, 38b5dcee22SMauro Carvalho Chehab ADV7842_INP_COLOR_SPACE_LIM_YCbCr_601 = 2, 39b5dcee22SMauro Carvalho Chehab ADV7842_INP_COLOR_SPACE_LIM_YCbCr_709 = 3, 40b5dcee22SMauro Carvalho Chehab ADV7842_INP_COLOR_SPACE_XVYCC_601 = 4, 41b5dcee22SMauro Carvalho Chehab ADV7842_INP_COLOR_SPACE_XVYCC_709 = 5, 42b5dcee22SMauro Carvalho Chehab ADV7842_INP_COLOR_SPACE_FULL_YCbCr_601 = 6, 43b5dcee22SMauro Carvalho Chehab ADV7842_INP_COLOR_SPACE_FULL_YCbCr_709 = 7, 44b5dcee22SMauro Carvalho Chehab ADV7842_INP_COLOR_SPACE_AUTO = 0xf, 45b5dcee22SMauro Carvalho Chehab }; 46b5dcee22SMauro Carvalho Chehab 47b5dcee22SMauro Carvalho Chehab /* Select output format (IO register 0x03, [4:2]) */ 48b5dcee22SMauro Carvalho Chehab enum adv7842_op_format_mode_sel { 49b5dcee22SMauro Carvalho Chehab ADV7842_OP_FORMAT_MODE0 = 0x00, 50b5dcee22SMauro Carvalho Chehab ADV7842_OP_FORMAT_MODE1 = 0x04, 51b5dcee22SMauro Carvalho Chehab ADV7842_OP_FORMAT_MODE2 = 0x08, 52b5dcee22SMauro Carvalho Chehab }; 53b5dcee22SMauro Carvalho Chehab 54b5dcee22SMauro Carvalho Chehab /* Mode of operation */ 55b5dcee22SMauro Carvalho Chehab enum adv7842_mode { 56b5dcee22SMauro Carvalho Chehab ADV7842_MODE_SDP, 57b5dcee22SMauro Carvalho Chehab ADV7842_MODE_COMP, 58b5dcee22SMauro Carvalho Chehab ADV7842_MODE_RGB, 59b5dcee22SMauro Carvalho Chehab ADV7842_MODE_HDMI 60b5dcee22SMauro Carvalho Chehab }; 61b5dcee22SMauro Carvalho Chehab 62b5dcee22SMauro Carvalho Chehab /* Video standard select (IO register 0x00, [5:0]) */ 63b5dcee22SMauro Carvalho Chehab enum adv7842_vid_std_select { 64b5dcee22SMauro Carvalho Chehab /* SDP */ 65b5dcee22SMauro Carvalho Chehab ADV7842_SDP_VID_STD_CVBS_SD_4x1 = 0x01, 66b5dcee22SMauro Carvalho Chehab ADV7842_SDP_VID_STD_YC_SD4_x1 = 0x09, 67b5dcee22SMauro Carvalho Chehab /* RGB */ 68b5dcee22SMauro Carvalho Chehab ADV7842_RGB_VID_STD_AUTO_GRAPH_MODE = 0x07, 69b5dcee22SMauro Carvalho Chehab /* HDMI GR */ 70b5dcee22SMauro Carvalho Chehab ADV7842_HDMI_GR_VID_STD_AUTO_GRAPH_MODE = 0x02, 71b5dcee22SMauro Carvalho Chehab /* HDMI COMP */ 72b5dcee22SMauro Carvalho Chehab ADV7842_HDMI_COMP_VID_STD_HD_1250P = 0x1e, 73b5dcee22SMauro Carvalho Chehab }; 74b5dcee22SMauro Carvalho Chehab 75b5dcee22SMauro Carvalho Chehab enum adv7842_select_input { 76b5dcee22SMauro Carvalho Chehab ADV7842_SELECT_HDMI_PORT_A, 77b5dcee22SMauro Carvalho Chehab ADV7842_SELECT_HDMI_PORT_B, 78b5dcee22SMauro Carvalho Chehab ADV7842_SELECT_VGA_RGB, 79b5dcee22SMauro Carvalho Chehab ADV7842_SELECT_VGA_COMP, 80b5dcee22SMauro Carvalho Chehab ADV7842_SELECT_SDP_CVBS, 81b5dcee22SMauro Carvalho Chehab ADV7842_SELECT_SDP_YC, 82b5dcee22SMauro Carvalho Chehab }; 83b5dcee22SMauro Carvalho Chehab 84b5dcee22SMauro Carvalho Chehab enum adv7842_drive_strength { 85b5dcee22SMauro Carvalho Chehab ADV7842_DR_STR_LOW = 0, 86b5dcee22SMauro Carvalho Chehab ADV7842_DR_STR_MEDIUM_LOW = 1, 87b5dcee22SMauro Carvalho Chehab ADV7842_DR_STR_MEDIUM_HIGH = 2, 88b5dcee22SMauro Carvalho Chehab ADV7842_DR_STR_HIGH = 3, 89b5dcee22SMauro Carvalho Chehab }; 90b5dcee22SMauro Carvalho Chehab 91b5dcee22SMauro Carvalho Chehab struct adv7842_sdp_csc_coeff { 92b5dcee22SMauro Carvalho Chehab bool manual; 93b5dcee22SMauro Carvalho Chehab u16 scaling; 94b5dcee22SMauro Carvalho Chehab u16 A1; 95b5dcee22SMauro Carvalho Chehab u16 A2; 96b5dcee22SMauro Carvalho Chehab u16 A3; 97b5dcee22SMauro Carvalho Chehab u16 A4; 98b5dcee22SMauro Carvalho Chehab u16 B1; 99b5dcee22SMauro Carvalho Chehab u16 B2; 100b5dcee22SMauro Carvalho Chehab u16 B3; 101b5dcee22SMauro Carvalho Chehab u16 B4; 102b5dcee22SMauro Carvalho Chehab u16 C1; 103b5dcee22SMauro Carvalho Chehab u16 C2; 104b5dcee22SMauro Carvalho Chehab u16 C3; 105b5dcee22SMauro Carvalho Chehab u16 C4; 106b5dcee22SMauro Carvalho Chehab }; 107b5dcee22SMauro Carvalho Chehab 108b5dcee22SMauro Carvalho Chehab struct adv7842_sdp_io_sync_adjustment { 109b5dcee22SMauro Carvalho Chehab bool adjust; 110b5dcee22SMauro Carvalho Chehab u16 hs_beg; 111b5dcee22SMauro Carvalho Chehab u16 hs_width; 112b5dcee22SMauro Carvalho Chehab u16 de_beg; 113b5dcee22SMauro Carvalho Chehab u16 de_end; 114b5dcee22SMauro Carvalho Chehab u8 vs_beg_o; 115b5dcee22SMauro Carvalho Chehab u8 vs_beg_e; 116b5dcee22SMauro Carvalho Chehab u8 vs_end_o; 117b5dcee22SMauro Carvalho Chehab u8 vs_end_e; 118b5dcee22SMauro Carvalho Chehab u8 de_v_beg_o; 119b5dcee22SMauro Carvalho Chehab u8 de_v_beg_e; 120b5dcee22SMauro Carvalho Chehab u8 de_v_end_o; 121b5dcee22SMauro Carvalho Chehab u8 de_v_end_e; 122b5dcee22SMauro Carvalho Chehab }; 123b5dcee22SMauro Carvalho Chehab 124b5dcee22SMauro Carvalho Chehab /* Platform dependent definition */ 125b5dcee22SMauro Carvalho Chehab struct adv7842_platform_data { 126b5dcee22SMauro Carvalho Chehab /* chip reset during probe */ 127b5dcee22SMauro Carvalho Chehab unsigned chip_reset:1; 128b5dcee22SMauro Carvalho Chehab 129b5dcee22SMauro Carvalho Chehab /* DIS_PWRDNB: 1 if the PWRDNB pin is unused and unconnected */ 130b5dcee22SMauro Carvalho Chehab unsigned disable_pwrdnb:1; 131b5dcee22SMauro Carvalho Chehab 132b5dcee22SMauro Carvalho Chehab /* DIS_CABLE_DET_RST: 1 if the 5V pins are unused and unconnected */ 133b5dcee22SMauro Carvalho Chehab unsigned disable_cable_det_rst:1; 134b5dcee22SMauro Carvalho Chehab 135b5dcee22SMauro Carvalho Chehab /* Analog input muxing mode */ 136b5dcee22SMauro Carvalho Chehab enum adv7842_ain_sel ain_sel; 137b5dcee22SMauro Carvalho Chehab 138b5dcee22SMauro Carvalho Chehab /* Bus rotation and reordering */ 139b5dcee22SMauro Carvalho Chehab enum adv7842_bus_order bus_order; 140b5dcee22SMauro Carvalho Chehab 141b5dcee22SMauro Carvalho Chehab /* Select output format mode */ 142b5dcee22SMauro Carvalho Chehab enum adv7842_op_format_mode_sel op_format_mode_sel; 143b5dcee22SMauro Carvalho Chehab 144b5dcee22SMauro Carvalho Chehab /* Default mode */ 145b5dcee22SMauro Carvalho Chehab enum adv7842_mode mode; 146b5dcee22SMauro Carvalho Chehab 147b5dcee22SMauro Carvalho Chehab /* Default input */ 148b5dcee22SMauro Carvalho Chehab unsigned input; 149b5dcee22SMauro Carvalho Chehab 150b5dcee22SMauro Carvalho Chehab /* Video standard */ 151b5dcee22SMauro Carvalho Chehab enum adv7842_vid_std_select vid_std_select; 152b5dcee22SMauro Carvalho Chehab 153b5dcee22SMauro Carvalho Chehab /* IO register 0x02 */ 154b5dcee22SMauro Carvalho Chehab unsigned alt_gamma:1; 155b5dcee22SMauro Carvalho Chehab 156b5dcee22SMauro Carvalho Chehab /* IO register 0x05 */ 157b5dcee22SMauro Carvalho Chehab unsigned blank_data:1; 158b5dcee22SMauro Carvalho Chehab unsigned insert_av_codes:1; 159b5dcee22SMauro Carvalho Chehab unsigned replicate_av_codes:1; 160b5dcee22SMauro Carvalho Chehab 161b5dcee22SMauro Carvalho Chehab /* IO register 0x30 */ 162b5dcee22SMauro Carvalho Chehab unsigned output_bus_lsb_to_msb:1; 163b5dcee22SMauro Carvalho Chehab 164b5dcee22SMauro Carvalho Chehab /* IO register 0x14 */ 165b5dcee22SMauro Carvalho Chehab enum adv7842_drive_strength dr_str_data; 166b5dcee22SMauro Carvalho Chehab enum adv7842_drive_strength dr_str_clk; 167b5dcee22SMauro Carvalho Chehab enum adv7842_drive_strength dr_str_sync; 168b5dcee22SMauro Carvalho Chehab 169b5dcee22SMauro Carvalho Chehab /* 170b5dcee22SMauro Carvalho Chehab * IO register 0x19: Adjustment to the LLC DLL phase in 171b5dcee22SMauro Carvalho Chehab * increments of 1/32 of a clock period. 172b5dcee22SMauro Carvalho Chehab */ 173b5dcee22SMauro Carvalho Chehab unsigned llc_dll_phase:5; 174b5dcee22SMauro Carvalho Chehab 175b5dcee22SMauro Carvalho Chehab /* External RAM for 3-D comb or frame synchronizer */ 176b5dcee22SMauro Carvalho Chehab unsigned sd_ram_size; /* ram size in MB */ 177b5dcee22SMauro Carvalho Chehab unsigned sd_ram_ddr:1; /* ddr or sdr sdram */ 178b5dcee22SMauro Carvalho Chehab 179b5dcee22SMauro Carvalho Chehab /* HDMI free run, CP-reg 0xBA */ 180b5dcee22SMauro Carvalho Chehab unsigned hdmi_free_run_enable:1; 181b5dcee22SMauro Carvalho Chehab /* 0 = Mode 0: run when there is no TMDS clock 182b5dcee22SMauro Carvalho Chehab 1 = Mode 1: run when there is no TMDS clock or the 183b5dcee22SMauro Carvalho Chehab video resolution does not match programmed one. */ 184b5dcee22SMauro Carvalho Chehab unsigned hdmi_free_run_mode:1; 185b5dcee22SMauro Carvalho Chehab 186b5dcee22SMauro Carvalho Chehab /* SDP free run, CP-reg 0xDD */ 187b5dcee22SMauro Carvalho Chehab unsigned sdp_free_run_auto:1; 188b5dcee22SMauro Carvalho Chehab unsigned sdp_free_run_man_col_en:1; 189b5dcee22SMauro Carvalho Chehab unsigned sdp_free_run_cbar_en:1; 190b5dcee22SMauro Carvalho Chehab unsigned sdp_free_run_force:1; 191b5dcee22SMauro Carvalho Chehab 192b5dcee22SMauro Carvalho Chehab /* HPA manual (0) or auto (1), affects HDMI register 0x69 */ 193b5dcee22SMauro Carvalho Chehab unsigned hpa_auto:1; 194b5dcee22SMauro Carvalho Chehab 195b5dcee22SMauro Carvalho Chehab struct adv7842_sdp_csc_coeff sdp_csc_coeff; 196b5dcee22SMauro Carvalho Chehab 197b5dcee22SMauro Carvalho Chehab struct adv7842_sdp_io_sync_adjustment sdp_io_sync_625; 198b5dcee22SMauro Carvalho Chehab struct adv7842_sdp_io_sync_adjustment sdp_io_sync_525; 199b5dcee22SMauro Carvalho Chehab 200b5dcee22SMauro Carvalho Chehab /* i2c addresses */ 201b5dcee22SMauro Carvalho Chehab u8 i2c_sdp_io; 202b5dcee22SMauro Carvalho Chehab u8 i2c_sdp; 203b5dcee22SMauro Carvalho Chehab u8 i2c_cp; 204b5dcee22SMauro Carvalho Chehab u8 i2c_vdp; 205b5dcee22SMauro Carvalho Chehab u8 i2c_afe; 206b5dcee22SMauro Carvalho Chehab u8 i2c_hdmi; 207b5dcee22SMauro Carvalho Chehab u8 i2c_repeater; 208b5dcee22SMauro Carvalho Chehab u8 i2c_edid; 209b5dcee22SMauro Carvalho Chehab u8 i2c_infoframe; 210b5dcee22SMauro Carvalho Chehab u8 i2c_cec; 211b5dcee22SMauro Carvalho Chehab u8 i2c_avlink; 212b5dcee22SMauro Carvalho Chehab }; 213b5dcee22SMauro Carvalho Chehab 214b5dcee22SMauro Carvalho Chehab #define V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE (V4L2_CID_DV_CLASS_BASE + 0x1000) 215b5dcee22SMauro Carvalho Chehab #define V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL (V4L2_CID_DV_CLASS_BASE + 0x1001) 216b5dcee22SMauro Carvalho Chehab #define V4L2_CID_ADV_RX_FREE_RUN_COLOR (V4L2_CID_DV_CLASS_BASE + 0x1002) 217b5dcee22SMauro Carvalho Chehab 218b5dcee22SMauro Carvalho Chehab /* custom ioctl, used to test the external RAM that's used by the 219b5dcee22SMauro Carvalho Chehab * deinterlacer. */ 220b5dcee22SMauro Carvalho Chehab #define ADV7842_CMD_RAM_TEST _IO('V', BASE_VIDIOC_PRIVATE) 221b5dcee22SMauro Carvalho Chehab 222b5dcee22SMauro Carvalho Chehab #define ADV7842_EDID_PORT_A 0 223b5dcee22SMauro Carvalho Chehab #define ADV7842_EDID_PORT_B 1 224b5dcee22SMauro Carvalho Chehab #define ADV7842_EDID_PORT_VGA 2 225b5dcee22SMauro Carvalho Chehab #define ADV7842_PAD_SOURCE 3 226b5dcee22SMauro Carvalho Chehab 227b5dcee22SMauro Carvalho Chehab #endif 228