1*d4ab3470SDennis Dalessandro /* 2*d4ab3470SDennis Dalessandro * Copyright (c) 2014 Intel Corporation. All rights reserved. 3*d4ab3470SDennis Dalessandro * 4*d4ab3470SDennis Dalessandro * This software is available to you under a choice of one of two 5*d4ab3470SDennis Dalessandro * licenses. You may choose to be licensed under the terms of the GNU 6*d4ab3470SDennis Dalessandro * General Public License (GPL) Version 2, available from the file 7*d4ab3470SDennis Dalessandro * COPYING in the main directory of this source tree, or the 8*d4ab3470SDennis Dalessandro * OpenIB.org BSD license below: 9*d4ab3470SDennis Dalessandro * 10*d4ab3470SDennis Dalessandro * Redistribution and use in source and binary forms, with or 11*d4ab3470SDennis Dalessandro * without modification, are permitted provided that the following 12*d4ab3470SDennis Dalessandro * conditions are met: 13*d4ab3470SDennis Dalessandro * 14*d4ab3470SDennis Dalessandro * - Redistributions of source code must retain the above 15*d4ab3470SDennis Dalessandro * copyright notice, this list of conditions and the following 16*d4ab3470SDennis Dalessandro * disclaimer. 17*d4ab3470SDennis Dalessandro * 18*d4ab3470SDennis Dalessandro * - Redistributions in binary form must reproduce the above 19*d4ab3470SDennis Dalessandro * copyright notice, this list of conditions and the following 20*d4ab3470SDennis Dalessandro * disclaimer in the documentation and/or other materials 21*d4ab3470SDennis Dalessandro * provided with the distribution. 22*d4ab3470SDennis Dalessandro * 23*d4ab3470SDennis Dalessandro * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24*d4ab3470SDennis Dalessandro * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25*d4ab3470SDennis Dalessandro * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26*d4ab3470SDennis Dalessandro * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27*d4ab3470SDennis Dalessandro * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28*d4ab3470SDennis Dalessandro * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29*d4ab3470SDennis Dalessandro * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30*d4ab3470SDennis Dalessandro * SOFTWARE. 31*d4ab3470SDennis Dalessandro */ 32*d4ab3470SDennis Dalessandro 33*d4ab3470SDennis Dalessandro #if !defined(OPA_PORT_INFO_H) 34*d4ab3470SDennis Dalessandro #define OPA_PORT_INFO_H 35*d4ab3470SDennis Dalessandro 36*d4ab3470SDennis Dalessandro /* Temporary until HFI driver is updated */ 37*d4ab3470SDennis Dalessandro #ifndef USE_PI_LED_ENABLE 38*d4ab3470SDennis Dalessandro #define USE_PI_LED_ENABLE 0 39*d4ab3470SDennis Dalessandro #endif 40*d4ab3470SDennis Dalessandro 41*d4ab3470SDennis Dalessandro #define OPA_PORT_LINK_MODE_NOP 0 /* No change */ 42*d4ab3470SDennis Dalessandro #define OPA_PORT_LINK_MODE_OPA 4 /* Port mode is OPA */ 43*d4ab3470SDennis Dalessandro 44*d4ab3470SDennis Dalessandro #define OPA_PORT_PACKET_FORMAT_NOP 0 /* No change */ 45*d4ab3470SDennis Dalessandro #define OPA_PORT_PACKET_FORMAT_8B 1 /* Format 8B */ 46*d4ab3470SDennis Dalessandro #define OPA_PORT_PACKET_FORMAT_9B 2 /* Format 9B */ 47*d4ab3470SDennis Dalessandro #define OPA_PORT_PACKET_FORMAT_10B 4 /* Format 10B */ 48*d4ab3470SDennis Dalessandro #define OPA_PORT_PACKET_FORMAT_16B 8 /* Format 16B */ 49*d4ab3470SDennis Dalessandro 50*d4ab3470SDennis Dalessandro #define OPA_PORT_LTP_CRC_MODE_NONE 0 /* No change */ 51*d4ab3470SDennis Dalessandro #define OPA_PORT_LTP_CRC_MODE_14 1 /* 14-bit LTP CRC mode (optional) */ 52*d4ab3470SDennis Dalessandro #define OPA_PORT_LTP_CRC_MODE_16 2 /* 16-bit LTP CRC mode */ 53*d4ab3470SDennis Dalessandro #define OPA_PORT_LTP_CRC_MODE_48 4 /* 48-bit LTP CRC mode (optional) */ 54*d4ab3470SDennis Dalessandro #define OPA_PORT_LTP_CRC_MODE_PER_LANE 8 /* 12/16-bit per lane LTP CRC mode */ 55*d4ab3470SDennis Dalessandro 56*d4ab3470SDennis Dalessandro /* Link Down / Neighbor Link Down Reason; indicated as follows: */ 57*d4ab3470SDennis Dalessandro #define OPA_LINKDOWN_REASON_NONE 0 /* No specified reason */ 58*d4ab3470SDennis Dalessandro #define OPA_LINKDOWN_REASON_RCV_ERROR_0 1 59*d4ab3470SDennis Dalessandro #define OPA_LINKDOWN_REASON_BAD_PKT_LEN 2 60*d4ab3470SDennis Dalessandro #define OPA_LINKDOWN_REASON_PKT_TOO_LONG 3 61*d4ab3470SDennis Dalessandro #define OPA_LINKDOWN_REASON_PKT_TOO_SHORT 4 62*d4ab3470SDennis Dalessandro #define OPA_LINKDOWN_REASON_BAD_SLID 5 63*d4ab3470SDennis Dalessandro #define OPA_LINKDOWN_REASON_BAD_DLID 6 64*d4ab3470SDennis Dalessandro #define OPA_LINKDOWN_REASON_BAD_L2 7 65*d4ab3470SDennis Dalessandro #define OPA_LINKDOWN_REASON_BAD_SC 8 66*d4ab3470SDennis Dalessandro #define OPA_LINKDOWN_REASON_RCV_ERROR_8 9 67*d4ab3470SDennis Dalessandro #define OPA_LINKDOWN_REASON_BAD_MID_TAIL 10 68*d4ab3470SDennis Dalessandro #define OPA_LINKDOWN_REASON_RCV_ERROR_10 11 69*d4ab3470SDennis Dalessandro #define OPA_LINKDOWN_REASON_PREEMPT_ERROR 12 70*d4ab3470SDennis Dalessandro #define OPA_LINKDOWN_REASON_PREEMPT_VL15 13 71*d4ab3470SDennis Dalessandro #define OPA_LINKDOWN_REASON_BAD_VL_MARKER 14 72*d4ab3470SDennis Dalessandro #define OPA_LINKDOWN_REASON_RCV_ERROR_14 15 73*d4ab3470SDennis Dalessandro #define OPA_LINKDOWN_REASON_RCV_ERROR_15 16 74*d4ab3470SDennis Dalessandro #define OPA_LINKDOWN_REASON_BAD_HEAD_DIST 17 75*d4ab3470SDennis Dalessandro #define OPA_LINKDOWN_REASON_BAD_TAIL_DIST 18 76*d4ab3470SDennis Dalessandro #define OPA_LINKDOWN_REASON_BAD_CTRL_DIST 19 77*d4ab3470SDennis Dalessandro #define OPA_LINKDOWN_REASON_BAD_CREDIT_ACK 20 78*d4ab3470SDennis Dalessandro #define OPA_LINKDOWN_REASON_UNSUPPORTED_VL_MARKER 21 79*d4ab3470SDennis Dalessandro #define OPA_LINKDOWN_REASON_BAD_PREEMPT 22 80*d4ab3470SDennis Dalessandro #define OPA_LINKDOWN_REASON_BAD_CONTROL_FLIT 23 81*d4ab3470SDennis Dalessandro #define OPA_LINKDOWN_REASON_EXCEED_MULTICAST_LIMIT 24 82*d4ab3470SDennis Dalessandro #define OPA_LINKDOWN_REASON_RCV_ERROR_24 25 83*d4ab3470SDennis Dalessandro #define OPA_LINKDOWN_REASON_RCV_ERROR_25 26 84*d4ab3470SDennis Dalessandro #define OPA_LINKDOWN_REASON_RCV_ERROR_26 27 85*d4ab3470SDennis Dalessandro #define OPA_LINKDOWN_REASON_RCV_ERROR_27 28 86*d4ab3470SDennis Dalessandro #define OPA_LINKDOWN_REASON_RCV_ERROR_28 29 87*d4ab3470SDennis Dalessandro #define OPA_LINKDOWN_REASON_RCV_ERROR_29 30 88*d4ab3470SDennis Dalessandro #define OPA_LINKDOWN_REASON_RCV_ERROR_30 31 89*d4ab3470SDennis Dalessandro #define OPA_LINKDOWN_REASON_EXCESSIVE_BUFFER_OVERRUN 32 90*d4ab3470SDennis Dalessandro #define OPA_LINKDOWN_REASON_UNKNOWN 33 91*d4ab3470SDennis Dalessandro /* 34 -reserved */ 92*d4ab3470SDennis Dalessandro #define OPA_LINKDOWN_REASON_REBOOT 35 93*d4ab3470SDennis Dalessandro #define OPA_LINKDOWN_REASON_NEIGHBOR_UNKNOWN 36 94*d4ab3470SDennis Dalessandro /* 37-38 reserved */ 95*d4ab3470SDennis Dalessandro #define OPA_LINKDOWN_REASON_FM_BOUNCE 39 96*d4ab3470SDennis Dalessandro #define OPA_LINKDOWN_REASON_SPEED_POLICY 40 97*d4ab3470SDennis Dalessandro #define OPA_LINKDOWN_REASON_WIDTH_POLICY 41 98*d4ab3470SDennis Dalessandro /* 42-48 reserved */ 99*d4ab3470SDennis Dalessandro #define OPA_LINKDOWN_REASON_DISCONNECTED 49 100*d4ab3470SDennis Dalessandro #define OPA_LINKDOWN_REASONLOCAL_MEDIA_NOT_INSTALLED 50 101*d4ab3470SDennis Dalessandro #define OPA_LINKDOWN_REASON_NOT_INSTALLED 51 102*d4ab3470SDennis Dalessandro #define OPA_LINKDOWN_REASON_CHASSIS_CONFIG 52 103*d4ab3470SDennis Dalessandro /* 53 reserved */ 104*d4ab3470SDennis Dalessandro #define OPA_LINKDOWN_REASON_END_TO_END_NOT_INSTALLED 54 105*d4ab3470SDennis Dalessandro /* 55 reserved */ 106*d4ab3470SDennis Dalessandro #define OPA_LINKDOWN_REASON_POWER_POLICY 56 107*d4ab3470SDennis Dalessandro #define OPA_LINKDOWN_REASON_LINKSPEED_POLICY 57 108*d4ab3470SDennis Dalessandro #define OPA_LINKDOWN_REASON_LINKWIDTH_POLICY 58 109*d4ab3470SDennis Dalessandro /* 59 reserved */ 110*d4ab3470SDennis Dalessandro #define OPA_LINKDOWN_REASON_SWITCH_MGMT 60 111*d4ab3470SDennis Dalessandro #define OPA_LINKDOWN_REASON_SMA_DISABLED 61 112*d4ab3470SDennis Dalessandro /* 62 reserved */ 113*d4ab3470SDennis Dalessandro #define OPA_LINKDOWN_REASON_TRANSIENT 63 114*d4ab3470SDennis Dalessandro /* 64-255 reserved */ 115*d4ab3470SDennis Dalessandro 116*d4ab3470SDennis Dalessandro /* OPA Link Init reason; indicated as follows: */ 117*d4ab3470SDennis Dalessandro /* 3-7; 11-15 reserved; 8-15 cleared on Polling->LinkUp */ 118*d4ab3470SDennis Dalessandro #define OPA_LINKINIT_REASON_NOP 0 119*d4ab3470SDennis Dalessandro #define OPA_LINKINIT_REASON_LINKUP (1 << 4) 120*d4ab3470SDennis Dalessandro #define OPA_LINKINIT_REASON_FLAPPING (2 << 4) 121*d4ab3470SDennis Dalessandro #define OPA_LINKINIT_REASON_CLEAR (8 << 4) 122*d4ab3470SDennis Dalessandro #define OPA_LINKINIT_OUTSIDE_POLICY (8 << 4) 123*d4ab3470SDennis Dalessandro #define OPA_LINKINIT_QUARANTINED (9 << 4) 124*d4ab3470SDennis Dalessandro #define OPA_LINKINIT_INSUFIC_CAPABILITY (10 << 4) 125*d4ab3470SDennis Dalessandro 126*d4ab3470SDennis Dalessandro #define OPA_LINK_SPEED_NOP 0x0000 /* Reserved (1-5 Gbps) */ 127*d4ab3470SDennis Dalessandro #define OPA_LINK_SPEED_12_5G 0x0001 /* 12.5 Gbps */ 128*d4ab3470SDennis Dalessandro #define OPA_LINK_SPEED_25G 0x0002 /* 25.78125? Gbps (EDR) */ 129*d4ab3470SDennis Dalessandro 130*d4ab3470SDennis Dalessandro #define OPA_LINK_WIDTH_1X 0x0001 131*d4ab3470SDennis Dalessandro #define OPA_LINK_WIDTH_2X 0x0002 132*d4ab3470SDennis Dalessandro #define OPA_LINK_WIDTH_3X 0x0004 133*d4ab3470SDennis Dalessandro #define OPA_LINK_WIDTH_4X 0x0008 134*d4ab3470SDennis Dalessandro 135*d4ab3470SDennis Dalessandro #define OPA_CAP_MASK3_IsSnoopSupported (1 << 7) 136*d4ab3470SDennis Dalessandro #define OPA_CAP_MASK3_IsAsyncSC2VLSupported (1 << 6) 137*d4ab3470SDennis Dalessandro #define OPA_CAP_MASK3_IsAddrRangeConfigSupported (1 << 5) 138*d4ab3470SDennis Dalessandro #define OPA_CAP_MASK3_IsPassThroughSupported (1 << 4) 139*d4ab3470SDennis Dalessandro #define OPA_CAP_MASK3_IsSharedSpaceSupported (1 << 3) 140*d4ab3470SDennis Dalessandro /* reserved (1 << 2) */ 141*d4ab3470SDennis Dalessandro #define OPA_CAP_MASK3_IsVLMarkerSupported (1 << 1) 142*d4ab3470SDennis Dalessandro #define OPA_CAP_MASK3_IsVLrSupported (1 << 0) 143*d4ab3470SDennis Dalessandro 144*d4ab3470SDennis Dalessandro /** 145*d4ab3470SDennis Dalessandro * new MTU values 146*d4ab3470SDennis Dalessandro */ 147*d4ab3470SDennis Dalessandro enum { 148*d4ab3470SDennis Dalessandro OPA_MTU_8192 = 6, 149*d4ab3470SDennis Dalessandro OPA_MTU_10240 = 7, 150*d4ab3470SDennis Dalessandro }; 151*d4ab3470SDennis Dalessandro 152*d4ab3470SDennis Dalessandro enum { 153*d4ab3470SDennis Dalessandro OPA_PORT_PHYS_CONF_DISCONNECTED = 0, 154*d4ab3470SDennis Dalessandro OPA_PORT_PHYS_CONF_STANDARD = 1, 155*d4ab3470SDennis Dalessandro OPA_PORT_PHYS_CONF_FIXED = 2, 156*d4ab3470SDennis Dalessandro OPA_PORT_PHYS_CONF_VARIABLE = 3, 157*d4ab3470SDennis Dalessandro OPA_PORT_PHYS_CONF_SI_PHOTO = 4 158*d4ab3470SDennis Dalessandro }; 159*d4ab3470SDennis Dalessandro 160*d4ab3470SDennis Dalessandro enum port_info_field_masks { 161*d4ab3470SDennis Dalessandro /* vl.cap */ 162*d4ab3470SDennis Dalessandro OPA_PI_MASK_VL_CAP = 0x1F, 163*d4ab3470SDennis Dalessandro /* port_states.ledenable_offlinereason */ 164*d4ab3470SDennis Dalessandro OPA_PI_MASK_OFFLINE_REASON = 0x0F, 165*d4ab3470SDennis Dalessandro OPA_PI_MASK_LED_ENABLE = 0x40, 166*d4ab3470SDennis Dalessandro /* port_states.unsleepstate_downdefstate */ 167*d4ab3470SDennis Dalessandro OPA_PI_MASK_UNSLEEP_STATE = 0xF0, 168*d4ab3470SDennis Dalessandro OPA_PI_MASK_DOWNDEF_STATE = 0x0F, 169*d4ab3470SDennis Dalessandro /* port_states.portphysstate_portstate */ 170*d4ab3470SDennis Dalessandro OPA_PI_MASK_PORT_PHYSICAL_STATE = 0xF0, 171*d4ab3470SDennis Dalessandro OPA_PI_MASK_PORT_STATE = 0x0F, 172*d4ab3470SDennis Dalessandro /* port_phys_conf */ 173*d4ab3470SDennis Dalessandro OPA_PI_MASK_PORT_PHYSICAL_CONF = 0x0F, 174*d4ab3470SDennis Dalessandro /* collectivemask_multicastmask */ 175*d4ab3470SDennis Dalessandro OPA_PI_MASK_COLLECT_MASK = 0x38, 176*d4ab3470SDennis Dalessandro OPA_PI_MASK_MULTICAST_MASK = 0x07, 177*d4ab3470SDennis Dalessandro /* mkeyprotect_lmc */ 178*d4ab3470SDennis Dalessandro OPA_PI_MASK_MKEY_PROT_BIT = 0xC0, 179*d4ab3470SDennis Dalessandro OPA_PI_MASK_LMC = 0x0F, 180*d4ab3470SDennis Dalessandro /* smsl */ 181*d4ab3470SDennis Dalessandro OPA_PI_MASK_SMSL = 0x1F, 182*d4ab3470SDennis Dalessandro /* partenforce_filterraw */ 183*d4ab3470SDennis Dalessandro /* Filter Raw In/Out bits 1 and 2 were removed */ 184*d4ab3470SDennis Dalessandro OPA_PI_MASK_LINKINIT_REASON = 0xF0, 185*d4ab3470SDennis Dalessandro OPA_PI_MASK_PARTITION_ENFORCE_IN = 0x08, 186*d4ab3470SDennis Dalessandro OPA_PI_MASK_PARTITION_ENFORCE_OUT = 0x04, 187*d4ab3470SDennis Dalessandro /* operational_vls */ 188*d4ab3470SDennis Dalessandro OPA_PI_MASK_OPERATIONAL_VL = 0x1F, 189*d4ab3470SDennis Dalessandro /* sa_qp */ 190*d4ab3470SDennis Dalessandro OPA_PI_MASK_SA_QP = 0x00FFFFFF, 191*d4ab3470SDennis Dalessandro /* sm_trap_qp */ 192*d4ab3470SDennis Dalessandro OPA_PI_MASK_SM_TRAP_QP = 0x00FFFFFF, 193*d4ab3470SDennis Dalessandro /* localphy_overrun_errors */ 194*d4ab3470SDennis Dalessandro OPA_PI_MASK_LOCAL_PHY_ERRORS = 0xF0, 195*d4ab3470SDennis Dalessandro OPA_PI_MASK_OVERRUN_ERRORS = 0x0F, 196*d4ab3470SDennis Dalessandro /* clientrereg_subnettimeout */ 197*d4ab3470SDennis Dalessandro OPA_PI_MASK_CLIENT_REREGISTER = 0x80, 198*d4ab3470SDennis Dalessandro OPA_PI_MASK_SUBNET_TIMEOUT = 0x1F, 199*d4ab3470SDennis Dalessandro /* port_link_mode */ 200*d4ab3470SDennis Dalessandro OPA_PI_MASK_PORT_LINK_SUPPORTED = (0x001F << 10), 201*d4ab3470SDennis Dalessandro OPA_PI_MASK_PORT_LINK_ENABLED = (0x001F << 5), 202*d4ab3470SDennis Dalessandro OPA_PI_MASK_PORT_LINK_ACTIVE = (0x001F << 0), 203*d4ab3470SDennis Dalessandro /* port_link_crc_mode */ 204*d4ab3470SDennis Dalessandro OPA_PI_MASK_PORT_LINK_CRC_SUPPORTED = 0x0F00, 205*d4ab3470SDennis Dalessandro OPA_PI_MASK_PORT_LINK_CRC_ENABLED = 0x00F0, 206*d4ab3470SDennis Dalessandro OPA_PI_MASK_PORT_LINK_CRC_ACTIVE = 0x000F, 207*d4ab3470SDennis Dalessandro /* port_mode */ 208*d4ab3470SDennis Dalessandro OPA_PI_MASK_PORT_MODE_SECURITY_CHECK = 0x0001, 209*d4ab3470SDennis Dalessandro OPA_PI_MASK_PORT_MODE_16B_TRAP_QUERY = 0x0002, 210*d4ab3470SDennis Dalessandro OPA_PI_MASK_PORT_MODE_PKEY_CONVERT = 0x0004, 211*d4ab3470SDennis Dalessandro OPA_PI_MASK_PORT_MODE_SC2SC_MAPPING = 0x0008, 212*d4ab3470SDennis Dalessandro OPA_PI_MASK_PORT_MODE_VL_MARKER = 0x0010, 213*d4ab3470SDennis Dalessandro OPA_PI_MASK_PORT_PASS_THROUGH = 0x0020, 214*d4ab3470SDennis Dalessandro OPA_PI_MASK_PORT_ACTIVE_OPTOMIZE = 0x0040, 215*d4ab3470SDennis Dalessandro /* flit_control.interleave */ 216*d4ab3470SDennis Dalessandro OPA_PI_MASK_INTERLEAVE_DIST_SUP = (0x0003 << 12), 217*d4ab3470SDennis Dalessandro OPA_PI_MASK_INTERLEAVE_DIST_ENABLE = (0x0003 << 10), 218*d4ab3470SDennis Dalessandro OPA_PI_MASK_INTERLEAVE_MAX_NEST_TX = (0x001F << 5), 219*d4ab3470SDennis Dalessandro OPA_PI_MASK_INTERLEAVE_MAX_NEST_RX = (0x001F << 0), 220*d4ab3470SDennis Dalessandro 221*d4ab3470SDennis Dalessandro /* port_error_action */ 222*d4ab3470SDennis Dalessandro OPA_PI_MASK_EX_BUFFER_OVERRUN = 0x80000000, 223*d4ab3470SDennis Dalessandro /* 7 bits reserved */ 224*d4ab3470SDennis Dalessandro OPA_PI_MASK_FM_CFG_ERR_EXCEED_MULTICAST_LIMIT = 0x00800000, 225*d4ab3470SDennis Dalessandro OPA_PI_MASK_FM_CFG_BAD_CONTROL_FLIT = 0x00400000, 226*d4ab3470SDennis Dalessandro OPA_PI_MASK_FM_CFG_BAD_PREEMPT = 0x00200000, 227*d4ab3470SDennis Dalessandro OPA_PI_MASK_FM_CFG_UNSUPPORTED_VL_MARKER = 0x00100000, 228*d4ab3470SDennis Dalessandro OPA_PI_MASK_FM_CFG_BAD_CRDT_ACK = 0x00080000, 229*d4ab3470SDennis Dalessandro OPA_PI_MASK_FM_CFG_BAD_CTRL_DIST = 0x00040000, 230*d4ab3470SDennis Dalessandro OPA_PI_MASK_FM_CFG_BAD_TAIL_DIST = 0x00020000, 231*d4ab3470SDennis Dalessandro OPA_PI_MASK_FM_CFG_BAD_HEAD_DIST = 0x00010000, 232*d4ab3470SDennis Dalessandro /* 2 bits reserved */ 233*d4ab3470SDennis Dalessandro OPA_PI_MASK_PORT_RCV_BAD_VL_MARKER = 0x00002000, 234*d4ab3470SDennis Dalessandro OPA_PI_MASK_PORT_RCV_PREEMPT_VL15 = 0x00001000, 235*d4ab3470SDennis Dalessandro OPA_PI_MASK_PORT_RCV_PREEMPT_ERROR = 0x00000800, 236*d4ab3470SDennis Dalessandro /* 1 bit reserved */ 237*d4ab3470SDennis Dalessandro OPA_PI_MASK_PORT_RCV_BAD_MidTail = 0x00000200, 238*d4ab3470SDennis Dalessandro /* 1 bit reserved */ 239*d4ab3470SDennis Dalessandro OPA_PI_MASK_PORT_RCV_BAD_SC = 0x00000080, 240*d4ab3470SDennis Dalessandro OPA_PI_MASK_PORT_RCV_BAD_L2 = 0x00000040, 241*d4ab3470SDennis Dalessandro OPA_PI_MASK_PORT_RCV_BAD_DLID = 0x00000020, 242*d4ab3470SDennis Dalessandro OPA_PI_MASK_PORT_RCV_BAD_SLID = 0x00000010, 243*d4ab3470SDennis Dalessandro OPA_PI_MASK_PORT_RCV_PKTLEN_TOOSHORT = 0x00000008, 244*d4ab3470SDennis Dalessandro OPA_PI_MASK_PORT_RCV_PKTLEN_TOOLONG = 0x00000004, 245*d4ab3470SDennis Dalessandro OPA_PI_MASK_PORT_RCV_BAD_PKTLEN = 0x00000002, 246*d4ab3470SDennis Dalessandro OPA_PI_MASK_PORT_RCV_BAD_LT = 0x00000001, 247*d4ab3470SDennis Dalessandro 248*d4ab3470SDennis Dalessandro /* pass_through.res_drctl */ 249*d4ab3470SDennis Dalessandro OPA_PI_MASK_PASS_THROUGH_DR_CONTROL = 0x01, 250*d4ab3470SDennis Dalessandro 251*d4ab3470SDennis Dalessandro /* buffer_units */ 252*d4ab3470SDennis Dalessandro OPA_PI_MASK_BUF_UNIT_VL15_INIT = (0x00000FFF << 11), 253*d4ab3470SDennis Dalessandro OPA_PI_MASK_BUF_UNIT_VL15_CREDIT_RATE = (0x0000001F << 6), 254*d4ab3470SDennis Dalessandro OPA_PI_MASK_BUF_UNIT_CREDIT_ACK = (0x00000003 << 3), 255*d4ab3470SDennis Dalessandro OPA_PI_MASK_BUF_UNIT_BUF_ALLOC = (0x00000003 << 0), 256*d4ab3470SDennis Dalessandro 257*d4ab3470SDennis Dalessandro /* neigh_mtu.pvlx_to_mtu */ 258*d4ab3470SDennis Dalessandro OPA_PI_MASK_NEIGH_MTU_PVL0 = 0xF0, 259*d4ab3470SDennis Dalessandro OPA_PI_MASK_NEIGH_MTU_PVL1 = 0x0F, 260*d4ab3470SDennis Dalessandro 261*d4ab3470SDennis Dalessandro /* neigh_mtu.vlstall_hoq_life */ 262*d4ab3470SDennis Dalessandro OPA_PI_MASK_VL_STALL = (0x03 << 5), 263*d4ab3470SDennis Dalessandro OPA_PI_MASK_HOQ_LIFE = (0x1F << 0), 264*d4ab3470SDennis Dalessandro 265*d4ab3470SDennis Dalessandro /* port_neigh_mode */ 266*d4ab3470SDennis Dalessandro OPA_PI_MASK_NEIGH_MGMT_ALLOWED = (0x01 << 3), 267*d4ab3470SDennis Dalessandro OPA_PI_MASK_NEIGH_FW_AUTH_BYPASS = (0x01 << 2), 268*d4ab3470SDennis Dalessandro OPA_PI_MASK_NEIGH_NODE_TYPE = (0x03 << 0), 269*d4ab3470SDennis Dalessandro 270*d4ab3470SDennis Dalessandro /* resptime_value */ 271*d4ab3470SDennis Dalessandro OPA_PI_MASK_RESPONSE_TIME_VALUE = 0x1F, 272*d4ab3470SDennis Dalessandro 273*d4ab3470SDennis Dalessandro /* mtucap */ 274*d4ab3470SDennis Dalessandro OPA_PI_MASK_MTU_CAP = 0x0F, 275*d4ab3470SDennis Dalessandro }; 276*d4ab3470SDennis Dalessandro 277*d4ab3470SDennis Dalessandro #if USE_PI_LED_ENABLE 278*d4ab3470SDennis Dalessandro struct opa_port_states { 279*d4ab3470SDennis Dalessandro u8 reserved; 280*d4ab3470SDennis Dalessandro u8 ledenable_offlinereason; /* 1 res, 1 bit, 6 bits */ 281*d4ab3470SDennis Dalessandro u8 reserved2; 282*d4ab3470SDennis Dalessandro u8 portphysstate_portstate; /* 4 bits, 4 bits */ 283*d4ab3470SDennis Dalessandro }; 284*d4ab3470SDennis Dalessandro #define PI_LED_ENABLE_SUP 1 285*d4ab3470SDennis Dalessandro #else 286*d4ab3470SDennis Dalessandro struct opa_port_states { 287*d4ab3470SDennis Dalessandro u8 reserved; 288*d4ab3470SDennis Dalessandro u8 offline_reason; /* 2 res, 6 bits */ 289*d4ab3470SDennis Dalessandro u8 reserved2; 290*d4ab3470SDennis Dalessandro u8 portphysstate_portstate; /* 4 bits, 4 bits */ 291*d4ab3470SDennis Dalessandro }; 292*d4ab3470SDennis Dalessandro #define PI_LED_ENABLE_SUP 0 293*d4ab3470SDennis Dalessandro #endif 294*d4ab3470SDennis Dalessandro 295*d4ab3470SDennis Dalessandro struct opa_port_state_info { 296*d4ab3470SDennis Dalessandro struct opa_port_states port_states; 297*d4ab3470SDennis Dalessandro u16 link_width_downgrade_tx_active; 298*d4ab3470SDennis Dalessandro u16 link_width_downgrade_rx_active; 299*d4ab3470SDennis Dalessandro }; 300*d4ab3470SDennis Dalessandro 301*d4ab3470SDennis Dalessandro struct opa_port_info { 302*d4ab3470SDennis Dalessandro __be32 lid; 303*d4ab3470SDennis Dalessandro __be32 flow_control_mask; 304*d4ab3470SDennis Dalessandro 305*d4ab3470SDennis Dalessandro struct { 306*d4ab3470SDennis Dalessandro u8 res; /* was inittype */ 307*d4ab3470SDennis Dalessandro u8 cap; /* 3 res, 5 bits */ 308*d4ab3470SDennis Dalessandro __be16 high_limit; 309*d4ab3470SDennis Dalessandro __be16 preempt_limit; 310*d4ab3470SDennis Dalessandro u8 arb_high_cap; 311*d4ab3470SDennis Dalessandro u8 arb_low_cap; 312*d4ab3470SDennis Dalessandro } vl; 313*d4ab3470SDennis Dalessandro 314*d4ab3470SDennis Dalessandro struct opa_port_states port_states; 315*d4ab3470SDennis Dalessandro u8 port_phys_conf; /* 4 res, 4 bits */ 316*d4ab3470SDennis Dalessandro u8 collectivemask_multicastmask; /* 2 res, 3, 3 */ 317*d4ab3470SDennis Dalessandro u8 mkeyprotect_lmc; /* 2 bits, 2 res, 4 bits */ 318*d4ab3470SDennis Dalessandro u8 smsl; /* 3 res, 5 bits */ 319*d4ab3470SDennis Dalessandro 320*d4ab3470SDennis Dalessandro u8 partenforce_filterraw; /* bit fields */ 321*d4ab3470SDennis Dalessandro u8 operational_vls; /* 3 res, 5 bits */ 322*d4ab3470SDennis Dalessandro __be16 pkey_8b; 323*d4ab3470SDennis Dalessandro __be16 pkey_10b; 324*d4ab3470SDennis Dalessandro __be16 mkey_violations; 325*d4ab3470SDennis Dalessandro 326*d4ab3470SDennis Dalessandro __be16 pkey_violations; 327*d4ab3470SDennis Dalessandro __be16 qkey_violations; 328*d4ab3470SDennis Dalessandro __be32 sm_trap_qp; /* 8 bits, 24 bits */ 329*d4ab3470SDennis Dalessandro 330*d4ab3470SDennis Dalessandro __be32 sa_qp; /* 8 bits, 24 bits */ 331*d4ab3470SDennis Dalessandro u8 neigh_port_num; 332*d4ab3470SDennis Dalessandro u8 link_down_reason; 333*d4ab3470SDennis Dalessandro u8 neigh_link_down_reason; 334*d4ab3470SDennis Dalessandro u8 clientrereg_subnettimeout; /* 1 bit, 2 bits, 5 */ 335*d4ab3470SDennis Dalessandro 336*d4ab3470SDennis Dalessandro struct { 337*d4ab3470SDennis Dalessandro __be16 supported; 338*d4ab3470SDennis Dalessandro __be16 enabled; 339*d4ab3470SDennis Dalessandro __be16 active; 340*d4ab3470SDennis Dalessandro } link_speed; 341*d4ab3470SDennis Dalessandro struct { 342*d4ab3470SDennis Dalessandro __be16 supported; 343*d4ab3470SDennis Dalessandro __be16 enabled; 344*d4ab3470SDennis Dalessandro __be16 active; 345*d4ab3470SDennis Dalessandro } link_width; 346*d4ab3470SDennis Dalessandro struct { 347*d4ab3470SDennis Dalessandro __be16 supported; 348*d4ab3470SDennis Dalessandro __be16 enabled; 349*d4ab3470SDennis Dalessandro __be16 tx_active; 350*d4ab3470SDennis Dalessandro __be16 rx_active; 351*d4ab3470SDennis Dalessandro } link_width_downgrade; 352*d4ab3470SDennis Dalessandro __be16 port_link_mode; /* 1 res, 5 bits, 5 bits, 5 bits */ 353*d4ab3470SDennis Dalessandro __be16 port_ltp_crc_mode; /* 4 res, 4 bits, 4 bits, 4 bits */ 354*d4ab3470SDennis Dalessandro 355*d4ab3470SDennis Dalessandro __be16 port_mode; /* 9 res, bit fields */ 356*d4ab3470SDennis Dalessandro struct { 357*d4ab3470SDennis Dalessandro __be16 supported; 358*d4ab3470SDennis Dalessandro __be16 enabled; 359*d4ab3470SDennis Dalessandro } port_packet_format; 360*d4ab3470SDennis Dalessandro struct { 361*d4ab3470SDennis Dalessandro __be16 interleave; /* 2 res, 2,2,5,5 */ 362*d4ab3470SDennis Dalessandro struct { 363*d4ab3470SDennis Dalessandro __be16 min_initial; 364*d4ab3470SDennis Dalessandro __be16 min_tail; 365*d4ab3470SDennis Dalessandro u8 large_pkt_limit; 366*d4ab3470SDennis Dalessandro u8 small_pkt_limit; 367*d4ab3470SDennis Dalessandro u8 max_small_pkt_limit; 368*d4ab3470SDennis Dalessandro u8 preemption_limit; 369*d4ab3470SDennis Dalessandro } preemption; 370*d4ab3470SDennis Dalessandro } flit_control; 371*d4ab3470SDennis Dalessandro 372*d4ab3470SDennis Dalessandro __be32 reserved4; 373*d4ab3470SDennis Dalessandro __be32 port_error_action; /* bit field */ 374*d4ab3470SDennis Dalessandro 375*d4ab3470SDennis Dalessandro struct { 376*d4ab3470SDennis Dalessandro u8 egress_port; 377*d4ab3470SDennis Dalessandro u8 res_drctl; /* 7 res, 1 */ 378*d4ab3470SDennis Dalessandro } pass_through; 379*d4ab3470SDennis Dalessandro __be16 mkey_lease_period; 380*d4ab3470SDennis Dalessandro __be32 buffer_units; /* 9 res, 12, 5, 3, 3 */ 381*d4ab3470SDennis Dalessandro 382*d4ab3470SDennis Dalessandro __be32 reserved5; 383*d4ab3470SDennis Dalessandro __be32 sm_lid; 384*d4ab3470SDennis Dalessandro 385*d4ab3470SDennis Dalessandro __be64 mkey; 386*d4ab3470SDennis Dalessandro 387*d4ab3470SDennis Dalessandro __be64 subnet_prefix; 388*d4ab3470SDennis Dalessandro 389*d4ab3470SDennis Dalessandro struct { 390*d4ab3470SDennis Dalessandro u8 pvlx_to_mtu[OPA_MAX_VLS/2]; /* 4 bits, 4 bits */ 391*d4ab3470SDennis Dalessandro } neigh_mtu; 392*d4ab3470SDennis Dalessandro 393*d4ab3470SDennis Dalessandro struct { 394*d4ab3470SDennis Dalessandro u8 vlstall_hoqlife; /* 3 bits, 5 bits */ 395*d4ab3470SDennis Dalessandro } xmit_q[OPA_MAX_VLS]; 396*d4ab3470SDennis Dalessandro 397*d4ab3470SDennis Dalessandro struct { 398*d4ab3470SDennis Dalessandro u8 addr[16]; 399*d4ab3470SDennis Dalessandro } ipaddr_ipv6; 400*d4ab3470SDennis Dalessandro 401*d4ab3470SDennis Dalessandro struct { 402*d4ab3470SDennis Dalessandro u8 addr[4]; 403*d4ab3470SDennis Dalessandro } ipaddr_ipv4; 404*d4ab3470SDennis Dalessandro 405*d4ab3470SDennis Dalessandro u32 reserved6; 406*d4ab3470SDennis Dalessandro u32 reserved7; 407*d4ab3470SDennis Dalessandro u32 reserved8; 408*d4ab3470SDennis Dalessandro 409*d4ab3470SDennis Dalessandro __be64 neigh_node_guid; 410*d4ab3470SDennis Dalessandro 411*d4ab3470SDennis Dalessandro __be32 ib_cap_mask; 412*d4ab3470SDennis Dalessandro __be16 reserved9; /* was ib_cap_mask2 */ 413*d4ab3470SDennis Dalessandro __be16 opa_cap_mask; 414*d4ab3470SDennis Dalessandro 415*d4ab3470SDennis Dalessandro __be32 reserved10; /* was link_roundtrip_latency */ 416*d4ab3470SDennis Dalessandro __be16 overall_buffer_space; 417*d4ab3470SDennis Dalessandro __be16 reserved11; /* was max_credit_hint */ 418*d4ab3470SDennis Dalessandro 419*d4ab3470SDennis Dalessandro __be16 diag_code; 420*d4ab3470SDennis Dalessandro struct { 421*d4ab3470SDennis Dalessandro u8 buffer; 422*d4ab3470SDennis Dalessandro u8 wire; 423*d4ab3470SDennis Dalessandro } replay_depth; 424*d4ab3470SDennis Dalessandro u8 port_neigh_mode; 425*d4ab3470SDennis Dalessandro u8 mtucap; /* 4 res, 4 bits */ 426*d4ab3470SDennis Dalessandro 427*d4ab3470SDennis Dalessandro u8 resptimevalue; /* 3 res, 5 bits */ 428*d4ab3470SDennis Dalessandro u8 local_port_num; 429*d4ab3470SDennis Dalessandro u8 reserved12; 430*d4ab3470SDennis Dalessandro u8 reserved13; /* was guid_cap */ 431*d4ab3470SDennis Dalessandro } __attribute__ ((packed)); 432*d4ab3470SDennis Dalessandro 433*d4ab3470SDennis Dalessandro #endif /* OPA_PORT_INFO_H */ 434