1742a3826SKaike Wan /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */ 2742a3826SKaike Wan /* 3742a3826SKaike Wan * Copyright(c) 2018 Intel Corporation. 4742a3826SKaike Wan * 5742a3826SKaike Wan */ 6742a3826SKaike Wan 7742a3826SKaike Wan #ifndef TID_RDMA_DEFS_H 8742a3826SKaike Wan #define TID_RDMA_DEFS_H 9742a3826SKaike Wan 10742a3826SKaike Wan #include <rdma/ib_pack.h> 11742a3826SKaike Wan 12742a3826SKaike Wan struct tid_rdma_read_req { 13742a3826SKaike Wan __le32 kdeth0; 14742a3826SKaike Wan __le32 kdeth1; 15742a3826SKaike Wan struct ib_reth reth; 16742a3826SKaike Wan __be32 tid_flow_psn; 17742a3826SKaike Wan __be32 tid_flow_qp; 18742a3826SKaike Wan __be32 verbs_qp; 19742a3826SKaike Wan }; 20742a3826SKaike Wan 21742a3826SKaike Wan struct tid_rdma_read_resp { 22742a3826SKaike Wan __le32 kdeth0; 23742a3826SKaike Wan __le32 kdeth1; 24742a3826SKaike Wan __be32 aeth; 25742a3826SKaike Wan __be32 reserved[4]; 26742a3826SKaike Wan __be32 verbs_psn; 27742a3826SKaike Wan __be32 verbs_qp; 28742a3826SKaike Wan }; 29742a3826SKaike Wan 30*c098bbb0SKaike Wan struct tid_rdma_write_req { 31*c098bbb0SKaike Wan __le32 kdeth0; 32*c098bbb0SKaike Wan __le32 kdeth1; 33*c098bbb0SKaike Wan struct ib_reth reth; 34*c098bbb0SKaike Wan __be32 reserved[2]; 35*c098bbb0SKaike Wan __be32 verbs_qp; 36*c098bbb0SKaike Wan }; 37*c098bbb0SKaike Wan 38*c098bbb0SKaike Wan struct tid_rdma_write_resp { 39*c098bbb0SKaike Wan __le32 kdeth0; 40*c098bbb0SKaike Wan __le32 kdeth1; 41*c098bbb0SKaike Wan __be32 aeth; 42*c098bbb0SKaike Wan __be32 reserved[3]; 43*c098bbb0SKaike Wan __be32 tid_flow_psn; 44*c098bbb0SKaike Wan __be32 tid_flow_qp; 45*c098bbb0SKaike Wan __be32 verbs_qp; 46*c098bbb0SKaike Wan }; 47*c098bbb0SKaike Wan 48*c098bbb0SKaike Wan struct tid_rdma_write_data { 49*c098bbb0SKaike Wan __le32 kdeth0; 50*c098bbb0SKaike Wan __le32 kdeth1; 51*c098bbb0SKaike Wan __be32 reserved[6]; 52*c098bbb0SKaike Wan __be32 verbs_qp; 53*c098bbb0SKaike Wan }; 54*c098bbb0SKaike Wan 55*c098bbb0SKaike Wan struct tid_rdma_resync { 56*c098bbb0SKaike Wan __le32 kdeth0; 57*c098bbb0SKaike Wan __le32 kdeth1; 58*c098bbb0SKaike Wan __be32 reserved[6]; 59*c098bbb0SKaike Wan __be32 verbs_qp; 60*c098bbb0SKaike Wan }; 61*c098bbb0SKaike Wan 62*c098bbb0SKaike Wan struct tid_rdma_ack { 63*c098bbb0SKaike Wan __le32 kdeth0; 64*c098bbb0SKaike Wan __le32 kdeth1; 65*c098bbb0SKaike Wan __be32 aeth; 66*c098bbb0SKaike Wan __be32 reserved[2]; 67*c098bbb0SKaike Wan __be32 tid_flow_psn; 68*c098bbb0SKaike Wan __be32 verbs_psn; 69*c098bbb0SKaike Wan __be32 tid_flow_qp; 70*c098bbb0SKaike Wan __be32 verbs_qp; 71*c098bbb0SKaike Wan }; 72*c098bbb0SKaike Wan 73742a3826SKaike Wan /* 74742a3826SKaike Wan * TID RDMA Opcodes 75742a3826SKaike Wan */ 76742a3826SKaike Wan #define IB_OPCODE_TID_RDMA 0xe0 77742a3826SKaike Wan enum { 78*c098bbb0SKaike Wan IB_OPCODE_WRITE_REQ = 0x0, 79*c098bbb0SKaike Wan IB_OPCODE_WRITE_RESP = 0x1, 80*c098bbb0SKaike Wan IB_OPCODE_WRITE_DATA = 0x2, 81*c098bbb0SKaike Wan IB_OPCODE_WRITE_DATA_LAST = 0x3, 82742a3826SKaike Wan IB_OPCODE_READ_REQ = 0x4, 83742a3826SKaike Wan IB_OPCODE_READ_RESP = 0x5, 84*c098bbb0SKaike Wan IB_OPCODE_RESYNC = 0x6, 85*c098bbb0SKaike Wan IB_OPCODE_ACK = 0x7, 86742a3826SKaike Wan 87*c098bbb0SKaike Wan IB_OPCODE(TID_RDMA, WRITE_REQ), 88*c098bbb0SKaike Wan IB_OPCODE(TID_RDMA, WRITE_RESP), 89*c098bbb0SKaike Wan IB_OPCODE(TID_RDMA, WRITE_DATA), 90*c098bbb0SKaike Wan IB_OPCODE(TID_RDMA, WRITE_DATA_LAST), 91742a3826SKaike Wan IB_OPCODE(TID_RDMA, READ_REQ), 92742a3826SKaike Wan IB_OPCODE(TID_RDMA, READ_RESP), 93*c098bbb0SKaike Wan IB_OPCODE(TID_RDMA, RESYNC), 94*c098bbb0SKaike Wan IB_OPCODE(TID_RDMA, ACK), 95742a3826SKaike Wan }; 96742a3826SKaike Wan 97742a3826SKaike Wan #define TID_OP(x) IB_OPCODE_TID_RDMA_##x 98742a3826SKaike Wan 99742a3826SKaike Wan /* 100742a3826SKaike Wan * Define TID RDMA specific WR opcodes. The ib_wr_opcode 101742a3826SKaike Wan * enum already provides some reserved values for use by 102742a3826SKaike Wan * low level drivers. Two of those are used but renamed 103742a3826SKaike Wan * to be more descriptive. 104742a3826SKaike Wan */ 105*c098bbb0SKaike Wan #define IB_WR_TID_RDMA_WRITE IB_WR_RESERVED1 106742a3826SKaike Wan #define IB_WR_TID_RDMA_READ IB_WR_RESERVED2 107742a3826SKaike Wan 108742a3826SKaike Wan #endif /* TID_RDMA_DEFS_H */ 109