xref: /linux/include/sound/cs35l41.h (revision 0be3ff0c)
1 /* SPDX-License-Identifier: GPL-2.0
2  *
3  * linux/sound/cs35l41.h -- Platform data for CS35L41
4  *
5  * Copyright (c) 2017-2021 Cirrus Logic Inc.
6  *
7  * Author: David Rhodes	<david.rhodes@cirrus.com>
8  */
9 
10 #ifndef __CS35L41_H
11 #define __CS35L41_H
12 
13 #include <linux/regmap.h>
14 
15 #define CS35L41_FIRSTREG		0x00000000
16 #define CS35L41_LASTREG			0x03804FE8
17 #define CS35L41_DEVID			0x00000000
18 #define CS35L41_REVID			0x00000004
19 #define CS35L41_FABID			0x00000008
20 #define CS35L41_RELID			0x0000000C
21 #define CS35L41_OTPID			0x00000010
22 #define CS35L41_SFT_RESET		0x00000020
23 #define CS35L41_TEST_KEY_CTL		0x00000040
24 #define CS35L41_USER_KEY_CTL		0x00000044
25 #define CS35L41_OTP_MEM0		0x00000400
26 #define CS35L41_OTP_MEM31		0x0000047C
27 #define CS35L41_OTP_CTRL0		0x00000500
28 #define CS35L41_OTP_CTRL1		0x00000504
29 #define CS35L41_OTP_CTRL3		0x00000508
30 #define CS35L41_OTP_CTRL4		0x0000050C
31 #define CS35L41_OTP_CTRL5		0x00000510
32 #define CS35L41_OTP_CTRL6		0x00000514
33 #define CS35L41_OTP_CTRL7		0x00000518
34 #define CS35L41_OTP_CTRL8		0x0000051C
35 #define CS35L41_PWR_CTRL1		0x00002014
36 #define CS35L41_PWR_CTRL2		0x00002018
37 #define CS35L41_PWR_CTRL3		0x0000201C
38 #define CS35L41_CTRL_OVRRIDE		0x00002020
39 #define CS35L41_AMP_OUT_MUTE		0x00002024
40 #define CS35L41_PROTECT_REL_ERR_IGN	0x00002034
41 #define CS35L41_GPIO_PAD_CONTROL	0x0000242C
42 #define CS35L41_JTAG_CONTROL		0x00002438
43 #define CS35L41_PWRMGT_CTL		0x00002900
44 #define CS35L41_WAKESRC_CTL		0x00002904
45 #define CS35L41_PWRMGT_STS		0x00002908
46 #define CS35L41_PLL_CLK_CTRL		0x00002C04
47 #define CS35L41_DSP_CLK_CTRL		0x00002C08
48 #define CS35L41_GLOBAL_CLK_CTRL		0x00002C0C
49 #define CS35L41_DATA_FS_SEL		0x00002C10
50 #define CS35L41_TST_FS_MON0		0x00002D10
51 #define CS35L41_MDSYNC_EN		0x00003400
52 #define CS35L41_MDSYNC_TX_ID		0x00003408
53 #define CS35L41_MDSYNC_PWR_CTRL		0x0000340C
54 #define CS35L41_MDSYNC_DATA_TX		0x00003410
55 #define CS35L41_MDSYNC_TX_STATUS	0x00003414
56 #define CS35L41_MDSYNC_DATA_RX		0x0000341C
57 #define CS35L41_MDSYNC_RX_STATUS	0x00003420
58 #define CS35L41_MDSYNC_ERR_STATUS	0x00003424
59 #define CS35L41_MDSYNC_SYNC_PTE2	0x00003528
60 #define CS35L41_MDSYNC_SYNC_PTE3	0x0000352C
61 #define CS35L41_MDSYNC_SYNC_MSM_STATUS	0x0000353C
62 #define CS35L41_BSTCVRT_VCTRL1		0x00003800
63 #define CS35L41_BSTCVRT_VCTRL2		0x00003804
64 #define CS35L41_BSTCVRT_PEAK_CUR	0x00003808
65 #define CS35L41_BSTCVRT_SFT_RAMP	0x0000380C
66 #define CS35L41_BSTCVRT_COEFF		0x00003810
67 #define CS35L41_BSTCVRT_SLOPE_LBST	0x00003814
68 #define CS35L41_BSTCVRT_SW_FREQ		0x00003818
69 #define CS35L41_BSTCVRT_DCM_CTRL	0x0000381C
70 #define CS35L41_BSTCVRT_DCM_MODE_FORCE	0x00003820
71 #define CS35L41_BSTCVRT_OVERVOLT_CTRL	0x00003830
72 #define CS35L41_VI_VOL_POL		0x00004000
73 #define CS35L41_VIMON_SPKMON_RESYNC	0x00004100
74 #define CS35L41_DTEMP_WARN_THLD		0x00004220
75 #define CS35L41_DTEMP_CFG		0x00004224
76 #define CS35L41_DTEMP_EN		0x00004308
77 #define CS35L41_VPVBST_FS_SEL		0x00004400
78 #define CS35L41_SP_ENABLES		0x00004800
79 #define CS35L41_SP_RATE_CTRL		0x00004804
80 #define CS35L41_SP_FORMAT		0x00004808
81 #define CS35L41_SP_HIZ_CTRL		0x0000480C
82 #define CS35L41_SP_FRAME_TX_SLOT	0x00004810
83 #define CS35L41_SP_FRAME_RX_SLOT	0x00004820
84 #define CS35L41_SP_TX_WL		0x00004830
85 #define CS35L41_SP_RX_WL		0x00004840
86 #define CS35L41_ASP_CONTROL4		0x00004854
87 #define CS35L41_DAC_PCM1_SRC		0x00004C00
88 #define CS35L41_ASP_TX1_SRC		0x00004C20
89 #define CS35L41_ASP_TX2_SRC		0x00004C24
90 #define CS35L41_ASP_TX3_SRC		0x00004C28
91 #define CS35L41_ASP_TX4_SRC		0x00004C2C
92 #define CS35L41_DSP1_RX1_SRC		0x00004C40
93 #define CS35L41_DSP1_RX2_SRC		0x00004C44
94 #define CS35L41_DSP1_RX3_SRC		0x00004C48
95 #define CS35L41_DSP1_RX4_SRC		0x00004C4C
96 #define CS35L41_DSP1_RX5_SRC		0x00004C50
97 #define CS35L41_DSP1_RX6_SRC		0x00004C54
98 #define CS35L41_DSP1_RX7_SRC		0x00004C58
99 #define CS35L41_DSP1_RX8_SRC		0x00004C5C
100 #define CS35L41_NGATE1_SRC		0x00004C60
101 #define CS35L41_NGATE2_SRC		0x00004C64
102 #define CS35L41_AMP_DIG_VOL_CTRL	0x00006000
103 #define CS35L41_VPBR_CFG		0x00006404
104 #define CS35L41_VBBR_CFG		0x00006408
105 #define CS35L41_VPBR_STATUS		0x0000640C
106 #define CS35L41_VBBR_STATUS		0x00006410
107 #define CS35L41_OVERTEMP_CFG		0x00006414
108 #define CS35L41_AMP_ERR_VOL		0x00006418
109 #define CS35L41_VOL_STATUS_TO_DSP	0x00006450
110 #define CS35L41_CLASSH_CFG		0x00006800
111 #define CS35L41_WKFET_CFG		0x00006804
112 #define CS35L41_NG_CFG			0x00006808
113 #define CS35L41_AMP_GAIN_CTRL		0x00006C04
114 #define CS35L41_DAC_MSM_CFG		0x00007400
115 #define CS35L41_IRQ1_CFG		0x00010000
116 #define CS35L41_IRQ1_STATUS		0x00010004
117 #define CS35L41_IRQ1_STATUS1		0x00010010
118 #define CS35L41_IRQ1_STATUS2		0x00010014
119 #define CS35L41_IRQ1_STATUS3		0x00010018
120 #define CS35L41_IRQ1_STATUS4		0x0001001C
121 #define CS35L41_IRQ1_RAW_STATUS1	0x00010090
122 #define CS35L41_IRQ1_RAW_STATUS2	0x00010094
123 #define CS35L41_IRQ1_RAW_STATUS3	0x00010098
124 #define CS35L41_IRQ1_RAW_STATUS4	0x0001009C
125 #define CS35L41_IRQ1_MASK1		0x00010110
126 #define CS35L41_IRQ1_MASK2		0x00010114
127 #define CS35L41_IRQ1_MASK3		0x00010118
128 #define CS35L41_IRQ1_MASK4		0x0001011C
129 #define CS35L41_IRQ1_FRC1		0x00010190
130 #define CS35L41_IRQ1_FRC2		0x00010194
131 #define CS35L41_IRQ1_FRC3		0x00010198
132 #define CS35L41_IRQ1_FRC4		0x0001019C
133 #define CS35L41_IRQ1_EDGE1		0x00010210
134 #define CS35L41_IRQ1_EDGE4		0x0001021C
135 #define CS35L41_IRQ1_POL1		0x00010290
136 #define CS35L41_IRQ1_POL2		0x00010294
137 #define CS35L41_IRQ1_POL3		0x00010298
138 #define CS35L41_IRQ1_POL4		0x0001029C
139 #define CS35L41_IRQ1_DB3		0x00010318
140 #define CS35L41_IRQ2_CFG		0x00010800
141 #define CS35L41_IRQ2_STATUS		0x00010804
142 #define CS35L41_IRQ2_STATUS1		0x00010810
143 #define CS35L41_IRQ2_STATUS2		0x00010814
144 #define CS35L41_IRQ2_STATUS3		0x00010818
145 #define CS35L41_IRQ2_STATUS4		0x0001081C
146 #define CS35L41_IRQ2_RAW_STATUS1	0x00010890
147 #define CS35L41_IRQ2_RAW_STATUS2	0x00010894
148 #define CS35L41_IRQ2_RAW_STATUS3	0x00010898
149 #define CS35L41_IRQ2_RAW_STATUS4	0x0001089C
150 #define CS35L41_IRQ2_MASK1		0x00010910
151 #define CS35L41_IRQ2_MASK2		0x00010914
152 #define CS35L41_IRQ2_MASK3		0x00010918
153 #define CS35L41_IRQ2_MASK4		0x0001091C
154 #define CS35L41_IRQ2_FRC1		0x00010990
155 #define CS35L41_IRQ2_FRC2		0x00010994
156 #define CS35L41_IRQ2_FRC3		0x00010998
157 #define CS35L41_IRQ2_FRC4		0x0001099C
158 #define CS35L41_IRQ2_EDGE1		0x00010A10
159 #define CS35L41_IRQ2_EDGE4		0x00010A1C
160 #define CS35L41_IRQ2_POL1		0x00010A90
161 #define CS35L41_IRQ2_POL2		0x00010A94
162 #define CS35L41_IRQ2_POL3		0x00010A98
163 #define CS35L41_IRQ2_POL4		0x00010A9C
164 #define CS35L41_IRQ2_DB3		0x00010B18
165 #define CS35L41_GPIO_STATUS1		0x00011000
166 #define CS35L41_GPIO1_CTRL1		0x00011008
167 #define CS35L41_GPIO2_CTRL1		0x0001100C
168 #define CS35L41_MIXER_NGATE_CFG		0x00012000
169 #define CS35L41_MIXER_NGATE_CH1_CFG	0x00012004
170 #define CS35L41_MIXER_NGATE_CH2_CFG	0x00012008
171 #define CS35L41_DSP_MBOX_1		0x00013000
172 #define CS35L41_DSP_MBOX_2		0x00013004
173 #define CS35L41_DSP_MBOX_3		0x00013008
174 #define CS35L41_DSP_MBOX_4		0x0001300C
175 #define CS35L41_DSP_MBOX_5		0x00013010
176 #define CS35L41_DSP_MBOX_6		0x00013014
177 #define CS35L41_DSP_MBOX_7		0x00013018
178 #define CS35L41_DSP_MBOX_8		0x0001301C
179 #define CS35L41_DSP_VIRT1_MBOX_1	0x00013020
180 #define CS35L41_DSP_VIRT1_MBOX_2	0x00013024
181 #define CS35L41_DSP_VIRT1_MBOX_3	0x00013028
182 #define CS35L41_DSP_VIRT1_MBOX_4	0x0001302C
183 #define CS35L41_DSP_VIRT1_MBOX_5	0x00013030
184 #define CS35L41_DSP_VIRT1_MBOX_6	0x00013034
185 #define CS35L41_DSP_VIRT1_MBOX_7	0x00013038
186 #define CS35L41_DSP_VIRT1_MBOX_8	0x0001303C
187 #define CS35L41_DSP_VIRT2_MBOX_1	0x00013040
188 #define CS35L41_DSP_VIRT2_MBOX_2	0x00013044
189 #define CS35L41_DSP_VIRT2_MBOX_3	0x00013048
190 #define CS35L41_DSP_VIRT2_MBOX_4	0x0001304C
191 #define CS35L41_DSP_VIRT2_MBOX_5	0x00013050
192 #define CS35L41_DSP_VIRT2_MBOX_6	0x00013054
193 #define CS35L41_DSP_VIRT2_MBOX_7	0x00013058
194 #define CS35L41_DSP_VIRT2_MBOX_8	0x0001305C
195 #define CS35L41_CLOCK_DETECT_1		0x00014000
196 #define CS35L41_TIMER1_CONTROL		0x00015000
197 #define CS35L41_TIMER1_COUNT_PRESET	0x00015004
198 #define CS35L41_TIMER1_START_STOP	0x0001500C
199 #define CS35L41_TIMER1_STATUS		0x00015010
200 #define CS35L41_TIMER1_COUNT_READBACK	0x00015014
201 #define CS35L41_TIMER1_DSP_CLK_CFG	0x00015018
202 #define CS35L41_TIMER1_DSP_CLK_STATUS	0x0001501C
203 #define CS35L41_TIMER2_CONTROL		0x00015100
204 #define CS35L41_TIMER2_COUNT_PRESET	0x00015104
205 #define CS35L41_TIMER2_START_STOP	0x0001510C
206 #define CS35L41_TIMER2_STATUS		0x00015110
207 #define CS35L41_TIMER2_COUNT_READBACK	0x00015114
208 #define CS35L41_TIMER2_DSP_CLK_CFG	0x00015118
209 #define CS35L41_TIMER2_DSP_CLK_STATUS	0x0001511C
210 #define CS35L41_DFT_JTAG_CONTROL	0x00016000
211 #define CS35L41_DIE_STS1		0x00017040
212 #define CS35L41_DIE_STS2		0x00017044
213 #define CS35L41_TEMP_CAL1		0x00017048
214 #define CS35L41_TEMP_CAL2		0x0001704C
215 #define CS35L41_DSP1_XMEM_PACK_0	0x02000000
216 #define CS35L41_DSP1_XMEM_PACK_3068	0x02002FF0
217 #define CS35L41_DSP1_XMEM_UNPACK32_0	0x02400000
218 #define CS35L41_DSP1_XMEM_UNPACK32_2046	0x02401FF8
219 #define CS35L41_DSP1_TIMESTAMP_COUNT	0x025C0800
220 #define CS35L41_DSP1_SYS_ID		0x025E0000
221 #define CS35L41_DSP1_SYS_VERSION	0x025E0004
222 #define CS35L41_DSP1_SYS_CORE_ID	0x025E0008
223 #define CS35L41_DSP1_SYS_AHB_ADDR	0x025E000C
224 #define CS35L41_DSP1_SYS_XSRAM_SIZE	0x025E0010
225 #define CS35L41_DSP1_SYS_YSRAM_SIZE	0x025E0018
226 #define CS35L41_DSP1_SYS_PSRAM_SIZE	0x025E0020
227 #define CS35L41_DSP1_SYS_PM_BOOT_SIZE	0x025E0028
228 #define CS35L41_DSP1_SYS_FEATURES	0x025E002C
229 #define CS35L41_DSP1_SYS_FIR_FILTERS	0x025E0030
230 #define CS35L41_DSP1_SYS_LMS_FILTERS	0x025E0034
231 #define CS35L41_DSP1_SYS_XM_BANK_SIZE	0x025E0038
232 #define CS35L41_DSP1_SYS_YM_BANK_SIZE	0x025E003C
233 #define CS35L41_DSP1_SYS_PM_BANK_SIZE	0x025E0040
234 #define CS35L41_DSP1_AHBM_WIN0_CTRL0	0x025E2000
235 #define CS35L41_DSP1_AHBM_WIN0_CTRL1	0x025E2004
236 #define CS35L41_DSP1_AHBM_WIN1_CTRL0	0x025E2008
237 #define CS35L41_DSP1_AHBM_WIN1_CTRL1	0x025E200C
238 #define CS35L41_DSP1_AHBM_WIN2_CTRL0	0x025E2010
239 #define CS35L41_DSP1_AHBM_WIN2_CTRL1	0x025E2014
240 #define CS35L41_DSP1_AHBM_WIN3_CTRL0	0x025E2018
241 #define CS35L41_DSP1_AHBM_WIN3_CTRL1	0x025E201C
242 #define CS35L41_DSP1_AHBM_WIN4_CTRL0	0x025E2020
243 #define CS35L41_DSP1_AHBM_WIN4_CTRL1	0x025E2024
244 #define CS35L41_DSP1_AHBM_WIN5_CTRL0	0x025E2028
245 #define CS35L41_DSP1_AHBM_WIN5_CTRL1	0x025E202C
246 #define CS35L41_DSP1_AHBM_WIN6_CTRL0	0x025E2030
247 #define CS35L41_DSP1_AHBM_WIN6_CTRL1	0x025E2034
248 #define CS35L41_DSP1_AHBM_WIN7_CTRL0	0x025E2038
249 #define CS35L41_DSP1_AHBM_WIN7_CTRL1	0x025E203C
250 #define CS35L41_DSP1_AHBM_WIN_DBG_CTRL0	0x025E2040
251 #define CS35L41_DSP1_AHBM_WIN_DBG_CTRL1	0x025E2044
252 #define CS35L41_DSP1_XMEM_UNPACK24_0	0x02800000
253 #define CS35L41_DSP1_XMEM_UNPACK24_4093	0x02803FF4
254 #define CS35L41_DSP1_CTRL_BASE		0x02B80000
255 #define CS35L41_DSP1_CORE_SOFT_RESET	0x02B80010
256 #define CS35L41_DSP1_DEBUG		0x02B80040
257 #define CS35L41_DSP1_TIMER_CTRL		0x02B80048
258 #define CS35L41_DSP1_STREAM_ARB_CTRL	0x02B80050
259 #define CS35L41_DSP1_RX1_RATE		0x02B80080
260 #define CS35L41_DSP1_RX2_RATE		0x02B80088
261 #define CS35L41_DSP1_RX3_RATE		0x02B80090
262 #define CS35L41_DSP1_RX4_RATE		0x02B80098
263 #define CS35L41_DSP1_RX5_RATE		0x02B800A0
264 #define CS35L41_DSP1_RX6_RATE		0x02B800A8
265 #define CS35L41_DSP1_RX7_RATE		0x02B800B0
266 #define CS35L41_DSP1_RX8_RATE		0x02B800B8
267 #define CS35L41_DSP1_TX1_RATE		0x02B80280
268 #define CS35L41_DSP1_TX2_RATE		0x02B80288
269 #define CS35L41_DSP1_TX3_RATE		0x02B80290
270 #define CS35L41_DSP1_TX4_RATE		0x02B80298
271 #define CS35L41_DSP1_TX5_RATE		0x02B802A0
272 #define CS35L41_DSP1_TX6_RATE		0x02B802A8
273 #define CS35L41_DSP1_TX7_RATE		0x02B802B0
274 #define CS35L41_DSP1_TX8_RATE		0x02B802B8
275 #define CS35L41_DSP1_NMI_CTRL1		0x02B80480
276 #define CS35L41_DSP1_NMI_CTRL2		0x02B80488
277 #define CS35L41_DSP1_NMI_CTRL3		0x02B80490
278 #define CS35L41_DSP1_NMI_CTRL4		0x02B80498
279 #define CS35L41_DSP1_NMI_CTRL5		0x02B804A0
280 #define CS35L41_DSP1_NMI_CTRL6		0x02B804A8
281 #define CS35L41_DSP1_NMI_CTRL7		0x02B804B0
282 #define CS35L41_DSP1_NMI_CTRL8		0x02B804B8
283 #define CS35L41_DSP1_RESUME_CTRL	0x02B80500
284 #define CS35L41_DSP1_IRQ1_CTRL		0x02B80508
285 #define CS35L41_DSP1_IRQ2_CTRL		0x02B80510
286 #define CS35L41_DSP1_IRQ3_CTRL		0x02B80518
287 #define CS35L41_DSP1_IRQ4_CTRL		0x02B80520
288 #define CS35L41_DSP1_IRQ5_CTRL		0x02B80528
289 #define CS35L41_DSP1_IRQ6_CTRL		0x02B80530
290 #define CS35L41_DSP1_IRQ7_CTRL		0x02B80538
291 #define CS35L41_DSP1_IRQ8_CTRL		0x02B80540
292 #define CS35L41_DSP1_IRQ9_CTRL		0x02B80548
293 #define CS35L41_DSP1_IRQ10_CTRL		0x02B80550
294 #define CS35L41_DSP1_IRQ11_CTRL		0x02B80558
295 #define CS35L41_DSP1_IRQ12_CTRL		0x02B80560
296 #define CS35L41_DSP1_IRQ13_CTRL		0x02B80568
297 #define CS35L41_DSP1_IRQ14_CTRL		0x02B80570
298 #define CS35L41_DSP1_IRQ15_CTRL		0x02B80578
299 #define CS35L41_DSP1_IRQ16_CTRL		0x02B80580
300 #define CS35L41_DSP1_IRQ17_CTRL		0x02B80588
301 #define CS35L41_DSP1_IRQ18_CTRL		0x02B80590
302 #define CS35L41_DSP1_IRQ19_CTRL		0x02B80598
303 #define CS35L41_DSP1_IRQ20_CTRL		0x02B805A0
304 #define CS35L41_DSP1_IRQ21_CTRL		0x02B805A8
305 #define CS35L41_DSP1_IRQ22_CTRL		0x02B805B0
306 #define CS35L41_DSP1_IRQ23_CTRL		0x02B805B8
307 #define CS35L41_DSP1_SCRATCH1		0x02B805C0
308 #define CS35L41_DSP1_SCRATCH2		0x02B805C8
309 #define CS35L41_DSP1_SCRATCH3		0x02B805D0
310 #define CS35L41_DSP1_SCRATCH4		0x02B805D8
311 #define CS35L41_DSP1_CCM_CORE_CTRL	0x02BC1000
312 #define CS35L41_DSP1_CCM_CLK_OVERRIDE	0x02BC1008
313 #define CS35L41_DSP1_XM_MSTR_EN		0x02BC2000
314 #define CS35L41_DSP1_XM_CORE_PRI	0x02BC2008
315 #define CS35L41_DSP1_XM_AHB_PACK_PL_PRI	0x02BC2010
316 #define CS35L41_DSP1_XM_AHB_UP_PL_PRI	0x02BC2018
317 #define CS35L41_DSP1_XM_ACCEL_PL0_PRI	0x02BC2020
318 #define CS35L41_DSP1_XM_NPL0_PRI	0x02BC2078
319 #define CS35L41_DSP1_YM_MSTR_EN		0x02BC20C0
320 #define CS35L41_DSP1_YM_CORE_PRI	0x02BC20C8
321 #define CS35L41_DSP1_YM_AHB_PACK_PL_PRI	0x02BC20D0
322 #define CS35L41_DSP1_YM_AHB_UP_PL_PRI	0x02BC20D8
323 #define CS35L41_DSP1_YM_ACCEL_PL0_PRI	0x02BC20E0
324 #define CS35L41_DSP1_YM_NPL0_PRI	0x02BC2138
325 #define CS35L41_DSP1_PM_MSTR_EN		0x02BC2180
326 #define CS35L41_DSP1_PM_PATCH0_ADDR	0x02BC2188
327 #define CS35L41_DSP1_PM_PATCH0_EN	0x02BC218C
328 #define CS35L41_DSP1_PM_PATCH0_DATA_LO	0x02BC2190
329 #define CS35L41_DSP1_PM_PATCH0_DATA_HI	0x02BC2194
330 #define CS35L41_DSP1_PM_PATCH1_ADDR	0x02BC2198
331 #define CS35L41_DSP1_PM_PATCH1_EN	0x02BC219C
332 #define CS35L41_DSP1_PM_PATCH1_DATA_LO	0x02BC21A0
333 #define CS35L41_DSP1_PM_PATCH1_DATA_HI	0x02BC21A4
334 #define CS35L41_DSP1_PM_PATCH2_ADDR	0x02BC21A8
335 #define CS35L41_DSP1_PM_PATCH2_EN	0x02BC21AC
336 #define CS35L41_DSP1_PM_PATCH2_DATA_LO	0x02BC21B0
337 #define CS35L41_DSP1_PM_PATCH2_DATA_HI	0x02BC21B4
338 #define CS35L41_DSP1_PM_PATCH3_ADDR	0x02BC21B8
339 #define CS35L41_DSP1_PM_PATCH3_EN	0x02BC21BC
340 #define CS35L41_DSP1_PM_PATCH3_DATA_LO	0x02BC21C0
341 #define CS35L41_DSP1_PM_PATCH3_DATA_HI	0x02BC21C4
342 #define CS35L41_DSP1_PM_PATCH4_ADDR	0x02BC21C8
343 #define CS35L41_DSP1_PM_PATCH4_EN	0x02BC21CC
344 #define CS35L41_DSP1_PM_PATCH4_DATA_LO	0x02BC21D0
345 #define CS35L41_DSP1_PM_PATCH4_DATA_HI	0x02BC21D4
346 #define CS35L41_DSP1_PM_PATCH5_ADDR	0x02BC21D8
347 #define CS35L41_DSP1_PM_PATCH5_EN	0x02BC21DC
348 #define CS35L41_DSP1_PM_PATCH5_DATA_LO	0x02BC21E0
349 #define CS35L41_DSP1_PM_PATCH5_DATA_HI	0x02BC21E4
350 #define CS35L41_DSP1_PM_PATCH6_ADDR	0x02BC21E8
351 #define CS35L41_DSP1_PM_PATCH6_EN	0x02BC21EC
352 #define CS35L41_DSP1_PM_PATCH6_DATA_LO	0x02BC21F0
353 #define CS35L41_DSP1_PM_PATCH6_DATA_HI	0x02BC21F4
354 #define CS35L41_DSP1_PM_PATCH7_ADDR	0x02BC21F8
355 #define CS35L41_DSP1_PM_PATCH7_EN	0x02BC21FC
356 #define CS35L41_DSP1_PM_PATCH7_DATA_LO	0x02BC2200
357 #define CS35L41_DSP1_PM_PATCH7_DATA_HI	0x02BC2204
358 #define CS35L41_DSP1_MPU_XM_ACCESS0	0x02BC3000
359 #define CS35L41_DSP1_MPU_YM_ACCESS0	0x02BC3004
360 #define CS35L41_DSP1_MPU_WNDW_ACCESS0	0x02BC3008
361 #define CS35L41_DSP1_MPU_XREG_ACCESS0	0x02BC300C
362 #define CS35L41_DSP1_MPU_YREG_ACCESS0	0x02BC3014
363 #define CS35L41_DSP1_MPU_XM_ACCESS1	0x02BC3018
364 #define CS35L41_DSP1_MPU_YM_ACCESS1	0x02BC301C
365 #define CS35L41_DSP1_MPU_WNDW_ACCESS1	0x02BC3020
366 #define CS35L41_DSP1_MPU_XREG_ACCESS1	0x02BC3024
367 #define CS35L41_DSP1_MPU_YREG_ACCESS1	0x02BC302C
368 #define CS35L41_DSP1_MPU_XM_ACCESS2	0x02BC3030
369 #define CS35L41_DSP1_MPU_YM_ACCESS2	0x02BC3034
370 #define CS35L41_DSP1_MPU_WNDW_ACCESS2	0x02BC3038
371 #define CS35L41_DSP1_MPU_XREG_ACCESS2	0x02BC303C
372 #define CS35L41_DSP1_MPU_YREG_ACCESS2	0x02BC3044
373 #define CS35L41_DSP1_MPU_XM_ACCESS3	0x02BC3048
374 #define CS35L41_DSP1_MPU_YM_ACCESS3	0x02BC304C
375 #define CS35L41_DSP1_MPU_WNDW_ACCESS3	0x02BC3050
376 #define CS35L41_DSP1_MPU_XREG_ACCESS3	0x02BC3054
377 #define CS35L41_DSP1_MPU_YREG_ACCESS3	0x02BC305C
378 #define CS35L41_DSP1_MPU_XM_VIO_ADDR	0x02BC3100
379 #define CS35L41_DSP1_MPU_XM_VIO_STATUS	0x02BC3104
380 #define CS35L41_DSP1_MPU_YM_VIO_ADDR	0x02BC3108
381 #define CS35L41_DSP1_MPU_YM_VIO_STATUS	0x02BC310C
382 #define CS35L41_DSP1_MPU_PM_VIO_ADDR	0x02BC3110
383 #define CS35L41_DSP1_MPU_PM_VIO_STATUS	0x02BC3114
384 #define CS35L41_DSP1_MPU_LOCK_CONFIG	0x02BC3140
385 #define CS35L41_DSP1_MPU_WDT_RST_CTRL	0x02BC3180
386 #define CS35L41_DSP1_STRMARB_MSTR0_CFG0	0x02BC5000
387 #define CS35L41_DSP1_STRMARB_MSTR0_CFG1	0x02BC5004
388 #define CS35L41_DSP1_STRMARB_MSTR0_CFG2	0x02BC5008
389 #define CS35L41_DSP1_STRMARB_MSTR1_CFG0	0x02BC5010
390 #define CS35L41_DSP1_STRMARB_MSTR1_CFG1	0x02BC5014
391 #define CS35L41_DSP1_STRMARB_MSTR1_CFG2	0x02BC5018
392 #define CS35L41_DSP1_STRMARB_MSTR2_CFG0	0x02BC5020
393 #define CS35L41_DSP1_STRMARB_MSTR2_CFG1	0x02BC5024
394 #define CS35L41_DSP1_STRMARB_MSTR2_CFG2	0x02BC5028
395 #define CS35L41_DSP1_STRMARB_MSTR3_CFG0	0x02BC5030
396 #define CS35L41_DSP1_STRMARB_MSTR3_CFG1	0x02BC5034
397 #define CS35L41_DSP1_STRMARB_MSTR3_CFG2	0x02BC5038
398 #define CS35L41_DSP1_STRMARB_MSTR4_CFG0	0x02BC5040
399 #define CS35L41_DSP1_STRMARB_MSTR4_CFG1	0x02BC5044
400 #define CS35L41_DSP1_STRMARB_MSTR4_CFG2	0x02BC5048
401 #define CS35L41_DSP1_STRMARB_MSTR5_CFG0	0x02BC5050
402 #define CS35L41_DSP1_STRMARB_MSTR5_CFG1	0x02BC5054
403 #define CS35L41_DSP1_STRMARB_MSTR5_CFG2	0x02BC5058
404 #define CS35L41_DSP1_STRMARB_MSTR6_CFG0	0x02BC5060
405 #define CS35L41_DSP1_STRMARB_MSTR6_CFG1	0x02BC5064
406 #define CS35L41_DSP1_STRMARB_MSTR6_CFG2	0x02BC5068
407 #define CS35L41_DSP1_STRMARB_MSTR7_CFG0	0x02BC5070
408 #define CS35L41_DSP1_STRMARB_MSTR7_CFG1	0x02BC5074
409 #define CS35L41_DSP1_STRMARB_MSTR7_CFG2	0x02BC5078
410 #define CS35L41_DSP1_STRMARB_TX0_CFG0	0x02BC5200
411 #define CS35L41_DSP1_STRMARB_TX0_CFG1	0x02BC5204
412 #define CS35L41_DSP1_STRMARB_TX1_CFG0	0x02BC5208
413 #define CS35L41_DSP1_STRMARB_TX1_CFG1	0x02BC520C
414 #define CS35L41_DSP1_STRMARB_TX2_CFG0	0x02BC5210
415 #define CS35L41_DSP1_STRMARB_TX2_CFG1	0x02BC5214
416 #define CS35L41_DSP1_STRMARB_TX3_CFG0	0x02BC5218
417 #define CS35L41_DSP1_STRMARB_TX3_CFG1	0x02BC521C
418 #define CS35L41_DSP1_STRMARB_TX4_CFG0	0x02BC5220
419 #define CS35L41_DSP1_STRMARB_TX4_CFG1	0x02BC5224
420 #define CS35L41_DSP1_STRMARB_TX5_CFG0	0x02BC5228
421 #define CS35L41_DSP1_STRMARB_TX5_CFG1	0x02BC522C
422 #define CS35L41_DSP1_STRMARB_TX6_CFG0	0x02BC5230
423 #define CS35L41_DSP1_STRMARB_TX6_CFG1	0x02BC5234
424 #define CS35L41_DSP1_STRMARB_TX7_CFG0	0x02BC5238
425 #define CS35L41_DSP1_STRMARB_TX7_CFG1	0x02BC523C
426 #define CS35L41_DSP1_STRMARB_RX0_CFG0	0x02BC5400
427 #define CS35L41_DSP1_STRMARB_RX0_CFG1	0x02BC5404
428 #define CS35L41_DSP1_STRMARB_RX1_CFG0	0x02BC5408
429 #define CS35L41_DSP1_STRMARB_RX1_CFG1	0x02BC540C
430 #define CS35L41_DSP1_STRMARB_RX2_CFG0	0x02BC5410
431 #define CS35L41_DSP1_STRMARB_RX2_CFG1	0x02BC5414
432 #define CS35L41_DSP1_STRMARB_RX3_CFG0	0x02BC5418
433 #define CS35L41_DSP1_STRMARB_RX3_CFG1	0x02BC541C
434 #define CS35L41_DSP1_STRMARB_RX4_CFG0	0x02BC5420
435 #define CS35L41_DSP1_STRMARB_RX4_CFG1	0x02BC5424
436 #define CS35L41_DSP1_STRMARB_RX5_CFG0	0x02BC5428
437 #define CS35L41_DSP1_STRMARB_RX5_CFG1	0x02BC542C
438 #define CS35L41_DSP1_STRMARB_RX6_CFG0	0x02BC5430
439 #define CS35L41_DSP1_STRMARB_RX6_CFG1	0x02BC5434
440 #define CS35L41_DSP1_STRMARB_RX7_CFG0	0x02BC5438
441 #define CS35L41_DSP1_STRMARB_RX7_CFG1	0x02BC543C
442 #define CS35L41_DSP1_STRMARB_IRQ0_CFG0	0x02BC5600
443 #define CS35L41_DSP1_STRMARB_IRQ0_CFG1	0x02BC5604
444 #define CS35L41_DSP1_STRMARB_IRQ0_CFG2	0x02BC5608
445 #define CS35L41_DSP1_STRMARB_IRQ1_CFG0	0x02BC5610
446 #define CS35L41_DSP1_STRMARB_IRQ1_CFG1	0x02BC5614
447 #define CS35L41_DSP1_STRMARB_IRQ1_CFG2	0x02BC5618
448 #define CS35L41_DSP1_STRMARB_IRQ2_CFG0	0x02BC5620
449 #define CS35L41_DSP1_STRMARB_IRQ2_CFG1	0x02BC5624
450 #define CS35L41_DSP1_STRMARB_IRQ2_CFG2	0x02BC5628
451 #define CS35L41_DSP1_STRMARB_IRQ3_CFG0	0x02BC5630
452 #define CS35L41_DSP1_STRMARB_IRQ3_CFG1	0x02BC5634
453 #define CS35L41_DSP1_STRMARB_IRQ3_CFG2	0x02BC5638
454 #define CS35L41_DSP1_STRMARB_IRQ4_CFG0	0x02BC5640
455 #define CS35L41_DSP1_STRMARB_IRQ4_CFG1	0x02BC5644
456 #define CS35L41_DSP1_STRMARB_IRQ4_CFG2	0x02BC5648
457 #define CS35L41_DSP1_STRMARB_IRQ5_CFG0	0x02BC5650
458 #define CS35L41_DSP1_STRMARB_IRQ5_CFG1	0x02BC5654
459 #define CS35L41_DSP1_STRMARB_IRQ5_CFG2	0x02BC5658
460 #define CS35L41_DSP1_STRMARB_IRQ6_CFG0	0x02BC5660
461 #define CS35L41_DSP1_STRMARB_IRQ6_CFG1	0x02BC5664
462 #define CS35L41_DSP1_STRMARB_IRQ6_CFG2	0x02BC5668
463 #define CS35L41_DSP1_STRMARB_IRQ7_CFG0	0x02BC5670
464 #define CS35L41_DSP1_STRMARB_IRQ7_CFG1	0x02BC5674
465 #define CS35L41_DSP1_STRMARB_IRQ7_CFG2	0x02BC5678
466 #define CS35L41_DSP1_STRMARB_RESYNC_MSK	0x02BC5A00
467 #define CS35L41_DSP1_STRMARB_ERR_STATUS	0x02BC5A08
468 #define CS35L41_DSP1_INTPCTL_RES_STATIC	0x02BC6000
469 #define CS35L41_DSP1_INTPCTL_RES_DYN	0x02BC6004
470 #define CS35L41_DSP1_INTPCTL_NMI_CTRL	0x02BC6008
471 #define CS35L41_DSP1_INTPCTL_IRQ_INV	0x02BC6010
472 #define CS35L41_DSP1_INTPCTL_IRQ_MODE	0x02BC6014
473 #define CS35L41_DSP1_INTPCTL_IRQ_EN	0x02BC6018
474 #define CS35L41_DSP1_INTPCTL_IRQ_MSK	0x02BC601C
475 #define CS35L41_DSP1_INTPCTL_IRQ_FLUSH	0x02BC6020
476 #define CS35L41_DSP1_INTPCTL_IRQ_MSKCLR	0x02BC6024
477 #define CS35L41_DSP1_INTPCTL_IRQ_FRC	0x02BC6028
478 #define CS35L41_DSP1_INTPCTL_IRQ_MSKSET	0x02BC602C
479 #define CS35L41_DSP1_INTPCTL_IRQ_ERR	0x02BC6030
480 #define CS35L41_DSP1_INTPCTL_IRQ_PEND	0x02BC6034
481 #define CS35L41_DSP1_INTPCTL_IRQ_GEN	0x02BC6038
482 #define CS35L41_DSP1_INTPCTL_TESTBITS	0x02BC6040
483 #define CS35L41_DSP1_WDT_CONTROL	0x02BC7000
484 #define CS35L41_DSP1_WDT_STATUS		0x02BC7008
485 #define CS35L41_DSP1_YMEM_PACK_0	0x02C00000
486 #define CS35L41_DSP1_YMEM_PACK_1532	0x02C017F0
487 #define CS35L41_DSP1_YMEM_UNPACK32_0	0x03000000
488 #define CS35L41_DSP1_YMEM_UNPACK32_1022	0x03000FF8
489 #define CS35L41_DSP1_YMEM_UNPACK24_0	0x03400000
490 #define CS35L41_DSP1_YMEM_UNPACK24_2045	0x03401FF4
491 #define CS35L41_DSP1_PMEM_0		0x03800000
492 #define CS35L41_DSP1_PMEM_5114		0x03804FE8
493 
494 /*test regs for emulation bringup*/
495 #define CS35L41_PLL_OVR			0x00003018
496 #define CS35L41_BST_TEST_DUTY		0x00003900
497 #define CS35L41_DIGPWM_IOCTRL		0x0000706C
498 
499 /*registers populated by OTP*/
500 #define CS35L41_OTP_TRIM_1		0x0000208c
501 #define CS35L41_OTP_TRIM_2		0x00002090
502 #define CS35L41_OTP_TRIM_3		0x00003010
503 #define CS35L41_OTP_TRIM_4		0x0000300C
504 #define CS35L41_OTP_TRIM_5		0x0000394C
505 #define CS35L41_OTP_TRIM_6		0x00003950
506 #define CS35L41_OTP_TRIM_7		0x00003954
507 #define CS35L41_OTP_TRIM_8		0x00003958
508 #define CS35L41_OTP_TRIM_9		0x0000395C
509 #define CS35L41_OTP_TRIM_10		0x0000416C
510 #define CS35L41_OTP_TRIM_11		0x00004160
511 #define CS35L41_OTP_TRIM_12		0x00004170
512 #define CS35L41_OTP_TRIM_13		0x00004360
513 #define CS35L41_OTP_TRIM_14		0x00004448
514 #define CS35L41_OTP_TRIM_15		0x0000444C
515 #define CS35L41_OTP_TRIM_16		0x00006E30
516 #define CS35L41_OTP_TRIM_17		0x00006E34
517 #define CS35L41_OTP_TRIM_18		0x00006E38
518 #define CS35L41_OTP_TRIM_19		0x00006E3C
519 #define CS35L41_OTP_TRIM_20		0x00006E40
520 #define CS35L41_OTP_TRIM_21		0x00006E44
521 #define CS35L41_OTP_TRIM_22		0x00006E48
522 #define CS35L41_OTP_TRIM_23		0x00006E4C
523 #define CS35L41_OTP_TRIM_24		0x00006E50
524 #define CS35L41_OTP_TRIM_25		0x00006E54
525 #define CS35L41_OTP_TRIM_26		0x00006E58
526 #define CS35L41_OTP_TRIM_27		0x00006E5C
527 #define CS35L41_OTP_TRIM_28		0x00006E60
528 #define CS35L41_OTP_TRIM_29		0x00006E64
529 #define CS35L41_OTP_TRIM_30		0x00007418
530 #define CS35L41_OTP_TRIM_31		0x0000741C
531 #define CS35L41_OTP_TRIM_32		0x00007434
532 #define CS35L41_OTP_TRIM_33		0x00007068
533 #define CS35L41_OTP_TRIM_34		0x0000410C
534 #define CS35L41_OTP_TRIM_35		0x0000400C
535 #define CS35L41_OTP_TRIM_36		0x00002030
536 
537 #define CS35L41_MAX_CACHE_REG		36
538 #define CS35L41_OTP_SIZE_WORDS		32
539 #define CS35L41_NUM_OTP_ELEM		100
540 
541 #define CS35L41_VALID_PDATA		0x80000000
542 #define CS35L41_NUM_SUPPLIES            2
543 
544 #define CS35L41_SCLK_MSTR_MASK		0x10
545 #define CS35L41_SCLK_MSTR_SHIFT		4
546 #define CS35L41_LRCLK_MSTR_MASK		0x01
547 #define CS35L41_LRCLK_MSTR_SHIFT	0
548 #define CS35L41_SCLK_INV_MASK		0x40
549 #define CS35L41_SCLK_INV_SHIFT		6
550 #define CS35L41_LRCLK_INV_MASK		0x04
551 #define CS35L41_LRCLK_INV_SHIFT		2
552 #define CS35L41_SCLK_FRC_MASK		0x20
553 #define CS35L41_SCLK_FRC_SHIFT		5
554 #define CS35L41_LRCLK_FRC_MASK		0x02
555 #define CS35L41_LRCLK_FRC_SHIFT		1
556 
557 #define CS35L41_AMP_GAIN_PCM_MASK	0x3E0
558 #define CS35L41_AMP_GAIN_ZC_MASK	0x0400
559 #define CS35L41_AMP_GAIN_ZC_SHIFT	10
560 
561 #define CS35L41_BST_CTL_MASK		0xFF
562 #define CS35L41_BST_CTL_SEL_MASK	0x03
563 #define CS35L41_BST_CTL_SEL_REG		0x00
564 #define CS35L41_BST_CTL_SEL_CLASSH	0x01
565 #define CS35L41_BST_IPK_MASK		0x7F
566 #define CS35L41_BST_IPK_SHIFT		0
567 #define CS35L41_BST_LIM_MASK		0x4
568 #define CS35L41_BST_LIM_SHIFT		2
569 #define CS35L41_BST_K1_MASK		0x000000FF
570 #define CS35L41_BST_K1_SHIFT		0
571 #define CS35L41_BST_K2_MASK		0x0000FF00
572 #define CS35L41_BST_K2_SHIFT		8
573 #define CS35L41_BST_SLOPE_MASK		0x0000FF00
574 #define CS35L41_BST_SLOPE_SHIFT		8
575 #define CS35L41_BST_LBST_VAL_MASK	0x00000003
576 #define CS35L41_BST_LBST_VAL_SHIFT	0
577 
578 #define CS35L41_TEMP_THLD_MASK		0x03
579 #define CS35L41_VMON_IMON_VOL_MASK	0x07FF07FF
580 #define CS35L41_PDM_MODE_MASK		0x01
581 #define CS35L41_PDM_MODE_SHIFT		0
582 
583 #define CS35L41_CH_MEM_DEPTH_MASK	0x07
584 #define CS35L41_CH_MEM_DEPTH_SHIFT	0
585 #define CS35L41_CH_HDRM_CTL_MASK	0x007F0000
586 #define CS35L41_CH_HDRM_CTL_SHIFT	16
587 #define CS35L41_CH_REL_RATE_MASK	0xFF00
588 #define CS35L41_CH_REL_RATE_SHIFT	8
589 #define CS35L41_CH_WKFET_DLY_MASK	0x001C
590 #define CS35L41_CH_WKFET_DLY_SHIFT	2
591 #define CS35L41_CH_WKFET_THLD_MASK	0x0F00
592 #define CS35L41_CH_WKFET_THLD_SHIFT	8
593 
594 #define CS35L41_HW_NG_SEL_MASK		0x3F00
595 #define CS35L41_HW_NG_SEL_SHIFT		8
596 #define CS35L41_HW_NG_DLY_MASK		0x0070
597 #define CS35L41_HW_NG_DLY_SHIFT		4
598 #define CS35L41_HW_NG_THLD_MASK		0x0007
599 #define CS35L41_HW_NG_THLD_SHIFT	0
600 
601 #define CS35L41_DSP_NG_ENABLE_MASK	0x00010000
602 #define CS35L41_DSP_NG_ENABLE_SHIFT	16
603 #define CS35L41_DSP_NG_THLD_MASK	0x7
604 #define CS35L41_DSP_NG_THLD_SHIFT	0
605 #define CS35L41_DSP_NG_DELAY_MASK	0x0F00
606 #define CS35L41_DSP_NG_DELAY_SHIFT	8
607 
608 #define CS35L41_ASP_FMT_MASK		0x0700
609 #define CS35L41_ASP_FMT_SHIFT		8
610 #define CS35L41_ASP_DOUT_HIZ_MASK	0x03
611 #define CS35L41_ASP_DOUT_HIZ_SHIFT	0
612 #define CS35L41_ASP_WIDTH_16		0x10
613 #define CS35L41_ASP_WIDTH_24		0x18
614 #define CS35L41_ASP_WIDTH_32		0x20
615 #define CS35L41_ASP_WIDTH_TX_MASK	0xFF0000
616 #define CS35L41_ASP_WIDTH_TX_SHIFT	16
617 #define CS35L41_ASP_WIDTH_RX_MASK	0xFF000000
618 #define CS35L41_ASP_WIDTH_RX_SHIFT	24
619 #define CS35L41_ASP_RX1_SLOT_MASK	0x3F
620 #define CS35L41_ASP_RX1_SLOT_SHIFT	0
621 #define CS35L41_ASP_RX2_SLOT_MASK	0x3F00
622 #define CS35L41_ASP_RX2_SLOT_SHIFT	8
623 #define CS35L41_ASP_RX_WL_MASK		0x3F
624 #define CS35L41_ASP_TX_WL_MASK		0x3F
625 #define CS35L41_ASP_RX_WL_SHIFT		0
626 #define CS35L41_ASP_TX_WL_SHIFT		0
627 #define CS35L41_ASP_SOURCE_MASK		0x7F
628 
629 #define CS35L41_INPUT_SRC_ASPRX1	0x08
630 #define CS35L41_INPUT_SRC_ASPRX2	0x09
631 #define CS35L41_INPUT_SRC_VMON		0x18
632 #define CS35L41_INPUT_SRC_IMON		0x19
633 #define CS35L41_INPUT_SRC_CLASSH	0x21
634 #define CS35L41_INPUT_SRC_VPMON		0x28
635 #define CS35L41_INPUT_SRC_VBSTMON	0x29
636 #define CS35L41_INPUT_SRC_TEMPMON	0x3A
637 #define CS35L41_INPUT_SRC_RSVD		0x3B
638 #define CS35L41_INPUT_DSP_TX1		0x32
639 #define CS35L41_INPUT_DSP_TX2		0x33
640 
641 #define CS35L41_WR_PEND_STS_MASK	0x2
642 
643 #define CS35L41_PLL_CLK_SEL_MASK	0x07
644 #define CS35L41_PLL_CLK_SEL_SHIFT	0
645 #define CS35L41_PLL_CLK_EN_MASK		0x10
646 #define CS35L41_PLL_CLK_EN_SHIFT	4
647 #define CS35L41_PLL_OPENLOOP_MASK	0x0800
648 #define CS35L41_PLL_OPENLOOP_SHIFT	11
649 #define CS35L41_PLLSRC_SCLK		0
650 #define CS35L41_PLLSRC_LRCLK		1
651 #define CS35L41_PLLSRC_SELF		3
652 #define CS35L41_PLLSRC_PDMCLK		4
653 #define CS35L41_PLLSRC_MCLK		5
654 #define CS35L41_PLLSRC_SWIRE		7
655 #define CS35L41_REFCLK_FREQ_MASK	0x7E0
656 #define CS35L41_REFCLK_FREQ_SHIFT	5
657 
658 #define CS35L41_GLOBAL_FS_MASK		0x1F
659 #define CS35L41_GLOBAL_FS_SHIFT		0
660 
661 #define CS35L41_GLOBAL_EN_MASK		0x01
662 #define CS35L41_GLOBAL_EN_SHIFT		0
663 #define CS35L41_BST_EN_MASK		0x0030
664 #define CS35L41_BST_EN_SHIFT		4
665 #define CS35L41_BST_EN_DEFAULT		0x2
666 #define CS35L41_AMP_EN_SHIFT		0
667 #define CS35L41_AMP_EN_MASK		1
668 
669 #define CS35L41_PDN_DONE_MASK		0x00800000
670 #define CS35L41_PDN_DONE_SHIFT		23
671 #define CS35L41_PUP_DONE_MASK		0x01000000
672 #define CS35L41_PUP_DONE_SHIFT		24
673 
674 #define CS35L36_PUP_DONE_IRQ_UNMASK	0x5F
675 #define CS35L36_PUP_DONE_IRQ_MASK	0xBF
676 
677 #define CS35L41_AMP_SHORT_ERR		0x80000000
678 #define CS35L41_BST_SHORT_ERR		0x0100
679 #define CS35L41_TEMP_WARN		0x8000
680 #define CS35L41_TEMP_ERR		0x00020000
681 #define CS35L41_BST_OVP_ERR		0x40
682 #define CS35L41_BST_DCM_UVP_ERR		0x80
683 #define CS35L41_OTP_BOOT_DONE		0x02
684 #define CS35L41_PLL_UNLOCK		0x10
685 #define CS35L41_OTP_BOOT_ERR		0x80000000
686 
687 #define CS35L41_AMP_SHORT_ERR_RLS	0x02
688 #define CS35L41_BST_SHORT_ERR_RLS	0x04
689 #define CS35L41_BST_OVP_ERR_RLS		0x08
690 #define CS35L41_BST_UVP_ERR_RLS		0x10
691 #define CS35L41_TEMP_WARN_ERR_RLS	0x20
692 #define CS35L41_TEMP_ERR_RLS		0x40
693 
694 #define CS35L41_INT1_MASK_DEFAULT	0x7FFCFE3F
695 #define CS35L41_INT1_UNMASK_PUP		0xFEFFFFFF
696 #define CS35L41_INT1_UNMASK_PDN		0xFF7FFFFF
697 
698 #define CS35L41_GPIO_DIR_MASK		0x80000000
699 #define CS35L41_GPIO_DIR_SHIFT		31
700 #define CS35L41_GPIO1_CTRL_MASK		0x00030000
701 #define CS35L41_GPIO1_CTRL_SHIFT	16
702 #define CS35L41_GPIO2_CTRL_MASK		0x07000000
703 #define CS35L41_GPIO2_CTRL_SHIFT	24
704 #define CS35L41_GPIO_CTRL_OPEN_INT	2
705 #define CS35L41_GPIO_CTRL_ACTV_LO	4
706 #define CS35L41_GPIO_CTRL_ACTV_HI	5
707 #define CS35L41_GPIO_POL_MASK		0x1000
708 #define CS35L41_GPIO_POL_SHIFT		12
709 
710 #define CS35L41_AMP_INV_PCM_SHIFT	14
711 #define CS35L41_AMP_INV_PCM_MASK	BIT(CS35L41_AMP_INV_PCM_SHIFT)
712 #define CS35L41_AMP_PCM_VOL_SHIFT	3
713 #define CS35L41_AMP_PCM_VOL_MASK	(0x7FF << 3)
714 #define CS35L41_AMP_PCM_VOL_MUTE	0x4CF
715 
716 #define CS35L41_CHIP_ID			0x35a40
717 #define CS35L41R_CHIP_ID		0x35b40
718 #define CS35L41_MTLREVID_MASK		0x0F
719 #define CS35L41_REVID_A0		0xA0
720 #define CS35L41_REVID_B0		0xB0
721 #define CS35L41_REVID_B2		0xB2
722 
723 #define CS35L41_HALO_CORE_RESET		0x00000200
724 
725 #define CS35L41_FS1_WINDOW_MASK		0x000007FF
726 #define CS35L41_FS2_WINDOW_MASK		0x00FFF800
727 #define CS35L41_FS2_WINDOW_SHIFT	12
728 
729 #define CS35L41_SPI_MAX_FREQ		4000000
730 #define CS35L41_REGSTRIDE		4
731 
732 enum cs35l41_clk_ids {
733 	CS35L41_CLKID_SCLK = 0,
734 	CS35L41_CLKID_LRCLK = 1,
735 	CS35L41_CLKID_MCLK = 4,
736 };
737 
738 struct cs35l41_irq_cfg {
739 	bool irq_pol_inv;
740 	bool irq_out_en;
741 	int irq_src_sel;
742 };
743 
744 struct cs35l41_platform_data {
745 	int bst_ind;
746 	int bst_ipk;
747 	int bst_cap;
748 	int dout_hiz;
749 	struct cs35l41_irq_cfg irq_config1;
750 	struct cs35l41_irq_cfg irq_config2;
751 };
752 
753 struct cs35l41_otp_packed_element_t {
754 	u32 reg;
755 	u8 shift;
756 	u8 size;
757 };
758 
759 struct cs35l41_otp_map_element_t {
760 	u32 id;
761 	u32 num_elements;
762 	const struct cs35l41_otp_packed_element_t *map;
763 	u32 bit_offset;
764 	u32 word_offset;
765 };
766 
767 extern struct regmap_config cs35l41_regmap_i2c;
768 extern struct regmap_config cs35l41_regmap_spi;
769 
770 int cs35l41_test_key_unlock(struct device *dev, struct regmap *regmap);
771 int cs35l41_test_key_lock(struct device *dev, struct regmap *regmap);
772 int cs35l41_otp_unpack(struct device *dev, struct regmap *regmap);
773 int cs35l41_register_errata_patch(struct device *dev, struct regmap *reg, unsigned int reg_revid);
774 int cs35l41_set_channels(struct device *dev, struct regmap *reg,
775 			 unsigned int tx_num, unsigned int *tx_slot,
776 			 unsigned int rx_num, unsigned int *rx_slot);
777 int cs35l41_boost_config(struct device *dev, struct regmap *regmap, int boost_ind, int boost_cap,
778 			 int boost_ipk);
779 
780 #endif /* __CS35L41_H */
781