1718dceddSDavid Howells /* exynos_drm.h 2718dceddSDavid Howells * 3718dceddSDavid Howells * Copyright (c) 2011 Samsung Electronics Co., Ltd. 4718dceddSDavid Howells * Authors: 5718dceddSDavid Howells * Inki Dae <inki.dae@samsung.com> 6718dceddSDavid Howells * Joonyoung Shim <jy0922.shim@samsung.com> 7718dceddSDavid Howells * Seung-Woo Kim <sw0312.kim@samsung.com> 8718dceddSDavid Howells * 9d81aecb5SInki Dae * This program is free software; you can redistribute it and/or modify it 10d81aecb5SInki Dae * under the terms of the GNU General Public License as published by the 11d81aecb5SInki Dae * Free Software Foundation; either version 2 of the License, or (at your 12d81aecb5SInki Dae * option) any later version. 13718dceddSDavid Howells */ 14718dceddSDavid Howells 15718dceddSDavid Howells #ifndef _UAPI_EXYNOS_DRM_H_ 16718dceddSDavid Howells #define _UAPI_EXYNOS_DRM_H_ 17718dceddSDavid Howells 1819b1e97aSGabriel Laskar #include "drm.h" 19718dceddSDavid Howells 20718dceddSDavid Howells /** 21718dceddSDavid Howells * User-desired buffer creation information structure. 22718dceddSDavid Howells * 23718dceddSDavid Howells * @size: user-desired memory allocation size. 24718dceddSDavid Howells * - this size value would be page-aligned internally. 25718dceddSDavid Howells * @flags: user request for setting memory type or cache attributes. 26718dceddSDavid Howells * @handle: returned a handle to created gem object. 27718dceddSDavid Howells * - this handle will be set by gem module of kernel side. 28718dceddSDavid Howells */ 29718dceddSDavid Howells struct drm_exynos_gem_create { 306615b20fSMikko Rapeli __u64 size; 31*cbf0acefSAndrzej Hajda __u32 flags; 32*cbf0acefSAndrzej Hajda __u32 handle; 33718dceddSDavid Howells }; 34718dceddSDavid Howells 35718dceddSDavid Howells /** 36718dceddSDavid Howells * A structure to gem information. 37718dceddSDavid Howells * 38718dceddSDavid Howells * @handle: a handle to gem object created. 39718dceddSDavid Howells * @flags: flag value including memory type and cache attribute and 40718dceddSDavid Howells * this value would be set by driver. 41718dceddSDavid Howells * @size: size to memory region allocated by gem and this size would 42718dceddSDavid Howells * be set by driver. 43718dceddSDavid Howells */ 44718dceddSDavid Howells struct drm_exynos_gem_info { 45*cbf0acefSAndrzej Hajda __u32 handle; 46*cbf0acefSAndrzej Hajda __u32 flags; 476615b20fSMikko Rapeli __u64 size; 48718dceddSDavid Howells }; 49718dceddSDavid Howells 50718dceddSDavid Howells /** 51718dceddSDavid Howells * A structure for user connection request of virtual display. 52718dceddSDavid Howells * 53718dceddSDavid Howells * @connection: indicate whether doing connetion or not by user. 54718dceddSDavid Howells * @extensions: if this value is 1 then the vidi driver would need additional 55718dceddSDavid Howells * 128bytes edid data. 56718dceddSDavid Howells * @edid: the edid data pointer from user side. 57718dceddSDavid Howells */ 58718dceddSDavid Howells struct drm_exynos_vidi_connection { 59*cbf0acefSAndrzej Hajda __u32 connection; 60*cbf0acefSAndrzej Hajda __u32 extensions; 616615b20fSMikko Rapeli __u64 edid; 62718dceddSDavid Howells }; 63718dceddSDavid Howells 64718dceddSDavid Howells /* memory type definitions. */ 65718dceddSDavid Howells enum e_drm_exynos_gem_mem_type { 66718dceddSDavid Howells /* Physically Continuous memory and used as default. */ 67718dceddSDavid Howells EXYNOS_BO_CONTIG = 0 << 0, 68718dceddSDavid Howells /* Physically Non-Continuous memory. */ 69718dceddSDavid Howells EXYNOS_BO_NONCONTIG = 1 << 0, 70718dceddSDavid Howells /* non-cachable mapping and used as default. */ 71718dceddSDavid Howells EXYNOS_BO_NONCACHABLE = 0 << 1, 72718dceddSDavid Howells /* cachable mapping. */ 73718dceddSDavid Howells EXYNOS_BO_CACHABLE = 1 << 1, 74718dceddSDavid Howells /* write-combine mapping. */ 75718dceddSDavid Howells EXYNOS_BO_WC = 1 << 2, 76718dceddSDavid Howells EXYNOS_BO_MASK = EXYNOS_BO_NONCONTIG | EXYNOS_BO_CACHABLE | 77718dceddSDavid Howells EXYNOS_BO_WC 78718dceddSDavid Howells }; 79718dceddSDavid Howells 80718dceddSDavid Howells struct drm_exynos_g2d_get_ver { 81718dceddSDavid Howells __u32 major; 82718dceddSDavid Howells __u32 minor; 83718dceddSDavid Howells }; 84718dceddSDavid Howells 85718dceddSDavid Howells struct drm_exynos_g2d_cmd { 86718dceddSDavid Howells __u32 offset; 87718dceddSDavid Howells __u32 data; 88718dceddSDavid Howells }; 89718dceddSDavid Howells 902a3098ffSInki Dae enum drm_exynos_g2d_buf_type { 912a3098ffSInki Dae G2D_BUF_USERPTR = 1 << 31, 922a3098ffSInki Dae }; 932a3098ffSInki Dae 94718dceddSDavid Howells enum drm_exynos_g2d_event_type { 95718dceddSDavid Howells G2D_EVENT_NOT, 96718dceddSDavid Howells G2D_EVENT_NONSTOP, 97718dceddSDavid Howells G2D_EVENT_STOP, /* not yet */ 98718dceddSDavid Howells }; 99718dceddSDavid Howells 1002a3098ffSInki Dae struct drm_exynos_g2d_userptr { 1012a3098ffSInki Dae unsigned long userptr; 1022a3098ffSInki Dae unsigned long size; 1032a3098ffSInki Dae }; 1042a3098ffSInki Dae 105718dceddSDavid Howells struct drm_exynos_g2d_set_cmdlist { 106718dceddSDavid Howells __u64 cmd; 1072a3098ffSInki Dae __u64 cmd_buf; 108718dceddSDavid Howells __u32 cmd_nr; 1092a3098ffSInki Dae __u32 cmd_buf_nr; 110718dceddSDavid Howells 111718dceddSDavid Howells /* for g2d event */ 112718dceddSDavid Howells __u64 event_type; 113718dceddSDavid Howells __u64 user_data; 114718dceddSDavid Howells }; 115718dceddSDavid Howells 116718dceddSDavid Howells struct drm_exynos_g2d_exec { 117718dceddSDavid Howells __u64 async; 118718dceddSDavid Howells }; 119718dceddSDavid Howells 120cb471f14SEunchul Kim enum drm_exynos_ops_id { 121cb471f14SEunchul Kim EXYNOS_DRM_OPS_SRC, 122cb471f14SEunchul Kim EXYNOS_DRM_OPS_DST, 123cb471f14SEunchul Kim EXYNOS_DRM_OPS_MAX, 124cb471f14SEunchul Kim }; 125cb471f14SEunchul Kim 126cb471f14SEunchul Kim struct drm_exynos_sz { 127cb471f14SEunchul Kim __u32 hsize; 128cb471f14SEunchul Kim __u32 vsize; 129cb471f14SEunchul Kim }; 130cb471f14SEunchul Kim 131cb471f14SEunchul Kim struct drm_exynos_pos { 132cb471f14SEunchul Kim __u32 x; 133cb471f14SEunchul Kim __u32 y; 134cb471f14SEunchul Kim __u32 w; 135cb471f14SEunchul Kim __u32 h; 136cb471f14SEunchul Kim }; 137cb471f14SEunchul Kim 138cb471f14SEunchul Kim enum drm_exynos_flip { 139cb471f14SEunchul Kim EXYNOS_DRM_FLIP_NONE = (0 << 0), 140cb471f14SEunchul Kim EXYNOS_DRM_FLIP_VERTICAL = (1 << 0), 141cb471f14SEunchul Kim EXYNOS_DRM_FLIP_HORIZONTAL = (1 << 1), 1424f21877cSEunchul Kim EXYNOS_DRM_FLIP_BOTH = EXYNOS_DRM_FLIP_VERTICAL | 1434f21877cSEunchul Kim EXYNOS_DRM_FLIP_HORIZONTAL, 144cb471f14SEunchul Kim }; 145cb471f14SEunchul Kim 146cb471f14SEunchul Kim enum drm_exynos_degree { 147cb471f14SEunchul Kim EXYNOS_DRM_DEGREE_0, 148cb471f14SEunchul Kim EXYNOS_DRM_DEGREE_90, 149cb471f14SEunchul Kim EXYNOS_DRM_DEGREE_180, 150cb471f14SEunchul Kim EXYNOS_DRM_DEGREE_270, 151cb471f14SEunchul Kim }; 152cb471f14SEunchul Kim 153cb471f14SEunchul Kim enum drm_exynos_planer { 154cb471f14SEunchul Kim EXYNOS_DRM_PLANAR_Y, 155cb471f14SEunchul Kim EXYNOS_DRM_PLANAR_CB, 156cb471f14SEunchul Kim EXYNOS_DRM_PLANAR_CR, 157cb471f14SEunchul Kim EXYNOS_DRM_PLANAR_MAX, 158cb471f14SEunchul Kim }; 159cb471f14SEunchul Kim 160cb471f14SEunchul Kim /** 161cb471f14SEunchul Kim * A structure for ipp supported property list. 162cb471f14SEunchul Kim * 163cb471f14SEunchul Kim * @version: version of this structure. 164cb471f14SEunchul Kim * @ipp_id: id of ipp driver. 165cb471f14SEunchul Kim * @count: count of ipp driver. 166cb471f14SEunchul Kim * @writeback: flag of writeback supporting. 167cb471f14SEunchul Kim * @flip: flag of flip supporting. 168cb471f14SEunchul Kim * @degree: flag of degree information. 169cb471f14SEunchul Kim * @csc: flag of csc supporting. 170cb471f14SEunchul Kim * @crop: flag of crop supporting. 171cb471f14SEunchul Kim * @scale: flag of scale supporting. 172cb471f14SEunchul Kim * @refresh_min: min hz of refresh. 173cb471f14SEunchul Kim * @refresh_max: max hz of refresh. 174cb471f14SEunchul Kim * @crop_min: crop min resolution. 175cb471f14SEunchul Kim * @crop_max: crop max resolution. 176cb471f14SEunchul Kim * @scale_min: scale min resolution. 177cb471f14SEunchul Kim * @scale_max: scale max resolution. 178cb471f14SEunchul Kim */ 179cb471f14SEunchul Kim struct drm_exynos_ipp_prop_list { 180cb471f14SEunchul Kim __u32 version; 181cb471f14SEunchul Kim __u32 ipp_id; 182cb471f14SEunchul Kim __u32 count; 183cb471f14SEunchul Kim __u32 writeback; 184cb471f14SEunchul Kim __u32 flip; 185cb471f14SEunchul Kim __u32 degree; 186cb471f14SEunchul Kim __u32 csc; 187cb471f14SEunchul Kim __u32 crop; 188cb471f14SEunchul Kim __u32 scale; 189cb471f14SEunchul Kim __u32 refresh_min; 190cb471f14SEunchul Kim __u32 refresh_max; 191cb471f14SEunchul Kim __u32 reserved; 192cb471f14SEunchul Kim struct drm_exynos_sz crop_min; 193cb471f14SEunchul Kim struct drm_exynos_sz crop_max; 194cb471f14SEunchul Kim struct drm_exynos_sz scale_min; 195cb471f14SEunchul Kim struct drm_exynos_sz scale_max; 196cb471f14SEunchul Kim }; 197cb471f14SEunchul Kim 198cb471f14SEunchul Kim /** 199cb471f14SEunchul Kim * A structure for ipp config. 200cb471f14SEunchul Kim * 201cb471f14SEunchul Kim * @ops_id: property of operation directions. 202cb471f14SEunchul Kim * @flip: property of mirror, flip. 203cb471f14SEunchul Kim * @degree: property of rotation degree. 204cb471f14SEunchul Kim * @fmt: property of image format. 205cb471f14SEunchul Kim * @sz: property of image size. 206cb471f14SEunchul Kim * @pos: property of image position(src-cropped,dst-scaler). 207cb471f14SEunchul Kim */ 208cb471f14SEunchul Kim struct drm_exynos_ipp_config { 209*cbf0acefSAndrzej Hajda __u32 ops_id; 210*cbf0acefSAndrzej Hajda __u32 flip; 211*cbf0acefSAndrzej Hajda __u32 degree; 212cb471f14SEunchul Kim __u32 fmt; 213cb471f14SEunchul Kim struct drm_exynos_sz sz; 214cb471f14SEunchul Kim struct drm_exynos_pos pos; 215cb471f14SEunchul Kim }; 216cb471f14SEunchul Kim 217cb471f14SEunchul Kim enum drm_exynos_ipp_cmd { 218cb471f14SEunchul Kim IPP_CMD_NONE, 219cb471f14SEunchul Kim IPP_CMD_M2M, 220cb471f14SEunchul Kim IPP_CMD_WB, 221cb471f14SEunchul Kim IPP_CMD_OUTPUT, 222cb471f14SEunchul Kim IPP_CMD_MAX, 223cb471f14SEunchul Kim }; 224cb471f14SEunchul Kim 225cb471f14SEunchul Kim /** 226cb471f14SEunchul Kim * A structure for ipp property. 227cb471f14SEunchul Kim * 228cb471f14SEunchul Kim * @config: source, destination config. 229cb471f14SEunchul Kim * @cmd: definition of command. 230cb471f14SEunchul Kim * @ipp_id: id of ipp driver. 231cb471f14SEunchul Kim * @prop_id: id of property. 232cb471f14SEunchul Kim * @refresh_rate: refresh rate. 233cb471f14SEunchul Kim */ 234cb471f14SEunchul Kim struct drm_exynos_ipp_property { 235cb471f14SEunchul Kim struct drm_exynos_ipp_config config[EXYNOS_DRM_OPS_MAX]; 236*cbf0acefSAndrzej Hajda __u32 cmd; 237cb471f14SEunchul Kim __u32 ipp_id; 238cb471f14SEunchul Kim __u32 prop_id; 239cb471f14SEunchul Kim __u32 refresh_rate; 240cb471f14SEunchul Kim }; 241cb471f14SEunchul Kim 242cb471f14SEunchul Kim enum drm_exynos_ipp_buf_type { 243cb471f14SEunchul Kim IPP_BUF_ENQUEUE, 244cb471f14SEunchul Kim IPP_BUF_DEQUEUE, 245cb471f14SEunchul Kim }; 246cb471f14SEunchul Kim 247cb471f14SEunchul Kim /** 248cb471f14SEunchul Kim * A structure for ipp buffer operations. 249cb471f14SEunchul Kim * 250cb471f14SEunchul Kim * @ops_id: operation directions. 251cb471f14SEunchul Kim * @buf_type: definition of buffer. 252cb471f14SEunchul Kim * @prop_id: id of property. 253cb471f14SEunchul Kim * @buf_id: id of buffer. 254cb471f14SEunchul Kim * @handle: Y, Cb, Cr each planar handle. 255cb471f14SEunchul Kim * @user_data: user data. 256cb471f14SEunchul Kim */ 257cb471f14SEunchul Kim struct drm_exynos_ipp_queue_buf { 258*cbf0acefSAndrzej Hajda __u32 ops_id; 259*cbf0acefSAndrzej Hajda __u32 buf_type; 260cb471f14SEunchul Kim __u32 prop_id; 261cb471f14SEunchul Kim __u32 buf_id; 262cb471f14SEunchul Kim __u32 handle[EXYNOS_DRM_PLANAR_MAX]; 263cb471f14SEunchul Kim __u32 reserved; 264cb471f14SEunchul Kim __u64 user_data; 265cb471f14SEunchul Kim }; 266cb471f14SEunchul Kim 267cb471f14SEunchul Kim enum drm_exynos_ipp_ctrl { 268cb471f14SEunchul Kim IPP_CTRL_PLAY, 269cb471f14SEunchul Kim IPP_CTRL_STOP, 270cb471f14SEunchul Kim IPP_CTRL_PAUSE, 271cb471f14SEunchul Kim IPP_CTRL_RESUME, 272cb471f14SEunchul Kim IPP_CTRL_MAX, 273cb471f14SEunchul Kim }; 274cb471f14SEunchul Kim 275cb471f14SEunchul Kim /** 276cb471f14SEunchul Kim * A structure for ipp start/stop operations. 277cb471f14SEunchul Kim * 278cb471f14SEunchul Kim * @prop_id: id of property. 279cb471f14SEunchul Kim * @ctrl: definition of control. 280cb471f14SEunchul Kim */ 281cb471f14SEunchul Kim struct drm_exynos_ipp_cmd_ctrl { 282cb471f14SEunchul Kim __u32 prop_id; 283*cbf0acefSAndrzej Hajda __u32 ctrl; 284cb471f14SEunchul Kim }; 285cb471f14SEunchul Kim 286718dceddSDavid Howells #define DRM_EXYNOS_GEM_CREATE 0x00 287718dceddSDavid Howells /* Reserved 0x03 ~ 0x05 for exynos specific gem ioctl */ 288718dceddSDavid Howells #define DRM_EXYNOS_GEM_GET 0x04 289718dceddSDavid Howells #define DRM_EXYNOS_VIDI_CONNECTION 0x07 290718dceddSDavid Howells 291718dceddSDavid Howells /* G2D */ 292718dceddSDavid Howells #define DRM_EXYNOS_G2D_GET_VER 0x20 293718dceddSDavid Howells #define DRM_EXYNOS_G2D_SET_CMDLIST 0x21 294718dceddSDavid Howells #define DRM_EXYNOS_G2D_EXEC 0x22 295718dceddSDavid Howells 296cb471f14SEunchul Kim /* IPP - Image Post Processing */ 297cb471f14SEunchul Kim #define DRM_EXYNOS_IPP_GET_PROPERTY 0x30 298cb471f14SEunchul Kim #define DRM_EXYNOS_IPP_SET_PROPERTY 0x31 299cb471f14SEunchul Kim #define DRM_EXYNOS_IPP_QUEUE_BUF 0x32 300cb471f14SEunchul Kim #define DRM_EXYNOS_IPP_CMD_CTRL 0x33 301cb471f14SEunchul Kim 302718dceddSDavid Howells #define DRM_IOCTL_EXYNOS_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + \ 303718dceddSDavid Howells DRM_EXYNOS_GEM_CREATE, struct drm_exynos_gem_create) 304718dceddSDavid Howells 305718dceddSDavid Howells #define DRM_IOCTL_EXYNOS_GEM_GET DRM_IOWR(DRM_COMMAND_BASE + \ 306718dceddSDavid Howells DRM_EXYNOS_GEM_GET, struct drm_exynos_gem_info) 307718dceddSDavid Howells 308718dceddSDavid Howells #define DRM_IOCTL_EXYNOS_VIDI_CONNECTION DRM_IOWR(DRM_COMMAND_BASE + \ 309718dceddSDavid Howells DRM_EXYNOS_VIDI_CONNECTION, struct drm_exynos_vidi_connection) 310718dceddSDavid Howells 311718dceddSDavid Howells #define DRM_IOCTL_EXYNOS_G2D_GET_VER DRM_IOWR(DRM_COMMAND_BASE + \ 312718dceddSDavid Howells DRM_EXYNOS_G2D_GET_VER, struct drm_exynos_g2d_get_ver) 313718dceddSDavid Howells #define DRM_IOCTL_EXYNOS_G2D_SET_CMDLIST DRM_IOWR(DRM_COMMAND_BASE + \ 314718dceddSDavid Howells DRM_EXYNOS_G2D_SET_CMDLIST, struct drm_exynos_g2d_set_cmdlist) 315718dceddSDavid Howells #define DRM_IOCTL_EXYNOS_G2D_EXEC DRM_IOWR(DRM_COMMAND_BASE + \ 316718dceddSDavid Howells DRM_EXYNOS_G2D_EXEC, struct drm_exynos_g2d_exec) 317718dceddSDavid Howells 318cb471f14SEunchul Kim #define DRM_IOCTL_EXYNOS_IPP_GET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + \ 319cb471f14SEunchul Kim DRM_EXYNOS_IPP_GET_PROPERTY, struct drm_exynos_ipp_prop_list) 320cb471f14SEunchul Kim #define DRM_IOCTL_EXYNOS_IPP_SET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + \ 321cb471f14SEunchul Kim DRM_EXYNOS_IPP_SET_PROPERTY, struct drm_exynos_ipp_property) 322cb471f14SEunchul Kim #define DRM_IOCTL_EXYNOS_IPP_QUEUE_BUF DRM_IOWR(DRM_COMMAND_BASE + \ 323cb471f14SEunchul Kim DRM_EXYNOS_IPP_QUEUE_BUF, struct drm_exynos_ipp_queue_buf) 324cb471f14SEunchul Kim #define DRM_IOCTL_EXYNOS_IPP_CMD_CTRL DRM_IOWR(DRM_COMMAND_BASE + \ 325cb471f14SEunchul Kim DRM_EXYNOS_IPP_CMD_CTRL, struct drm_exynos_ipp_cmd_ctrl) 326cb471f14SEunchul Kim 327718dceddSDavid Howells /* EXYNOS specific events */ 328718dceddSDavid Howells #define DRM_EXYNOS_G2D_EVENT 0x80000000 329cb471f14SEunchul Kim #define DRM_EXYNOS_IPP_EVENT 0x80000001 330718dceddSDavid Howells 331718dceddSDavid Howells struct drm_exynos_g2d_event { 332718dceddSDavid Howells struct drm_event base; 333718dceddSDavid Howells __u64 user_data; 334718dceddSDavid Howells __u32 tv_sec; 335718dceddSDavid Howells __u32 tv_usec; 336718dceddSDavid Howells __u32 cmdlist_no; 337718dceddSDavid Howells __u32 reserved; 338718dceddSDavid Howells }; 339718dceddSDavid Howells 340cb471f14SEunchul Kim struct drm_exynos_ipp_event { 341cb471f14SEunchul Kim struct drm_event base; 342cb471f14SEunchul Kim __u64 user_data; 343cb471f14SEunchul Kim __u32 tv_sec; 344cb471f14SEunchul Kim __u32 tv_usec; 345cb471f14SEunchul Kim __u32 prop_id; 346cb471f14SEunchul Kim __u32 reserved; 347cb471f14SEunchul Kim __u32 buf_id[EXYNOS_DRM_OPS_MAX]; 348cb471f14SEunchul Kim }; 349cb471f14SEunchul Kim 350718dceddSDavid Howells #endif /* _UAPI_EXYNOS_DRM_H_ */ 351