1c501ca23SJeffrey Hugo /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note 2c501ca23SJeffrey Hugo * 3c501ca23SJeffrey Hugo * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. 4c501ca23SJeffrey Hugo * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. 5c501ca23SJeffrey Hugo */ 6c501ca23SJeffrey Hugo 7c501ca23SJeffrey Hugo #ifndef QAIC_ACCEL_H_ 8c501ca23SJeffrey Hugo #define QAIC_ACCEL_H_ 9c501ca23SJeffrey Hugo 10c501ca23SJeffrey Hugo #include "drm.h" 11c501ca23SJeffrey Hugo 12c501ca23SJeffrey Hugo #if defined(__cplusplus) 13c501ca23SJeffrey Hugo extern "C" { 14c501ca23SJeffrey Hugo #endif 15c501ca23SJeffrey Hugo 16c501ca23SJeffrey Hugo /* The length(4K) includes len and count fields of qaic_manage_msg */ 17c501ca23SJeffrey Hugo #define QAIC_MANAGE_MAX_MSG_LENGTH SZ_4K 18c501ca23SJeffrey Hugo 19c501ca23SJeffrey Hugo /* semaphore flags */ 20c501ca23SJeffrey Hugo #define QAIC_SEM_INSYNCFENCE 2 21c501ca23SJeffrey Hugo #define QAIC_SEM_OUTSYNCFENCE 1 22c501ca23SJeffrey Hugo 23c501ca23SJeffrey Hugo /* Semaphore commands */ 24c501ca23SJeffrey Hugo #define QAIC_SEM_NOP 0 25c501ca23SJeffrey Hugo #define QAIC_SEM_INIT 1 26c501ca23SJeffrey Hugo #define QAIC_SEM_INC 2 27c501ca23SJeffrey Hugo #define QAIC_SEM_DEC 3 28c501ca23SJeffrey Hugo #define QAIC_SEM_WAIT_EQUAL 4 29c501ca23SJeffrey Hugo #define QAIC_SEM_WAIT_GT_EQ 5 /* Greater than or equal */ 30c501ca23SJeffrey Hugo #define QAIC_SEM_WAIT_GT_0 6 /* Greater than 0 */ 31c501ca23SJeffrey Hugo 32c501ca23SJeffrey Hugo #define QAIC_TRANS_UNDEFINED 0 33c501ca23SJeffrey Hugo #define QAIC_TRANS_PASSTHROUGH_FROM_USR 1 34c501ca23SJeffrey Hugo #define QAIC_TRANS_PASSTHROUGH_TO_USR 2 35c501ca23SJeffrey Hugo #define QAIC_TRANS_PASSTHROUGH_FROM_DEV 3 36c501ca23SJeffrey Hugo #define QAIC_TRANS_PASSTHROUGH_TO_DEV 4 37c501ca23SJeffrey Hugo #define QAIC_TRANS_DMA_XFER_FROM_USR 5 38c501ca23SJeffrey Hugo #define QAIC_TRANS_DMA_XFER_TO_DEV 6 39c501ca23SJeffrey Hugo #define QAIC_TRANS_ACTIVATE_FROM_USR 7 40c501ca23SJeffrey Hugo #define QAIC_TRANS_ACTIVATE_FROM_DEV 8 41c501ca23SJeffrey Hugo #define QAIC_TRANS_ACTIVATE_TO_DEV 9 42c501ca23SJeffrey Hugo #define QAIC_TRANS_DEACTIVATE_FROM_USR 10 43c501ca23SJeffrey Hugo #define QAIC_TRANS_DEACTIVATE_FROM_DEV 11 44c501ca23SJeffrey Hugo #define QAIC_TRANS_STATUS_FROM_USR 12 45c501ca23SJeffrey Hugo #define QAIC_TRANS_STATUS_TO_USR 13 46c501ca23SJeffrey Hugo #define QAIC_TRANS_STATUS_FROM_DEV 14 47c501ca23SJeffrey Hugo #define QAIC_TRANS_STATUS_TO_DEV 15 48c501ca23SJeffrey Hugo #define QAIC_TRANS_TERMINATE_FROM_DEV 16 49c501ca23SJeffrey Hugo #define QAIC_TRANS_TERMINATE_TO_DEV 17 50c501ca23SJeffrey Hugo #define QAIC_TRANS_DMA_XFER_CONT 18 51c501ca23SJeffrey Hugo #define QAIC_TRANS_VALIDATE_PARTITION_FROM_DEV 19 52c501ca23SJeffrey Hugo #define QAIC_TRANS_VALIDATE_PARTITION_TO_DEV 20 53c501ca23SJeffrey Hugo 54c501ca23SJeffrey Hugo /** 55c501ca23SJeffrey Hugo * struct qaic_manage_trans_hdr - Header for a transaction in a manage message. 56c501ca23SJeffrey Hugo * @type: In. Identifies this transaction. See QAIC_TRANS_* defines. 57c501ca23SJeffrey Hugo * @len: In. Length of this transaction, including this header. 58c501ca23SJeffrey Hugo */ 59c501ca23SJeffrey Hugo struct qaic_manage_trans_hdr { 60c501ca23SJeffrey Hugo __u32 type; 61c501ca23SJeffrey Hugo __u32 len; 62c501ca23SJeffrey Hugo }; 63c501ca23SJeffrey Hugo 64c501ca23SJeffrey Hugo /** 65c501ca23SJeffrey Hugo * struct qaic_manage_trans_passthrough - Defines a passthrough transaction. 66c501ca23SJeffrey Hugo * @hdr: In. Header to identify this transaction. 67c501ca23SJeffrey Hugo * @data: In. Payload of this ransaction. Opaque to the driver. Userspace must 68c501ca23SJeffrey Hugo * encode in little endian and align/pad to 64-bit. 69c501ca23SJeffrey Hugo */ 70c501ca23SJeffrey Hugo struct qaic_manage_trans_passthrough { 71c501ca23SJeffrey Hugo struct qaic_manage_trans_hdr hdr; 72c501ca23SJeffrey Hugo __u8 data[]; 73c501ca23SJeffrey Hugo }; 74c501ca23SJeffrey Hugo 75c501ca23SJeffrey Hugo /** 76c501ca23SJeffrey Hugo * struct qaic_manage_trans_dma_xfer - Defines a DMA transfer transaction. 77c501ca23SJeffrey Hugo * @hdr: In. Header to identify this transaction. 78c501ca23SJeffrey Hugo * @tag: In. Identified this transfer in other transactions. Opaque to the 79c501ca23SJeffrey Hugo * driver. 80c501ca23SJeffrey Hugo * @pad: Structure padding. 81c501ca23SJeffrey Hugo * @addr: In. Address of the data to DMA to the device. 82c501ca23SJeffrey Hugo * @size: In. Length of the data to DMA to the device. 83c501ca23SJeffrey Hugo */ 84c501ca23SJeffrey Hugo struct qaic_manage_trans_dma_xfer { 85c501ca23SJeffrey Hugo struct qaic_manage_trans_hdr hdr; 86c501ca23SJeffrey Hugo __u32 tag; 87c501ca23SJeffrey Hugo __u32 pad; 88c501ca23SJeffrey Hugo __u64 addr; 89c501ca23SJeffrey Hugo __u64 size; 90c501ca23SJeffrey Hugo }; 91c501ca23SJeffrey Hugo 92c501ca23SJeffrey Hugo /** 93c501ca23SJeffrey Hugo * struct qaic_manage_trans_activate_to_dev - Defines an activate request. 94c501ca23SJeffrey Hugo * @hdr: In. Header to identify this transaction. 95c501ca23SJeffrey Hugo * @queue_size: In. Number of elements for DBC request and response queues. 96c501ca23SJeffrey Hugo * @eventfd: Unused. 97c501ca23SJeffrey Hugo * @options: In. Device specific options for this activate. 98c501ca23SJeffrey Hugo * @pad: Structure padding. Must be 0. 99c501ca23SJeffrey Hugo */ 100c501ca23SJeffrey Hugo struct qaic_manage_trans_activate_to_dev { 101c501ca23SJeffrey Hugo struct qaic_manage_trans_hdr hdr; 102c501ca23SJeffrey Hugo __u32 queue_size; 103c501ca23SJeffrey Hugo __u32 eventfd; 104c501ca23SJeffrey Hugo __u32 options; 105c501ca23SJeffrey Hugo __u32 pad; 106c501ca23SJeffrey Hugo }; 107c501ca23SJeffrey Hugo 108c501ca23SJeffrey Hugo /** 109c501ca23SJeffrey Hugo * struct qaic_manage_trans_activate_from_dev - Defines an activate response. 110c501ca23SJeffrey Hugo * @hdr: Out. Header to identify this transaction. 111c501ca23SJeffrey Hugo * @status: Out. Return code of the request from the device. 112c501ca23SJeffrey Hugo * @dbc_id: Out. Id of the assigned DBC for successful request. 113c501ca23SJeffrey Hugo * @options: Out. Device specific options for this activate. 114c501ca23SJeffrey Hugo */ 115c501ca23SJeffrey Hugo struct qaic_manage_trans_activate_from_dev { 116c501ca23SJeffrey Hugo struct qaic_manage_trans_hdr hdr; 117c501ca23SJeffrey Hugo __u32 status; 118c501ca23SJeffrey Hugo __u32 dbc_id; 119c501ca23SJeffrey Hugo __u64 options; 120c501ca23SJeffrey Hugo }; 121c501ca23SJeffrey Hugo 122c501ca23SJeffrey Hugo /** 123c501ca23SJeffrey Hugo * struct qaic_manage_trans_deactivate - Defines a deactivate request. 124c501ca23SJeffrey Hugo * @hdr: In. Header to identify this transaction. 125c501ca23SJeffrey Hugo * @dbc_id: In. Id of assigned DBC. 126c501ca23SJeffrey Hugo * @pad: Structure padding. Must be 0. 127c501ca23SJeffrey Hugo */ 128c501ca23SJeffrey Hugo struct qaic_manage_trans_deactivate { 129c501ca23SJeffrey Hugo struct qaic_manage_trans_hdr hdr; 130c501ca23SJeffrey Hugo __u32 dbc_id; 131c501ca23SJeffrey Hugo __u32 pad; 132c501ca23SJeffrey Hugo }; 133c501ca23SJeffrey Hugo 134c501ca23SJeffrey Hugo /** 135c501ca23SJeffrey Hugo * struct qaic_manage_trans_status_to_dev - Defines a status request. 136c501ca23SJeffrey Hugo * @hdr: In. Header to identify this transaction. 137c501ca23SJeffrey Hugo */ 138c501ca23SJeffrey Hugo struct qaic_manage_trans_status_to_dev { 139c501ca23SJeffrey Hugo struct qaic_manage_trans_hdr hdr; 140c501ca23SJeffrey Hugo }; 141c501ca23SJeffrey Hugo 142c501ca23SJeffrey Hugo /** 143c501ca23SJeffrey Hugo * struct qaic_manage_trans_status_from_dev - Defines a status response. 144c501ca23SJeffrey Hugo * @hdr: Out. Header to identify this transaction. 145c501ca23SJeffrey Hugo * @major: Out. NNC protocol version major number. 146c501ca23SJeffrey Hugo * @minor: Out. NNC protocol version minor number. 147c501ca23SJeffrey Hugo * @status: Out. Return code from device. 148c501ca23SJeffrey Hugo * @status_flags: Out. Flags from device. Bit 0 indicates if CRCs are required. 149c501ca23SJeffrey Hugo */ 150c501ca23SJeffrey Hugo struct qaic_manage_trans_status_from_dev { 151c501ca23SJeffrey Hugo struct qaic_manage_trans_hdr hdr; 152c501ca23SJeffrey Hugo __u16 major; 153c501ca23SJeffrey Hugo __u16 minor; 154c501ca23SJeffrey Hugo __u32 status; 155c501ca23SJeffrey Hugo __u64 status_flags; 156c501ca23SJeffrey Hugo }; 157c501ca23SJeffrey Hugo 158c501ca23SJeffrey Hugo /** 159c501ca23SJeffrey Hugo * struct qaic_manage_msg - Defines a message to the device. 160c501ca23SJeffrey Hugo * @len: In. Length of all the transactions contained within this message. 161c501ca23SJeffrey Hugo * @count: In. Number of transactions in this message. 162c501ca23SJeffrey Hugo * @data: In. Address to an array where the transactions can be found. 163c501ca23SJeffrey Hugo */ 164c501ca23SJeffrey Hugo struct qaic_manage_msg { 165c501ca23SJeffrey Hugo __u32 len; 166c501ca23SJeffrey Hugo __u32 count; 167c501ca23SJeffrey Hugo __u64 data; 168c501ca23SJeffrey Hugo }; 169c501ca23SJeffrey Hugo 170c501ca23SJeffrey Hugo /** 171c501ca23SJeffrey Hugo * struct qaic_create_bo - Defines a request to create a buffer object. 172c501ca23SJeffrey Hugo * @size: In. Size of the buffer in bytes. 173c501ca23SJeffrey Hugo * @handle: Out. GEM handle for the BO. 174c501ca23SJeffrey Hugo * @pad: Structure padding. Must be 0. 175c501ca23SJeffrey Hugo */ 176c501ca23SJeffrey Hugo struct qaic_create_bo { 177c501ca23SJeffrey Hugo __u64 size; 178c501ca23SJeffrey Hugo __u32 handle; 179c501ca23SJeffrey Hugo __u32 pad; 180c501ca23SJeffrey Hugo }; 181c501ca23SJeffrey Hugo 182c501ca23SJeffrey Hugo /** 183c501ca23SJeffrey Hugo * struct qaic_mmap_bo - Defines a request to prepare a BO for mmap(). 184c501ca23SJeffrey Hugo * @handle: In. Handle of the GEM BO to prepare for mmap(). 185c501ca23SJeffrey Hugo * @pad: Structure padding. Must be 0. 186c501ca23SJeffrey Hugo * @offset: Out. Offset value to provide to mmap(). 187c501ca23SJeffrey Hugo */ 188c501ca23SJeffrey Hugo struct qaic_mmap_bo { 189c501ca23SJeffrey Hugo __u32 handle; 190c501ca23SJeffrey Hugo __u32 pad; 191c501ca23SJeffrey Hugo __u64 offset; 192c501ca23SJeffrey Hugo }; 193c501ca23SJeffrey Hugo 194c501ca23SJeffrey Hugo /** 195c501ca23SJeffrey Hugo * struct qaic_sem - Defines a semaphore command for a BO slice. 196c501ca23SJeffrey Hugo * @val: In. Only lower 12 bits are valid. 197c501ca23SJeffrey Hugo * @index: In. Only lower 5 bits are valid. 198c501ca23SJeffrey Hugo * @presync: In. 1 if presync operation, 0 if postsync. 199c501ca23SJeffrey Hugo * @cmd: In. One of QAIC_SEM_*. 200c501ca23SJeffrey Hugo * @flags: In. Bitfield. See QAIC_SEM_INSYNCFENCE and QAIC_SEM_OUTSYNCFENCE 201c501ca23SJeffrey Hugo * @pad: Structure padding. Must be 0. 202c501ca23SJeffrey Hugo */ 203c501ca23SJeffrey Hugo struct qaic_sem { 204c501ca23SJeffrey Hugo __u16 val; 205c501ca23SJeffrey Hugo __u8 index; 206c501ca23SJeffrey Hugo __u8 presync; 207c501ca23SJeffrey Hugo __u8 cmd; 208c501ca23SJeffrey Hugo __u8 flags; 209c501ca23SJeffrey Hugo __u16 pad; 210c501ca23SJeffrey Hugo }; 211c501ca23SJeffrey Hugo 212c501ca23SJeffrey Hugo /** 213c501ca23SJeffrey Hugo * struct qaic_attach_slice_entry - Defines a single BO slice. 214c501ca23SJeffrey Hugo * @size: In. Size of this slice in bytes. 215c501ca23SJeffrey Hugo * @sem0: In. Semaphore command 0. Must be 0 is not valid. 216c501ca23SJeffrey Hugo * @sem1: In. Semaphore command 1. Must be 0 is not valid. 217c501ca23SJeffrey Hugo * @sem2: In. Semaphore command 2. Must be 0 is not valid. 218c501ca23SJeffrey Hugo * @sem3: In. Semaphore command 3. Must be 0 is not valid. 219c501ca23SJeffrey Hugo * @dev_addr: In. Device address this slice pushes to or pulls from. 220c501ca23SJeffrey Hugo * @db_addr: In. Address of the doorbell to ring. 221c501ca23SJeffrey Hugo * @db_data: In. Data to write to the doorbell. 222c501ca23SJeffrey Hugo * @db_len: In. Size of the doorbell data in bits - 32, 16, or 8. 0 is for 223c501ca23SJeffrey Hugo * inactive doorbells. 224c501ca23SJeffrey Hugo * @offset: In. Start of this slice as an offset from the start of the BO. 225c501ca23SJeffrey Hugo */ 226c501ca23SJeffrey Hugo struct qaic_attach_slice_entry { 227c501ca23SJeffrey Hugo __u64 size; 228c501ca23SJeffrey Hugo struct qaic_sem sem0; 229c501ca23SJeffrey Hugo struct qaic_sem sem1; 230c501ca23SJeffrey Hugo struct qaic_sem sem2; 231c501ca23SJeffrey Hugo struct qaic_sem sem3; 232c501ca23SJeffrey Hugo __u64 dev_addr; 233c501ca23SJeffrey Hugo __u64 db_addr; 234c501ca23SJeffrey Hugo __u32 db_data; 235c501ca23SJeffrey Hugo __u32 db_len; 236c501ca23SJeffrey Hugo __u64 offset; 237c501ca23SJeffrey Hugo }; 238c501ca23SJeffrey Hugo 239c501ca23SJeffrey Hugo /** 240c501ca23SJeffrey Hugo * struct qaic_attach_slice_hdr - Defines metadata for a set of BO slices. 241c501ca23SJeffrey Hugo * @count: In. Number of slices for this BO. 242c501ca23SJeffrey Hugo * @dbc_id: In. Associate the sliced BO with this DBC. 243c501ca23SJeffrey Hugo * @handle: In. GEM handle of the BO to slice. 244c501ca23SJeffrey Hugo * @dir: In. Direction of data flow. 1 = DMA_TO_DEVICE, 2 = DMA_FROM_DEVICE 245*0808aef8SPranjal Ramajor Asha Kanojiya * @size: Deprecated. This value is ignored and size of @handle is used instead. 246c501ca23SJeffrey Hugo */ 247c501ca23SJeffrey Hugo struct qaic_attach_slice_hdr { 248c501ca23SJeffrey Hugo __u32 count; 249c501ca23SJeffrey Hugo __u32 dbc_id; 250c501ca23SJeffrey Hugo __u32 handle; 251c501ca23SJeffrey Hugo __u32 dir; 252c501ca23SJeffrey Hugo __u64 size; 253c501ca23SJeffrey Hugo }; 254c501ca23SJeffrey Hugo 255c501ca23SJeffrey Hugo /** 256c501ca23SJeffrey Hugo * struct qaic_attach_slice - Defines a set of BO slices. 257c501ca23SJeffrey Hugo * @hdr: In. Metadata of the set of slices. 258c501ca23SJeffrey Hugo * @data: In. Pointer to an array containing the slice definitions. 259c501ca23SJeffrey Hugo */ 260c501ca23SJeffrey Hugo struct qaic_attach_slice { 261c501ca23SJeffrey Hugo struct qaic_attach_slice_hdr hdr; 262c501ca23SJeffrey Hugo __u64 data; 263c501ca23SJeffrey Hugo }; 264c501ca23SJeffrey Hugo 265c501ca23SJeffrey Hugo /** 266c501ca23SJeffrey Hugo * struct qaic_execute_entry - Defines a BO to submit to the device. 267c501ca23SJeffrey Hugo * @handle: In. GEM handle of the BO to commit to the device. 268c501ca23SJeffrey Hugo * @dir: In. Direction of data. 1 = to device, 2 = from device. 269c501ca23SJeffrey Hugo */ 270c501ca23SJeffrey Hugo struct qaic_execute_entry { 271c501ca23SJeffrey Hugo __u32 handle; 272c501ca23SJeffrey Hugo __u32 dir; 273c501ca23SJeffrey Hugo }; 274c501ca23SJeffrey Hugo 275c501ca23SJeffrey Hugo /** 276c501ca23SJeffrey Hugo * struct qaic_partial_execute_entry - Defines a BO to resize and submit. 277c501ca23SJeffrey Hugo * @handle: In. GEM handle of the BO to commit to the device. 278c501ca23SJeffrey Hugo * @dir: In. Direction of data. 1 = to device, 2 = from device. 2793b511278SPranjal Ramajor Asha Kanojiya * @resize: In. New size of the BO. Must be <= the original BO size. 2803b511278SPranjal Ramajor Asha Kanojiya * @resize as 0 would be interpreted as no DMA transfer is 2813b511278SPranjal Ramajor Asha Kanojiya * involved. 282c501ca23SJeffrey Hugo */ 283c501ca23SJeffrey Hugo struct qaic_partial_execute_entry { 284c501ca23SJeffrey Hugo __u32 handle; 285c501ca23SJeffrey Hugo __u32 dir; 286c501ca23SJeffrey Hugo __u64 resize; 287c501ca23SJeffrey Hugo }; 288c501ca23SJeffrey Hugo 289c501ca23SJeffrey Hugo /** 290c501ca23SJeffrey Hugo * struct qaic_execute_hdr - Defines metadata for BO submission. 291c501ca23SJeffrey Hugo * @count: In. Number of BOs to submit. 292c501ca23SJeffrey Hugo * @dbc_id: In. DBC to submit the BOs on. 293c501ca23SJeffrey Hugo */ 294c501ca23SJeffrey Hugo struct qaic_execute_hdr { 295c501ca23SJeffrey Hugo __u32 count; 296c501ca23SJeffrey Hugo __u32 dbc_id; 297c501ca23SJeffrey Hugo }; 298c501ca23SJeffrey Hugo 299c501ca23SJeffrey Hugo /** 300c501ca23SJeffrey Hugo * struct qaic_execute - Defines a list of BOs to submit to the device. 301c501ca23SJeffrey Hugo * @hdr: In. BO list metadata. 302c501ca23SJeffrey Hugo * @data: In. Pointer to an array of BOs to submit. 303c501ca23SJeffrey Hugo */ 304c501ca23SJeffrey Hugo struct qaic_execute { 305c501ca23SJeffrey Hugo struct qaic_execute_hdr hdr; 306c501ca23SJeffrey Hugo __u64 data; 307c501ca23SJeffrey Hugo }; 308c501ca23SJeffrey Hugo 309c501ca23SJeffrey Hugo /** 310c501ca23SJeffrey Hugo * struct qaic_wait - Defines a blocking wait for BO execution. 311c501ca23SJeffrey Hugo * @handle: In. GEM handle of the BO to wait on. 312c501ca23SJeffrey Hugo * @timeout: In. Maximum time in ms to wait for the BO. 313c501ca23SJeffrey Hugo * @dbc_id: In. DBC the BO is submitted to. 314c501ca23SJeffrey Hugo * @pad: Structure padding. Must be 0. 315c501ca23SJeffrey Hugo */ 316c501ca23SJeffrey Hugo struct qaic_wait { 317c501ca23SJeffrey Hugo __u32 handle; 318c501ca23SJeffrey Hugo __u32 timeout; 319c501ca23SJeffrey Hugo __u32 dbc_id; 320c501ca23SJeffrey Hugo __u32 pad; 321c501ca23SJeffrey Hugo }; 322c501ca23SJeffrey Hugo 323c501ca23SJeffrey Hugo /** 324c501ca23SJeffrey Hugo * struct qaic_perf_stats_hdr - Defines metadata for getting BO perf info. 325c501ca23SJeffrey Hugo * @count: In. Number of BOs requested. 326c501ca23SJeffrey Hugo * @pad: Structure padding. Must be 0. 327c501ca23SJeffrey Hugo * @dbc_id: In. DBC the BO are associated with. 328c501ca23SJeffrey Hugo */ 329c501ca23SJeffrey Hugo struct qaic_perf_stats_hdr { 330c501ca23SJeffrey Hugo __u16 count; 331c501ca23SJeffrey Hugo __u16 pad; 332c501ca23SJeffrey Hugo __u32 dbc_id; 333c501ca23SJeffrey Hugo }; 334c501ca23SJeffrey Hugo 335c501ca23SJeffrey Hugo /** 336c501ca23SJeffrey Hugo * struct qaic_perf_stats - Defines a request for getting BO perf info. 337c501ca23SJeffrey Hugo * @hdr: In. Request metadata 338c501ca23SJeffrey Hugo * @data: In. Pointer to array of stats structures that will receive the data. 339c501ca23SJeffrey Hugo */ 340c501ca23SJeffrey Hugo struct qaic_perf_stats { 341c501ca23SJeffrey Hugo struct qaic_perf_stats_hdr hdr; 342c501ca23SJeffrey Hugo __u64 data; 343c501ca23SJeffrey Hugo }; 344c501ca23SJeffrey Hugo 345c501ca23SJeffrey Hugo /** 346c501ca23SJeffrey Hugo * struct qaic_perf_stats_entry - Defines a BO perf info. 347c501ca23SJeffrey Hugo * @handle: In. GEM handle of the BO to get perf stats for. 348c501ca23SJeffrey Hugo * @queue_level_before: Out. Number of elements in the queue before this BO 349c501ca23SJeffrey Hugo * was submitted. 350c501ca23SJeffrey Hugo * @num_queue_element: Out. Number of elements added to the queue to submit 351c501ca23SJeffrey Hugo * this BO. 352c501ca23SJeffrey Hugo * @submit_latency_us: Out. Time taken by the driver to submit this BO. 353c501ca23SJeffrey Hugo * @device_latency_us: Out. Time taken by the device to execute this BO. 354c501ca23SJeffrey Hugo * @pad: Structure padding. Must be 0. 355c501ca23SJeffrey Hugo */ 356c501ca23SJeffrey Hugo struct qaic_perf_stats_entry { 357c501ca23SJeffrey Hugo __u32 handle; 358c501ca23SJeffrey Hugo __u32 queue_level_before; 359c501ca23SJeffrey Hugo __u32 num_queue_element; 360c501ca23SJeffrey Hugo __u32 submit_latency_us; 361c501ca23SJeffrey Hugo __u32 device_latency_us; 362c501ca23SJeffrey Hugo __u32 pad; 363c501ca23SJeffrey Hugo }; 364c501ca23SJeffrey Hugo 365217b8123SPranjal Ramajor Asha Kanojiya /** 366217b8123SPranjal Ramajor Asha Kanojiya * struct qaic_detach_slice - Detaches slicing configuration from BO. 367217b8123SPranjal Ramajor Asha Kanojiya * @handle: In. GEM handle of the BO to detach slicing configuration. 368217b8123SPranjal Ramajor Asha Kanojiya * @pad: Structure padding. Must be 0. 369217b8123SPranjal Ramajor Asha Kanojiya */ 370217b8123SPranjal Ramajor Asha Kanojiya struct qaic_detach_slice { 371217b8123SPranjal Ramajor Asha Kanojiya __u32 handle; 372217b8123SPranjal Ramajor Asha Kanojiya __u32 pad; 373217b8123SPranjal Ramajor Asha Kanojiya }; 374217b8123SPranjal Ramajor Asha Kanojiya 375c501ca23SJeffrey Hugo #define DRM_QAIC_MANAGE 0x00 376c501ca23SJeffrey Hugo #define DRM_QAIC_CREATE_BO 0x01 377c501ca23SJeffrey Hugo #define DRM_QAIC_MMAP_BO 0x02 378c501ca23SJeffrey Hugo #define DRM_QAIC_ATTACH_SLICE_BO 0x03 379c501ca23SJeffrey Hugo #define DRM_QAIC_EXECUTE_BO 0x04 380c501ca23SJeffrey Hugo #define DRM_QAIC_PARTIAL_EXECUTE_BO 0x05 381c501ca23SJeffrey Hugo #define DRM_QAIC_WAIT_BO 0x06 382c501ca23SJeffrey Hugo #define DRM_QAIC_PERF_STATS_BO 0x07 383217b8123SPranjal Ramajor Asha Kanojiya #define DRM_QAIC_DETACH_SLICE_BO 0x08 384c501ca23SJeffrey Hugo 385c501ca23SJeffrey Hugo #define DRM_IOCTL_QAIC_MANAGE DRM_IOWR(DRM_COMMAND_BASE + DRM_QAIC_MANAGE, struct qaic_manage_msg) 386c501ca23SJeffrey Hugo #define DRM_IOCTL_QAIC_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_QAIC_CREATE_BO, struct qaic_create_bo) 387c501ca23SJeffrey Hugo #define DRM_IOCTL_QAIC_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_QAIC_MMAP_BO, struct qaic_mmap_bo) 388c501ca23SJeffrey Hugo #define DRM_IOCTL_QAIC_ATTACH_SLICE_BO DRM_IOW(DRM_COMMAND_BASE + DRM_QAIC_ATTACH_SLICE_BO, struct qaic_attach_slice) 389c501ca23SJeffrey Hugo #define DRM_IOCTL_QAIC_EXECUTE_BO DRM_IOW(DRM_COMMAND_BASE + DRM_QAIC_EXECUTE_BO, struct qaic_execute) 390c501ca23SJeffrey Hugo #define DRM_IOCTL_QAIC_PARTIAL_EXECUTE_BO DRM_IOW(DRM_COMMAND_BASE + DRM_QAIC_PARTIAL_EXECUTE_BO, struct qaic_execute) 391c501ca23SJeffrey Hugo #define DRM_IOCTL_QAIC_WAIT_BO DRM_IOW(DRM_COMMAND_BASE + DRM_QAIC_WAIT_BO, struct qaic_wait) 392c501ca23SJeffrey Hugo #define DRM_IOCTL_QAIC_PERF_STATS_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_QAIC_PERF_STATS_BO, struct qaic_perf_stats) 393217b8123SPranjal Ramajor Asha Kanojiya #define DRM_IOCTL_QAIC_DETACH_SLICE_BO DRM_IOW(DRM_COMMAND_BASE + DRM_QAIC_DETACH_SLICE_BO, struct qaic_detach_slice) 394c501ca23SJeffrey Hugo 395c501ca23SJeffrey Hugo #if defined(__cplusplus) 396c501ca23SJeffrey Hugo } 397c501ca23SJeffrey Hugo #endif 398c501ca23SJeffrey Hugo 399c501ca23SJeffrey Hugo #endif /* QAIC_ACCEL_H_ */ 400